CN110675088B - Efficient division method for complex tasks of digital twin system - Google Patents
Efficient division method for complex tasks of digital twin system Download PDFInfo
- Publication number
- CN110675088B CN110675088B CN201910966591.0A CN201910966591A CN110675088B CN 110675088 B CN110675088 B CN 110675088B CN 201910966591 A CN201910966591 A CN 201910966591A CN 110675088 B CN110675088 B CN 110675088B
- Authority
- CN
- China
- Prior art keywords
- digital twin
- twin system
- module
- complex task
- division
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06Q—INFORMATION AND COMMUNICATION TECHNOLOGY [ICT] SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES; SYSTEMS OR METHODS SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES, NOT OTHERWISE PROVIDED FOR
- G06Q10/00—Administration; Management
- G06Q10/06—Resources, workflows, human or project management; Enterprise or organisation planning; Enterprise or organisation modelling
- G06Q10/063—Operations research, analysis or management
- G06Q10/0631—Resource planning, allocation, distributing or scheduling for enterprises or organisations
- G06Q10/06312—Adjustment or analysis of established resource schedule, e.g. resource or task levelling, or dynamic rescheduling
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N3/00—Computing arrangements based on biological models
- G06N3/12—Computing arrangements based on biological models using genetic models
- G06N3/126—Evolutionary algorithms, e.g. genetic algorithms or genetic programming
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06Q—INFORMATION AND COMMUNICATION TECHNOLOGY [ICT] SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES; SYSTEMS OR METHODS SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES, NOT OTHERWISE PROVIDED FOR
- G06Q50/00—Systems or methods specially adapted for specific business sectors, e.g. utilities or tourism
- G06Q50/04—Manufacturing
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
- Y02P90/30—Computing systems specially adapted for manufacturing
Abstract
The invention discloses a method for efficiently dividing complex tasks of a digital twin system, which is suitable for a heterogeneous multi-core SoC environment designed by Xilinx ZYNQ-7000SoC and comprises the following steps: designing a complex task division early-stage module of a digital twin system, wherein the module completes the overall execution time minimization solution of a task based on a classical genetic algorithm; designing a complex task division later-stage module of the digital twin system, wherein the module completes the overall execution time minimization solution of the task based on a greedy algorithm; designing a complex task division scheduling module 1 of the digital twin system, wherein the module finishes the stopping of an early-stage module and the starting of a later-stage module; and designing a complex task division scheduling module 2 of the digital twin system, determining whether to perform task division iteration again or not by monitoring the iteration times of the modules at the later stage, and calculating and outputting an optimal division scheme. The invention combines the classical genetic algorithm and the greedy algorithm, ensures the global and local optimizing capability of task division, and improves the complex task division efficiency of the digital twin system.
Description
Technical Field
The invention belongs to the field of electronic engineering and computer science, and particularly relates to a method for efficiently dividing complex tasks of a digital twin system.
Background
Intelligent manufacturing becomes the key development field of China and even the world, and how to realize fault health management and control, energy consumption management and production line process simulation prediction of manufacturing bottom equipment is the key for improving the intelligent manufacturing level. Digital twin (also called digital twins) establishes complete mapping of a virtual space and a physical entity in a digital mode, and realizes interaction and fusion of a physical world and an information world through virtual-real interaction, simulation prediction of the physical entity by the virtual space and complete mapping of the running state of the physical entity in the virtual space. Internationally, Rockschidman, Inc. lists digital twins as the first 6 top technologies in future national defense and aerospace industry in 11 months in 2017; in China, the Chinese science and agreement of 12 months in 2017 lists digital twins as one of ten scientific and technological advances in world intelligent manufacturing, and the government of China takes digital twins cities as a necessary way and an effective means for realizing smart cities. It can be seen that the digital twin is widely researched and applied in the fields of intelligent manufacturing, urban construction, military industry and national defense and the like.
The implementation of the digital twin technology includes not only controlling real and real, but also simulating and predicting physical entities in a virtual space based on a certain rule, which necessarily includes solving complex tasks. For solving complex tasks in a digital twin system, firstly, precise division of the complex tasks needs to be completed, and the problems that which tasks are suitable for being executed on hardware (such as FPGA) and which tasks are suitable for being executed on software (such as ARM) are involved.
The ZYNO-7000SoC of Xilinx corporation integrates FPGA and ARM, based on the FPGA and ARM, a heterogeneous multi-core SoC environment can be constructed, the heterogeneous multi-core SoC environment comprises an FPGA unit, a MicroBlaze core and an ARM core, different cores process tasks of respective holding, and the heterogeneous multi-core SoC environment is suitable for division and solution of complex tasks of a digital twin system.
For the partition solution of complex tasks, the traditional method generally only starts from the global optimum or the local optimum of the solution, and omits the requirement of the partition solution on considering both the global optimum and the local optimum. Therefore, aiming at the complex task partitioning requirement of a digital twin system in a heterogeneous multi-core SoC environment, the invention discloses a high-efficiency partitioning method for the complex task of the digital twin system, which is suitable for the heterogeneous multi-core SoC environment designed by ZYNQ-7000SoC, covers the design of an early-stage module, a later-stage module and a scheduling module of the complex task partitioning of the digital twin system, adopts a mode of combining a classical genetic algorithm and a greedy algorithm, ensures the global and local optimizing capability of the task partitioning, and improves the complex task partitioning efficiency of the digital twin system.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: the method covers the design of an early stage module, a later stage module and a scheduling module of the complex task division of the digital twin system, adopts a mode of combining a classical genetic algorithm and a greedy algorithm, ensures the global and local optimizing capability of the task division, and improves the complex task division efficiency of the digital twin system.
The technical problem to be solved by the invention is realized by adopting the following technical scheme: a method for efficiently dividing complex tasks of a digital twin system is suitable for a heterogeneous multi-core SoC environment designed by Xilinx ZYNQ-7000SoC, and the heterogeneous multi-core SoC environment at least comprises an FPGA unit, a MicroBlaze core unit and two ARM core units. The method comprises the following steps:
step (1), designing a complex task division early-stage module of a digital twin system, wherein the module completes the overall task execution time minimum solution based on a genetic algorithm, and the implementation is as follows:
firstly, assuming that the number of complex tasks of a digital twin system is n, setting a set F [ k ] to represent an initial partitioning scheme, wherein k is equal to 3 n; initializing T to infinity, and initializing iteration times i to 0;
selecting, crossing and varying a division scheme based on a genetic algorithm, wherein an objective function is the minimization of the overall execution time of the task;
③ calculate a set F [ k ]]The overall execution time T of each schemejWhere j represents the set F [ k ]]The serial numbers of each scheme in the (1), and j is less than or equal to k;
④ when TjWhen the temperature is more than T: update set F [ k ]]I.e. in the set F [ k ]]When k equals 1, ③ in step (4) is executed;
⑤ when TjWhen T is less than or equal to T: setting the value of T to TjSet F [ k ]]The change is not changed;
step (2), designing a complex task division scheduling module 1 of the digital twin system, wherein the complex task division scheduling module stops a complex task division early-stage module of the digital twin system and starts a complex task division later-stage module of the digital twin system, and the complex task division scheduling module is specifically realized as follows:
when the number n of complex tasks of the digital twin system is more than 20: if the iteration times i are larger than 5n, ending the operation of the early-stage module of the complex task division of the digital twin system, and starting the late-stage module of the complex task division of the digital twin system; if the iteration frequency i is less than or equal to 5n, returning to the second step in the step (1), and adding 1 to the iteration frequency i;
② when the number n of complex tasks of digital twin system is less than or equal to 20, if the iteration number i is more than n2Finishing the operation of the early-stage module of the complex task division of the digital twin system, and starting the late-stage module of the complex task division of the digital twin system; if the number of iterations i is less than or equal to n2(ii)/2, returning to ② in the step (1), and adding 1 to the iteration number i;
and (3) designing a complex task division later-stage module of the digital twin system, wherein the module completes the minimum solution of the overall execution time of the task based on a greedy algorithm, and the detailed implementation is as follows:
comparing the integral execution time of two adjacent partition schemes in a set F [ k ], and deleting the partition scheme with larger execution time; comparing the overall execution time of two adjacent division schemes, namely comparing the overall execution time of a first scheme and a second scheme, and the overall execution time of a third scheme and a fourth scheme, and so on, and directly deleting the kth scheme when k is an odd number;
executing the third step in the step (4) when k is equal to 1; otherwise, executing the step (4);
and (4) designing a complex task division scheduling module 2 of the digital twin system, wherein the complex task division scheduling module 2 determines whether to perform task division iteration again or not by monitoring the iteration times of a module at the late stage of complex task division of the digital twin system, and calculates and outputs an optimal division scheme, and the method is specifically realized as follows:
when the number n of complex tasks of the digital twin system is more than 20: if the iteration times i is larger than 10n, ending the operation of the complex task division later-stage module of the digital twin system, and outputting a division scheme set F [ k ] at the moment, wherein k is smaller than 3 n; if the iteration frequency i is less than or equal to 10n, returning to the step (3), and adding 1 to the iteration frequency i;
② when the number n of complex tasks of digital twin system is less than or equal to 20, if the iteration number i is more than n2Ending the operation of the digital twin system complex task division later module, and outputting the division scheme set F [ k ] at the moment]And k is less than 3 n; if the number of iterations i is less than or equal to n2Returning to ① in step (3), and adding 1 to the iteration number i;
and thirdly, calculating the execution time of each scheme in the scheme set F [ k ] at the moment, and taking the scheme with the minimum overall execution time as a final scheme.
The method is suitable for a heterogeneous multi-core SoC environment designed by ZYNQ-7000SoC, and the heterogeneous multi-core SoC environment at least comprises an FPGA unit, a MicroBlaze core unit and two ARM core units.
One ARM core unit of two ARM core units in the heterogeneous multi-core SoC environment is marked as an ARM core 1, and the other ARM core unit is marked as an ARM core 2;
the digital twin system complex task division scheduling module 1 and the digital twin system complex task division scheduling module 2 operate in an ARM core 2 in a heterogeneous multi-core SoC environment to complete scheduling in the complex task division process;
the early-stage complex task division module and the later-stage complex task division module of the digital twin system run in an FPGA (field programmable gate array), a MicroBlaze core and an ARM (advanced RISC machine) core 1 in a heterogeneous multi-core SoC (system on chip) environment to complete the execution after the complex task division.
Compared with the prior art, the invention has the advantages that:
(1) the division and solution of complex tasks of a digital twin system are realized based on a heterogeneous multi-core SoC environment, so that the tasks with different characteristics can be executed on corresponding software and hardware (FPGA or MicroBlaze/ARM core), and the overall efficiency of task execution is improved;
(2) the method provided by the invention covers the design of an early-stage module, a later-stage module and a scheduling module of the complex task division of the digital twin system, adopts a mode of combining a classical genetic algorithm and a greedy algorithm, ensures the global and local optimizing capability of the task division, and improves the complex task division efficiency of the digital twin system.
Drawings
FIG. 1 is a block flow diagram of the method of the present invention;
fig. 2 is a block diagram of a heterogeneous multi-core SoC environment according to the present invention.
Detailed Description
The present invention is described in further detail below with reference to the attached drawings.
The invention relates to a method for efficiently dividing complex tasks of a digital twin system, which is suitable for a heterogeneous multi-core SoC environment designed by ZYNQ-7000SoC, wherein the heterogeneous multi-core SoC environment at least comprises an FPGA unit, a MicroBlaze core unit and two ARM core units. Aiming at the complex task division requirement of a digital twin system in a heterogeneous multi-core SoC environment, the method covers the design of an early-stage module, a later-stage module and a scheduling module of the complex task division of the digital twin system, adopts a mode of combining a classical genetic algorithm and a greedy algorithm, ensures the global and local optimizing capability of the task division, and improves the complex task division efficiency of the digital twin system.
The flow diagram of the invention is shown in fig. 1, the structural diagram of the heterogeneous multi-core SoC environment of the invention is shown in fig. 2, and the specific implementation is as follows:
step (1), defining complex task attributes of a digital twin system, wherein the attribute definitions can comprise execution time and loading time of tasks on hardware (such as FPGA), execution time and loading time on software (such as MicroBlaze core and ARM core), and the like;
step (2), dividing the complex task of the digital twin system into mathematical codes, wherein the tasks can be encoded into binary '1' by executing on hardware (such as FPGA) and binary '0' by executing on software (such as MicroBlaze core and ARM core), so that for each division scheme, the mathematical expression is as a multi-element array of {0, 1, 1, …, 0, 0, 1 };
step (3) fig. 1 shows a digital twin system complex task division early-stage module (main execution step), which specifically comprises the following steps:
firstly, assuming that the number of complex tasks of a digital twin system is n, setting a set F [ k ] to represent an initial partitioning scheme, wherein k is equal to 3 n; initializing T to infinity, and initializing iteration times i to 0;
secondly, selecting, crossing and varying a partitioning scheme based on a classical genetic algorithm, wherein an objective function is the minimization of the overall execution time of the task;
③ calculate a set F [ k ]]The overall execution time T of each schemejWhere j represents the set F [ k ]]The serial numbers of each scheme in the (1), and j is less than or equal to k;
④ when TjWhen the temperature is more than T: update set F [ k ]]I.e. in the set F [ k ]]When k equals 1, ③ in step (6) is executed;
⑤ when TjWhen T is less than or equal to T: setting the value of T to TjSet F [ k ]]The change is not changed;
step (4) fig. 1 shows 2 a complex task division scheduling module 1 (main execution step) of the digital twin system, which is specifically implemented as follows:
when the number n of complex tasks of the digital twin system is more than 20: if the iteration times i are larger than 5n, ending the operation of the early-stage module of the complex task division of the digital twin system, and starting the late-stage module of the complex task division of the digital twin system; if the iteration frequency i is less than or equal to 5n, returning to the step II in the step (3), and adding 1 to the iteration frequency i;
② when the number n of complex tasks of digital twin system is less than or equal to 20, if the iteration number i is more than n2Finishing the operation of the early-stage module of the complex task division of the digital twin system, and starting the late-stage module of the complex task division of the digital twin system; if the number of iterations i is less than or equal to n2(ii)/2, return to ② in (3) and increment the number of iterations i by 1;
step (5) fig. 1 shows 3 a complex task division later-stage module (a main execution step) for designing a digital twin system, which is specifically realized as follows:
comparing the overall execution time of two adjacent division schemes in a set F [ k ] (namely comparing the overall execution time of a first scheme and a second scheme, the overall execution time of a third scheme and a fourth scheme, and so on, and directly deleting the kth scheme when k is an odd number), and deleting the division scheme with larger execution time;
executing the third step in the step (6) when k is equal to 1; otherwise, executing the step (6);
step (6) fig. 1 shows 4 that the complex task division scheduling module 2 of the digital twin system is designed (mainly executed steps), and the following steps are specifically realized:
when the number n of complex tasks of the digital twin system is more than 20: if the iteration times i is larger than 10n, ending the operation of the complex task division later-stage module of the digital twin system, and outputting a division scheme set F [ k ] at the moment, wherein k is smaller than 3 n; if the iteration frequency i is less than or equal to 10n, returning to the step (5), and adding 1 to the iteration frequency i;
② when the number n of complex tasks of digital twin system is less than or equal to 20, if the iteration number i is more than n2Ending the operation of the digital twin system complex task division later module, and outputting the division scheme set F [ k ] at the moment]And k is less than 3 n; if the number of iterations i is less than or equal to n2Returning to ① in (5) and adding 1 to the iteration number i;
and thirdly, calculating the execution time of each scheme in the scheme set F [ k ] at the moment, and taking the scheme with the minimum overall execution time as a final scheme.
(7) As shown in fig. 2, the digital twin system complex task division scheduling module 1 and the digital twin system complex task division scheduling module 2 operate in an ARM core 2 in a heterogeneous multi-core SoC environment, and mainly complete scheduling in the complex task division process; the early-stage complex task division module and the later-stage complex task division module of the digital twin system run in an FPGA (field programmable gate array), a MicroBlaze core and an ARM (advanced RISC machine) core 1 in a heterogeneous multi-core SoC (system on chip) environment and mainly complete the execution after the complex task division.
In conclusion, the invention discloses a method for efficiently dividing complex tasks of a digital twin system, which comprises a digital twin system complex task division early-stage module, a digital twin system complex task division later-stage module, a digital twin system complex task division scheduling module 1 and a digital twin system complex task division scheduling module 2, wherein a classical genetic algorithm and a greedy algorithm are combined, so that the global and local optimizing capability of task division is ensured, and the complex task division efficiency of the digital twin system is improved.
Those skilled in the art will appreciate that the invention may be practiced without these specific details.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.
Claims (3)
1. A high-efficiency division method for complex tasks of a digital twin system is suitable for a heterogeneous multi-core SoC environment, and the heterogeneous multi-core SoC environment at least comprises an FPGA unit, a MicroBlaze core unit and two ARM core units, and is characterized by comprising the following steps:
step (1), designing a complex task division early-stage module of a digital twin system, wherein the module completes the overall task execution time minimum solution based on a genetic algorithm, and the implementation is as follows:
firstly, assuming that the number of complex tasks of a digital twin system is n, setting a set F [ k ] to represent an initial partitioning scheme, wherein k is equal to 3 n; initializing T to infinity, and initializing iteration times i to 0;
selecting, crossing and varying a division scheme based on a genetic algorithm, wherein an objective function is the minimization of the overall execution time of the task;
③ calculate a set F [ k ]]The overall execution time T of each schemejWhere j represents the set F [ k ]]The serial numbers of each scheme in the (1), and j is less than or equal to k;
④ when TjWhen the temperature is more than T: update set F [ k ]]I.e. in the set F [ k ]]When k equals 1, ③ in step (4) is executed;
⑤ when TjWhen T is less than or equal to T: setting the value of T to TjSet F [ k ]]The change is not changed;
step (2), designing a complex task division scheduling module 1 of the digital twin system, wherein the complex task division scheduling module 1 stops a complex task division early-stage module of the digital twin system and starts a complex task division later-stage module of the digital twin system, and the method is specifically realized as follows:
when the number n of complex tasks of the digital twin system is more than 20: if the iteration times i are larger than 5n, ending the operation of the early-stage module of the complex task division of the digital twin system, and starting the late-stage module of the complex task division of the digital twin system; if the iteration frequency i is less than or equal to 5n, returning to the second step in the step (1), and adding 1 to the iteration frequency i;
② when the number n of complex tasks of digital twin system is less than or equal to 20, if the iteration number i is more than n2Finishing the operation of the early-stage module of the complex task division of the digital twin system, and starting the late-stage module of the complex task division of the digital twin system; if the number of iterations i is less than or equal to n2(ii)/2, returning to ② in the step (1), and adding 1 to the iteration number i;
and (3) designing a complex task division later-stage module of the digital twin system, wherein the module completes the minimum solution of the overall execution time of the task based on a greedy algorithm, and the detailed implementation is as follows:
comparing the integral execution time of two adjacent partition schemes in a set F [ k ], and deleting the partition scheme with larger execution time; comparing the overall execution time of two adjacent division schemes, namely comparing the overall execution time of a first scheme and a second scheme, and the overall execution time of a third scheme and a fourth scheme, and so on, and directly deleting the kth scheme when k is an odd number;
executing the third step in the step (4) when k is equal to 1; otherwise, executing the step (4);
and (4) designing a complex task division scheduling module 2 of the digital twin system, wherein the complex task division scheduling module 2 determines whether to perform task division iteration again or not by monitoring the iteration times of a module at the late stage of complex task division of the digital twin system, and calculates and outputs an optimal division scheme, and the method is specifically realized as follows:
when the number n of complex tasks of the digital twin system is more than 20: if the iteration times i is larger than 10n, ending the operation of the complex task division later-stage module of the digital twin system, and outputting a division scheme set F [ k ] at the moment, wherein k is smaller than 3 n; if the iteration frequency i is less than or equal to 10n, returning to the step (3), and adding 1 to the iteration frequency i;
② when the number n of complex tasks of digital twin system is less than or equal to 20, if the iteration number i is more than n2Ending the operation of the digital twin system complex task division later module, and outputting the division scheme set F [ k ] at the moment]And k is less than 3 n; if the number of iterations i is less than or equal to n2Returning to ① in step (3), and adding 1 to the iteration number i;
and thirdly, calculating the execution time of each scheme in the scheme set F [ k ] at the moment, and taking the scheme with the minimum overall execution time as a final scheme.
2. A method for efficient partitioning of a complex task for a digital twin system as defined in claim 1, wherein:
the method is suitable for a heterogeneous multi-core SoC environment designed by ZYNQ-7000SoC, and the heterogeneous multi-core SoC environment at least comprises an FPGA unit, a MicroBlaze core unit and two ARM core units.
3. A method for efficient partitioning of a complex task for a digital twin system as defined in claim 1, wherein: one ARM core unit of two ARM core units in the heterogeneous multi-core SoC environment is marked as an ARM core 1, and the other ARM core unit is marked as an ARM core 2;
the digital twin system complex task division scheduling module 1 and the digital twin system complex task division scheduling module 2 operate in an ARM core 2 in a heterogeneous multi-core SoC environment to complete scheduling in the complex task division process;
the early-stage complex task division module and the later-stage complex task division module of the digital twin system run in an FPGA (field programmable gate array), a MicroBlaze core and an ARM (advanced RISC machine) core 1 in a heterogeneous multi-core SoC (system on chip) environment to complete the execution after the complex task division.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910966591.0A CN110675088B (en) | 2019-10-12 | 2019-10-12 | Efficient division method for complex tasks of digital twin system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910966591.0A CN110675088B (en) | 2019-10-12 | 2019-10-12 | Efficient division method for complex tasks of digital twin system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110675088A CN110675088A (en) | 2020-01-10 |
| CN110675088B true CN110675088B (en) | 2020-10-09 |
Family
ID=69081747
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910966591.0A Active CN110675088B (en) | 2019-10-12 | 2019-10-12 | Efficient division method for complex tasks of digital twin system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110675088B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112306658A (en) * | 2020-10-31 | 2021-02-02 | 贵州电网有限责任公司 | Digital twin application management scheduling method for multi-energy system |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107133088A (en) * | 2017-04-19 | 2017-09-05 | 武汉科技大学 | A kind of multiple nucleus system method for scheduling task based on particle cluster algorithm |
| CN108196953A (en) * | 2017-12-28 | 2018-06-22 | 北京航空航天大学 | A kind of heterogeneous polynuclear parallel processing apparatus and method towards isomerous multi-source big data |
| CN109189205A (en) * | 2018-09-30 | 2019-01-11 | 武汉理工大学 | A kind of heterogeneous polynuclear embedded real time system energy optimization dispatching method |
| CN110209478A (en) * | 2019-05-16 | 2019-09-06 | 重庆邮电大学 | A kind of heterogeneous polynuclear system on chip method for scheduling task and device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10496436B2 (en) * | 2018-01-30 | 2019-12-03 | Pusan National University Industry-University Cooperation Foundation | Method and apparatus for automatically scheduling jobs in computer numerical control machines using machine learning approaches |
-
2019
- 2019-10-12 CN CN201910966591.0A patent/CN110675088B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107133088A (en) * | 2017-04-19 | 2017-09-05 | 武汉科技大学 | A kind of multiple nucleus system method for scheduling task based on particle cluster algorithm |
| CN108196953A (en) * | 2017-12-28 | 2018-06-22 | 北京航空航天大学 | A kind of heterogeneous polynuclear parallel processing apparatus and method towards isomerous multi-source big data |
| CN109189205A (en) * | 2018-09-30 | 2019-01-11 | 武汉理工大学 | A kind of heterogeneous polynuclear embedded real time system energy optimization dispatching method |
| CN110209478A (en) * | 2019-05-16 | 2019-09-06 | 重庆邮电大学 | A kind of heterogeneous polynuclear system on chip method for scheduling task and device |
Non-Patent Citations (2)
| Title |
|---|
| 异构多核系统任务调度算法研究;赵国亮;《计算机工程与设计》;20140930;第35卷(第9期);3099-3104 * |
| 面向异构多核平台的两段式多任务调度算法研究;赵茂行;《控制工程》;20181231;第25卷(第12期);2140-2145 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN110675088A (en) | 2020-01-10 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| Fan et al. | DAPPLE: A pipelined data parallel approach for training large models | |
| CN102193830B (en) | Many-core environment-oriented division mapping/reduction parallel programming model | |
| CN102624865B (en) | Cluster load prediction method and distributed cluster management system | |
| Wolinski et al. | Automatic selection of application-specific reconfigurable processor extensions | |
| CN110675088B (en) | Efficient division method for complex tasks of digital twin system | |
| CN103942081A (en) | Method for generating IL instruction lists of PLC ladder diagrams | |
| Huang et al. | BRCE: bi-roles co-evolution for energy-efficient distributed heterogeneous permutation flow shop scheduling with flexible machine speed | |
| Liang et al. | Hybrid algorithm based on genetic simulated annealing algorithm for complex multiproduct scheduling problem with zero-wait constraint | |
| CN102750428B (en) | Water supply network node hydraulic computation equation parallel algorithm regional construction method | |
| Deniziak et al. | Hardware/software co-synthesis of distributed embedded systems using genetic programming | |
| CN102509177B (en) | Locally weighted linear regression projection operation method based on cloud platform | |
| CN103593220A (en) | OPENCL compilation | |
| CN105243238A (en) | Integrated quick product iteration forming device and method | |
| CN115328551A (en) | Microprocessor architecture design method and system based on operator | |
| CN103942195A (en) | Data processing system and data processing method | |
| Xie et al. | A novel conformable fractional nonlinear grey Bernoulli model and its application | |
| Wang et al. | An estimation of distribution algorithm for the flexible job-shop scheduling problem | |
| CN104182909A (en) | Multi-core parallel successive approximation method of hydropower system optimal scheduling | |
| CN113012760A (en) | FPGA-based gene sequence assembly algorithm calculation acceleration method | |
| CN105676995A (en) | Method for achieving low power consumption of three-dimensional measurement chip | |
| CN109710314A (en) | A method of based on graph structure distributed parallel mode construction figure | |
| Wang et al. | A new scheme for cache optimization based on cluster computing framework spark | |
| Jarrah et al. | Optimized parallel architecture of evolutionary neural network for mass spectrometry data processing | |
| CN103246564B (en) | A kind of large-scale virtual machine fast transferring decision-making method of facing cloud Data centre | |
| Chen et al. | Graph-OPU: A Highly Integrated FPGA-Based Overlay Processor for Graph Neural Networks |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |