CN108183615A - A kind of voltage sampling circuit applied to primary side feedback formula flyback converter - Google Patents
A kind of voltage sampling circuit applied to primary side feedback formula flyback converter Download PDFInfo
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- CN108183615A CN108183615A CN201810061866.1A CN201810061866A CN108183615A CN 108183615 A CN108183615 A CN 108183615A CN 201810061866 A CN201810061866 A CN 201810061866A CN 108183615 A CN108183615 A CN 108183615A
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
- H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
- H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
- H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
- H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/94—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the way in which the control signals are generated
- H03K17/96—Touch switches
- H03K17/962—Capacitive touch switches
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Abstract
A kind of voltage sampling circuit applied to primary side feedback formula flyback converter belongs to power electronics field.Including the sampling unit in parallel of sampling control signal generation circuit, sampled signal gating circuit and at least two, sampling unit includes sampling switch, sampling holding capacitor and transmitting switch, sampling switch and power stage signal to be sampled is transmitted to sampling holding capacitor；Sample holding capacitor store sampled voltage；Transmitting switch exports suitable sampled voltage；Sampling control signal generation circuit controls the sampling switch in sampling unit to sequentially turn on respectively for generating control signal so that sampling holding capacitor stores corresponding sampled voltage；Sampled signal gating circuit judges that system is operated in CCM or DCM patterns, generates gating signal and the transmitting switch in corresponding sampling unit is controlled to be connected, will be sent out closest to the sampled value of actual value.The circuit structure of the present invention is simple, and sampling precision is higher, and can be worked normally under continuous current mode CCM and discontinuous conduct mode DCM.
Description
Technical field
The invention belongs to power electronics fields, are related to a kind of voltage applied to primary side feedback formula flyback converter and adopt
Sample circuit.
Background technology
Flyback converter is since it can realize boosting and decompression simultaneously, and can realize electrical isolation etc. between outputting and inputting
Advantage is widely applied.Primary side feedback technology detects output voltage by adding an auxiliary winding on the transformer
Variation, voltage sample precision is high, can reach higher output accuracy, faster dynamic response.Wherein high-precision voltage sample
Key is the searching of sampled point, and during due to primary side energy transmission to secondary side, secondary side electric current flows through secondary side rectifier diode can be
Apparent pressure drop is generated on diode, so as to influence the accuracy of sampled voltage.In order to improve sampling precision in diode
It is sampled during electric current very little, therefore, primary side feedback formula flyback converter is often operated in discontinuous conduct mode DCM when working normally.
Digital control method can provide higher sampling precision, but circuit structure is often extremely complex.The side of simulation
Method circuit structure is simple, but is extremely difficult to very high precision.On the other hand, it is continuous to be likely to be at electric current when flyback converter starts
Pattern CCM, therefore sample circuit needs to work under continuous current mode CCM and discontinuous conduct mode DCM both patterns.
Invention content
The problem to be solved in the present invention：First, higher sampling precision is provided with relatively simple structure；Second is that it needs
It can work under CCM and DCM both of which.In view of the above-mentioned problems, the present invention proposes a kind of high-accuracy voltage sample circuit, application
In primary side feedback formula flyback converter, sample to obtain sampled value, and correspondence system is work successively by least two sampling modules
Make to export the sampled value closest to actual value respectively in continuous current mode CCM or discontinuous conduct mode DCM,
The technical scheme is that：
A kind of voltage sampling circuit applied to primary side feedback formula flyback converter generates electricity including sampling control signal
The sampling unit in parallel of road, sampled signal gating circuit and at least two,
The sampling unit includes sampling switch, sampling holding capacitor and transmitting switch, the sampling switch and transmission and opens
Series connection is closed, for series connection point by being grounded after the sampling holding capacitor, the other end of the sampling switch is single as the sampling
The input terminal of member, the output terminal of the other end of the transmitting switch as the sampling unit；
The input terminal of each sampling unit is connected and is used as the input terminal of the voltage sampling circuit, output terminal phase
Connect and be used as the output terminal of the voltage sampling circuit；
The sampling control signal generation circuit controls signal to control the sampling in each sampling unit respectively for generating
Switch, sequentially turns on the sampling switch；
The sampled signal gating circuit is used to generating gating signal controls transmitting switch in each sampling unit respectively,
It to be connected so that only there are one corresponding transmitting switches in a sampling period.
Specifically, there are three the sampling units, the first sampling unit includes the first sampling switch S1, the first sampling is kept
Signal at the series connection point of capacitance C1 and the first transmitting switch P1, the first sampling switch S1 and the first transmitting switch P1 is adopted for first
Sample signal VSENSE1；Second sampling unit includes the second sampling switch S2, the second sampling holding capacitor C2 and the second transmitting switch
Signal at the series connection point of P2, the second sampling switch S2 and the second transmitting switch P2 is the second sampled signal VSENSE2；Third samples
Unit includes third sampling switch S3, third sampling holding capacitor C3 and third transmitting switch P3, third sampling switch S3 and the
Signal at the series connection point of three transmitting switch P3 is third sampled signal VSENSE3。
Specifically, the sampling control signal generation circuit includes three frequency division module, first comparator COMP1, the second ratio
Compared with device COMP2, third comparator COMP3, the one or two input and door AND21, the two or two input and door AND22, the three or two input
With door AND23, the four or two input and door AND24, the five or two input and door AND25, the six or two input and door AND26, the one or four
Input and door AND41, the first d type flip flop D1, the second d type flip flop D2, third d type flip flop D3, NMOS tube MN, capacitance C4, electric current
Source I and the first phase inverter INV1,
Three frequency division module includes an input terminal and three output terminals, and input terminal connects sampling frequency signal SH_clk,
Three of them output terminal connects the four or two input and door AND24, the five or two input and the inputs of door AND25 and the six or two and door respectively
The first input end of AND26；
The grid of NMOS tube MN connects the input terminal of the first phase inverter INV1 and connects the primary side feedback formula inverse-excitation converting
The grid drive signal D of primary side power tube in deviceRIVE, drain electrode is respectively by connecting power supply potential and passing through capacitance after current source I
It is grounded after C4, source electrode ground connection；
First sampled signal VSENSE1The negative input and third comparator COMP3 of connection first comparator COMP1 is just
To input terminal, the second sampled signal VSENSE2Connect the positive input and the second comparator COMP2 of first comparator COMP1
Negative input, third sampled signal VSENSE3Connect the positive input of the second comparator COMP2 and third comparator COMP3
Negative input, the output terminal of first comparator COMP1, the second comparator COMP2 and third comparator COMP3 connects respectively
One or two input and door AND21, the two or two input and the inputs of door AND22 and the three or two and the first input end of door AND23, first
Two inputs connect NMOS with door AND21, the two or two input with the inputs of door AND22 and the three or two with the second input terminal of door AND23
The drain electrode of pipe MN；
The D input terminals of first d type flip flop D1, the second d type flip flop D2 and third d type flip flop D3 are all connected with power supply potential,
Input end of clock connects the one or two input and door AND21, the two or two input and the inputs of door AND22 and the three or two and door respectively
The output terminal of AND23,Output terminal connects the one or four input and the first input end of door AND41, the second input terminal and the respectively
Three input terminals；
One or four input connect the output terminal of the first phase inverter INV1 with the 4th input terminal of door AND41, and output terminal connects
Connect the four or two input and door AND24, the five or two input and the inputs of door AND25 and the six or two and the second input terminal of door AND26；
Four or two input and door AND24, the five or two input and the inputs of door AND25 and the six or two and the output terminal of door AND26
Output first control signal V respectivelyS1, second control signal VS2With third control signal VS3First sampling is controlled to open respectively
Close S1, the second sampling switch S2 and third sampling switch S3.
Specifically, the sampled signal gating circuit includes four d flip-flop D4, the 5th d type flip flop D5, the second phase inverter
INV2, third phase inverter INV3, the 4th phase inverter INV4, the 5th phase inverter INV5, hex inverter INV6, the seven or two input with
Door AND27, the eight or two input and door AND28, the one or three input and door AND31, the two or three are inputted and door AND32, the two or four defeated
Enter and door AND42, the three or four input and door AND43, two inputs or door OR2, three inputs or door OR3, XOR gate XOR and same or door
XNOR,
The D input terminals connection power supply potential of four d flip-flop D4, input end of clock connection first control signal VS1, Q
The seven or two input of output terminal connection and the first input end of door AND27；
The D input terminals connection ground potential of 5th d type flip flop D5, input end of clock connection second control signal VS2, Q is defeated
The eight or two input of outlet connection and the first input end of door AND28；
The input terminal connection third control signal V of second phase inverter INV2S3, output terminal connection four d flip-flop D4 and
The set end of 5th d type flip flop D5；
Three input terminals of three inputs or door OR3 connect the first D in the sampling control signal generation circuit and trigger respectively
The Q output of device D1, the second d type flip flop D2 and third d type flip flop D3, the input of output terminal connection third phase inverter INV3
End；
The one or four input connects the in the sampling control signal generation circuit after being negated with the output end signal of door AND41
Seven or two inputs and the inputs of door AND27 and the eight or two and the second input terminal of door AND28；
Seven or two input connect same or door XNOR first input end, hex inverter INV6 with the output terminal of door AND27
Input terminal, the two or three input and the inputs of door AND32 and the two or four and the first input end of door AND42；
Eight or two input connect the first input end of XOR gate XOR, the 4th phase inverter INV4 with the output terminal of door AND28
Input terminal, the one or three input and the inputs of door AND31 and the three or four and the first input end of door AND43；
The second input terminal of the output terminal connection XOR gate XOR of third phase inverter INV3, same or door XNOR the second input
End, the input terminal of the 5th phase inverter INV5 and the three or four input and the second input terminal of door AND43；
Clock signal Clk connections the one or three input with door AND31, the two or three input with door AND32 and the two or four input with
The second input terminal of door AND42 and the three or four input and the third input terminal of door AND43, the clock signal Clk with it is described
Primary side feedback formula flyback converter switching frequency is consistent；
One or three input connect with the third input terminal of door AND31 together or the output terminal of door XNOR, output terminal export the
One gating signal VP1；
Two or three input connect the output terminal of XOR gate XOR, output terminal output second with the third input terminal of door AND32
Gating signal VP2；
Two or four input connect the output terminal of the 4th phase inverter INV4, the 4th input with the third input terminal of door AND42
The first input end of the output terminal of the 5th phase inverter INV5 of end connection, two input of output terminal connection or door OR2；
Three or four input connect the output terminal of hex inverter INV6 with the 4th input terminal of door AND43, and output terminal connects
Meet the output terminal output third gating signal V of two inputs or the second input terminal of door OR2, two inputs or door OR2P3；
The first gating signal VP1, the second gating signal VP2With third gating signal VP3Described first is controlled to pass respectively
Defeated switch P1, the second transmitting switch P2 and third transmitting switch P3.
Beneficial effects of the present invention are：The circuit structure of the present invention is simple, and sampling precision is higher, and in the electric current progressive die
It can be worked normally under formula CCM and discontinuous conduct mode DCM.
Description of the drawings
Fig. 1 is primary side feedback formula flyback converter structure diagram.
Fig. 2 is single in sampling for a kind of voltage sampling circuit applied to primary side feedback formula flyback converter proposed by the present invention
Structure diagram when member is three.
Fig. 3 is the structure diagram of sampling control signal generation circuit in embodiment.
Fig. 4 is the structure diagram of sampled signal gating circuit in embodiment.
Specific embodiment
The present invention is further described with reference to the accompanying drawings and detailed description.
It is a kind of voltage sampling circuit applied to primary side feedback formula flyback converter proposed by the present invention as shown in Figure 2
Structure diagram includes the sampling unit of sampling control signal generation circuit, sampled signal gating circuit and at least two parallel connections,
Sampling unit includes sampling switch, sampling holding capacitor and transmitting switch, and sampling switch and transmitting switch series connection, series connection point lead to
It is grounded after over-sampling holding capacitor, the input terminal of the other end of sampling switch as sampling unit, the other end of transmitting switch is made
Output terminal for sampling unit；The input terminal of each sampling unit is connected and the input terminal of voltage sampling circuit is used as to connect primary side
Voltage signal V of the voltage after electric resistance partial pressure on auxiliary group of winding of reaction type flyback converter primary side power stageSENSE, output
End is connected and the output terminal as voltage sampling circuit exports sampled signal；Sampling control signal generation circuit controls for generating
Signal controls the sampling switch in sampling unit to sequentially turn on respectively so that the sampling holding capacitor storage in each sampling unit
Respective sampled voltage；Sampled signal gating circuit is used to generate the transmitting switch in the corresponding sampling unit of gating signal control
It is connected, the sampled voltage that holding capacitor storage is sampled in the sampling unit is exported, interior an of switch periods can there are one pass
Defeated switch is opened.
The present invention is described in detail by embodiment of three sampling units below.
As shown in Fig. 2, the first sampling unit includes the first sampling switch S1, the first sampling holding capacitor C1 and the first transmission
It is the first sampled signal V to switch the signal at the series connection point of P1, the first sampling switch S1 and the first transmitting switch P1SENSE1, pass through
First sampling holding capacitor C1 storages；Second sampling unit includes the second sampling switch S2, the second sampling holding capacitor C2 and the
Signal at the series connection point of two transmitting switch P2, the second sampling switch S2 and the second transmitting switch P2 is the second sampled signal
VSENSE2, pass through the second sampling holding capacitor C2 storages；Third sampling unit includes third sampling switch S3, third sampling is kept
Signal at capacitance C3 and the series connection point of third transmitting switch P3, third sampling switch S3 and third transmitting switch P3 is adopted for third
Sample signal VSENSE3, holding capacitor C3 storages are sampled by third.
The schematic diagram of sampling control signal generation circuit in the present embodiment is illustrated in figure 3, comparator adopts current period
Sample value and last periods samples subtract the offset voltage of comparator, and relatively to judge whether sampling terminates current with system
Operating mode, output first control signal VS1, second control signal VS2With third control signal VS3The first sampling of control respectively is opened
S1, the second sampling switch S2 and third sampling switch S3 are closed,
The operation principle of sampling control signal generation circuit is in the present embodiment：DRIVESignal is power tube drive signal,
Only work as DRIVEDuring for " 0 ", sampling just carries out.When sampling just starts, sampled voltage signal is not set up also, is controlled in order to prevent
Circuit false triggering turns over height and then by the first sampled signal in time delayed signal Delay (i.e. the drain terminal voltage signal of NMOS tube MN)
VSENSE1, the second sampled signal VSENSE2With third sampled signal VSENSE3It is compared.Three comparators are the comparison with imbalance
Device, offset voltage is about 100mV in the present embodiment, and each comparator adopted corresponding current period sampled value with the last period
Sample value subtracts 100mV and compares.
Under discontinuous conduct mode DCM, as the electric current I of diode D in primary side feedback formula flyback transformerSIt is zero, sampling electricity
The input voltage V of volt circuitSENSEVoltage when drastically declining, sampled value is abnormal low value, and the output of comparator at this time is turned over
Height terminates sampling；Under continuous current mode CCM, three comparators are always low level, when next switch periods start, are driven
Dynamic signal DRIVESampling is terminated when turning over high, the two integrates to obtain Sample signals (the i.e. the 1st input and the door of control sampling
The output end signal of AND41).Sampling frequency signal SH_clk is given by outside, and in general frequency is higher, is inverse-excitation converting
Tens hundreds of times of device switching frequency, sampling frequency signal SH_clk by after three frequency division with sampling control signal Sample phases
Three with being controlled three sampling switch respectively control signal VS1、VS2、VS3。
The structure diagram of sampled signal gating circuit in the present embodiment as shown in Figure 4, by continuous current mode CCM and
The sampled value transmission of two kinds of operating modes of discontinuous conduct mode DCM is uniformly processed, and exports the first gating signal VP1, second gating letter
Number VP2With third gating signal VP3The first gating switch P1, the second gating switch P2 and third gating switch P3 are controlled respectively.
The operation principle of sampled signal gating circuit is in the present embodiment：Four d flip-flop D4 and the 5th d type flip flop D5 structures
Into state machine, the first control signal V of sampling control signal generation circuit outputS1, second control signal VS2It controls and believes with third
Number VS3As the input of state machine, the first sampling unit at this time is represented when exports coding is 11 and is being sampled, is represented when being 10
The second sampling unit is sampling at this time, and third sampling unit at this time is represented when being 01 and is being sampled.By exports coding and control
The signal nSample phases of the inverted of the Sample signals of sampling are with being finally which is being adopted at the end of obtaining characterization sampling
The encoded signal a (the i.e. the 7th 2 input and the output signal of door AND27) and encoded signal b (the i.e. the 8th 2 input and door of sample
The output signal of AND28).Signal c (i.e. the output signal of third phase inverter INV3) is touched for the first trigger D1, second in Fig. 3
The signal that the signal exclusive or of the Q output output of hair device D2 and third trigger D3 obtains, signal c represent to be currently operating in for 0
Discontinuous conduct mode DCM, signal c represent to be currently operating in continuous current mode CCM for 1.Under DCM patterns, when sampling is terminated
The signal that the third last sampling period samples is sent out；Under CCM patterns, the signal sampled when sampling and terminating is sent
Go out.
Therefore it can obtain opening the sampling that switch P1 sends out the first via when tri- Signal codings of a, b, c are 111 and 010
Value；The sampled value that switch P2 sends out the second tunnel is opened when tri- Signal codings of a, b, c are 101 and 110；When tri- letters of a, b, c
The sampled value that switch P3 sends out third road is opened when number being encoded to 011 and 100.111 and 010 can by a, c with or rear and b phases with
It arrives；101 and 110 can be by after b, c exclusive or and a phases are with obtaining；011 and 100 can only be negated by a with b, c phase with, b, c are negated and a phases
With the two is gone or is obtained again.In order to which suitable sampled value is passed under unified continuous current mode CCM and discontinuous conduct mode DCM
The time of subsequent module is delivered to, by the Clk clock signals phase that above-mentioned signal starts with the period with being unified in next switch periods and opening
Suitable sampled value is transmitted to subsequent module during the beginning.
Pass through foregoing description, it can be seen that the present embodiment can meet continuous current mode CCM and discontinuous conduct mode DCM
All workable demand under both of which, while higher sampling precision is provided with relatively simple structure.
Those of ordinary skill in the art can make various do not depart from originally according to these technical inspirations disclosed by the invention
The other various specific deformations and combination of essence are invented, these deformations and combination are still within the scope of the present invention.
Claims (4)
1. a kind of voltage sampling circuit applied to primary side feedback formula flyback converter, which is characterized in that believe including controlling of sampling
The sampling units in parallel of number generation circuit, sampled signal gating circuit and at least two,
The sampling unit includes sampling switch, sampling holding capacitor and transmitting switch, the sampling switch and transmitting switch string
Connection, series connection point after the sampling holding capacitor by being grounded, and the other end of the sampling switch is as the sampling unit
Input terminal, the output terminal of the other end of the transmitting switch as the sampling unit；
The input terminal of each sampling unit is connected and is used as the input terminal of the voltage sampling circuit, and output terminal is connected simultaneously
Output terminal as the voltage sampling circuit；
The sampling control signal generation circuit controls signal to control the sampling switch in each sampling unit respectively for generating,
Sequentially turn on the sampling switch；
The sampled signal gating circuit is used to generating gating signal controls transmitting switch in each sampling unit respectively so that
Only there are one corresponding transmitting switches in one sampling period to be connected.
2. the voltage sampling circuit according to claim 1 applied to primary side feedback formula flyback converter, which is characterized in that
There are three the sampling units, and the first sampling unit includes the first sampling switch (S1), the first sampling holding capacitor (C1) and the
Signal at the series connection point of one transmitting switch (P1), the first sampling switch (S1) and the first transmitting switch (P1) is believed for the first sampling
Number (VSENSE1)；Second sampling unit includes the second sampling switch (S2), the second sampling holding capacitor (C2) and the second transmitting switch
(P2), the signal at the series connection point of the second sampling switch (S2) and the second transmitting switch (P2) is the second sampled signal (VSENSE2)；
Third sampling unit includes third sampling switch (S3), third sampling holding capacitor (C3) and third transmitting switch (P3), third
Signal at the series connection point of sampling switch (S3) and third transmitting switch (P3) is third sampled signal (VSENSE3)。
3. the voltage sampling circuit according to claim 2 applied to primary side feedback formula flyback converter, which is characterized in that
The sampling control signal generation circuit includes three frequency division module, first comparator (COMP1), the second comparator (COMP2), the
Three comparators (COMP3), the one or two input and door (AND21), the two or two input and door (AND22), the three or two input and door
(AND23), the four or two input and door (AND24), the five or two input and door (AND25), the six or two input and door (AND26), the
One or four inputs and door (AND41), the first d type flip flop (D1), the second d type flip flop (D2), third d type flip flop (D3), NMOS tube
(MN), capacitance (C4), current source (I) and the first phase inverter (INV1),
Three frequency division module includes an input terminal and three output terminals, and input terminal connects sampling frequency signal (SH_clk),
Three output terminals connect the four or two input and door (AND24), the five or two input and door (AND25) and the six or two input and door respectively
(AND26) first input end；
The grid of NMOS tube (MN) connects the input terminal of the first phase inverter (INV1) and connects the primary side feedback formula inverse-excitation converting
Grid drive signal (the D of primary side power tube in deviceRIVE), drain electrode by current source (I) is connected power supply potential and passed through afterwards respectively
Capacitance (C4) is grounded afterwards, source electrode ground connection；
First sampled signal (VSENSE1) negative input of connection first comparator (COMP1) and third comparator (COMP3)
Positive input, the second sampled signal (VSENSE2) connection first comparator (COMP1) positive input and the second comparator
(COMP2) negative input, third sampled signal (VSENSE3) the second comparator of connection (COMP2) positive input and the
The negative input of three comparators (COMP3), first comparator (COMP1), the second comparator (COMP2) and third comparator
(COMP3) output terminal connects the one or two input respectively and door (AND21), the two or two input are defeated with door (AND22) and the three or two
Enter and the first input end of door (AND23), the one or two input and door (AND21), the two or two input and door (AND22) and the three or two
Input connect the drain electrode of NMOS tube (MN) with the second input terminal of door (AND23)；
The D input terminals of first d type flip flop (D1), the second d type flip flop (D2) and third d type flip flop (D3) are all connected with power supply potential,
Its input end of clock connect respectively the one or two input with door (AND21), the two or two input with door (AND22) and the three or two input and
The output terminal of door (AND23),Output terminal connects the first input end of the one or four input and door (AND41), the second input respectively
End and third input terminal；
One or four input connect the output terminal of the first phase inverter (INV1) with the 4th input terminal of door (AND41), and output terminal connects
Connect the four or two input and door (AND24), the five or two input and door (AND25) and the six or two input with it is the second of door (AND26) defeated
Enter end；
Four or two input and door (AND24), the five or two input and door (AND25) and the six or two input and the output of door (AND26)
End exports first control signal (V respectivelyS1), second control signal (VS2) and third control signal (VS3) described is controlled respectively
One sampling switch (S1), the second sampling switch (S2) and third sampling switch (S3).
4. the voltage sampling circuit according to claim 3 applied to primary side feedback formula flyback converter, which is characterized in that
The sampled signal gating circuit includes four d flip-flop (D4), the 5th d type flip flop (D5), the second phase inverter (INV2), third
Phase inverter (INV3), the 4th phase inverter (INV4), the 5th phase inverter (INV5), hex inverter (INV6), the seven or two input with
Door (AND27), the eight or two input with door (AND28), the one or three input with door (AND31), the two or three input with door (AND32),
Two or four input and door (AND42), the three or four input and door (AND43), two inputs or door (OR2), three inputs or door (OR3),
XOR gate (XOR) and same or door (XNOR),
The D input terminals connection power supply potential of four d flip-flop (D4), input end of clock connection first control signal (VS1), Q
The seven or two input of output terminal connection and the first input end of door (AND27)；
The D input terminals connection ground potential of 5th d type flip flop (D5), input end of clock connection second control signal (VS2), Q is defeated
The eight or two input of outlet connection and the first input end of door (AND28)；
The input terminal connection third control signal (V of second phase inverter (INV2)S3), output terminal connection four d flip-flop (D4)
With the set end of the 5th d type flip flop (D5)；
Three input terminals of three inputs or door (OR3) connect the first d type flip flop in the sampling control signal generation circuit respectively
(D1), the Q output of the second d type flip flop (D2) and third d type flip flop (D3), output terminal connection third phase inverter (INV3)
Input terminal；
The output end signal of the one or four input and door (AND41) connects the 7th after negating in the sampling control signal generation circuit
Two inputs and door (AND27) and the eight or two input and the second input terminal of door (AND28)；
Seven or two input connect same or door (XNOR) first input end, hex inverter with the output terminal of door (AND27)
(INV6) input terminal, the two or three input input the first input end with door (AND42) with door (AND32) and the two or four；
Eight or two input connect the first input end of XOR gate (XOR), the 4th phase inverter (INV4) with the output terminal of door (AND28)
Input terminal, the one or three input with door (AND31) and the three or four input and door (AND43) first input end；
Second input terminal of the output terminal connection XOR gate (XOR) of third phase inverter (INV3), with or door (XNOR) it is second defeated
Enter end, the input terminal of the 5th phase inverter (INV5) and the three or four input and the second input terminal of door (AND43)；
The one or three input of clock signal (Clk) connection and door (AND31), the two or three input and door (AND32) and the two or four input
With the second input terminal of door (AND42) and the three or four input and the third input terminal of door (AND43), the clock signal
(Clk) it is consistent with the primary side feedback formula flyback converter switching frequency；
One or three input connect with the third input terminal of door (AND31) together or the output terminal of door (XNOR), output terminal export the
One gating signal (VP1)；
Two or three input connect the output terminal of XOR gate (XOR), output terminal output second with the third input terminal of door (AND32)
Gating signal (VP2)；
Two or four input connect the output terminal of the 4th phase inverter (INV4), the 4th input with the third input terminal of door (AND42)
The first input end of the output terminal of the 5th phase inverter (INV5) of end connection, two input of output terminal connection or door (OR2)；
Three or four input connect the output terminal of hex inverter (INV6) with the 4th input terminal of door (AND43), and output terminal connects
Meet the output terminal output third gating signal (V of the second input terminal of two inputs or door (OR2), two inputs or door (OR2)P3)；
First gating signal (the VP1), the second gating signal (VP2) and third gating signal (VP3) described first is controlled respectively
Transmitting switch (P1), the second transmitting switch (P2) and third transmitting switch (P3).
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| CN201810061866.1A CN108183615B (en) | 2018-01-23 | 2018-01-23 | Voltage sampling circuit applied to primary side feedback type flyback converter |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201810061866.1A CN108183615B (en) | 2018-01-23 | 2018-01-23 | Voltage sampling circuit applied to primary side feedback type flyback converter |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109980920A (en) * | 2019-05-06 | 2019-07-05 | 电子科技大学 | The logic control circuit of slope compensation signal in a kind of Peak Current Mode DC-DC converter |
| CN113625034A (en) * | 2021-07-19 | 2021-11-09 | 北京知存科技有限公司 | Sampling circuit, sampling array, integrated storage and calculation chip and electronic equipment |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105763039A (en) * | 2016-03-03 | 2016-07-13 | 复旦大学 | Charge transfer structure and method for capacitive-type charge pump |
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2018
- 2018-01-23 CN CN201810061866.1A patent/CN108183615B/en not_active Expired - Fee Related
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105763039A (en) * | 2016-03-03 | 2016-07-13 | 复旦大学 | Charge transfer structure and method for capacitive-type charge pump |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109980920A (en) * | 2019-05-06 | 2019-07-05 | 电子科技大学 | The logic control circuit of slope compensation signal in a kind of Peak Current Mode DC-DC converter |
| CN109980920B (en) * | 2019-05-06 | 2020-07-31 | 电子科技大学 | Logic control circuit of slope compensation signal in peak current mode DC-DC converter |
| CN113625034A (en) * | 2021-07-19 | 2021-11-09 | 北京知存科技有限公司 | Sampling circuit, sampling array, integrated storage and calculation chip and electronic equipment |
| CN113625034B (en) * | 2021-07-19 | 2024-05-24 | 杭州知存算力科技有限公司 | Sampling circuit, sampling array, integrated memory chip and electronic equipment |
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| CN108183615B (en) | 2020-01-03 |
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