CN108122964A - A kind of igbt - Google Patents
A kind of igbt Download PDFInfo
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- CN108122964A CN108122964A CN201711415532.1A CN201711415532A CN108122964A CN 108122964 A CN108122964 A CN 108122964A CN 201711415532 A CN201711415532 A CN 201711415532A CN 108122964 A CN108122964 A CN 108122964A
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- 238000009825 accumulation Methods 0.000 claims abstract description 35
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- 230000008859 change Effects 0.000 claims description 5
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 3
- 229910052760 oxygen Inorganic materials 0.000 claims description 3
- 239000001301 oxygen Substances 0.000 claims description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims 1
- 239000010931 gold Substances 0.000 claims 1
- 229910052737 gold Inorganic materials 0.000 claims 1
- 230000000694 effects Effects 0.000 abstract description 16
- 238000000034 method Methods 0.000 abstract description 12
- 238000005516 engineering process Methods 0.000 abstract description 11
- 239000004065 semiconductor Substances 0.000 abstract description 8
- 230000009467 reduction Effects 0.000 abstract description 6
- 239000000243 solution Substances 0.000 description 9
- 230000004048 modification Effects 0.000 description 5
- 238000012986 modification Methods 0.000 description 5
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- 238000002347 injection Methods 0.000 description 4
- 239000007924 injection Substances 0.000 description 4
- 230000009471 action Effects 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- 230000005611 electricity Effects 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
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- 230000007850 degeneration Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7398—Vertical transistors, e.g. vertical IGBT with both emitter and collector contacts in the same substrate side
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
- H01L29/0623—Buried supplementary region, e.g. buried guard ring
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
Abstract
A kind of igbt that the application provides, is related to field of semiconductor devices, including：N+ emitters, Pwell regions, wherein being provided with the first slot grid and the second slot grid in the Pwell regions；N drift regions；Carrier accumulation layer；P implanted layers；Without circle born of the same parents region, local grid is provided in the region without circle born of the same parents and is narrowed bias structure, wherein, the local grid bias structure that narrows includes：First grid, the first grid form laterally broadening structure in bottom, and broadening direction is towards second grid；Second grid, the second grid form laterally broadening structure in bottom, and the broadening direction is towards the first grid.After solving igbt carrier accumulation layer technology concentration raising of the prior art, the technical issues of causing igbt pressure-resistant reduction, reach and conduction voltage drop is being greatly lowered simultaneously, original voltage endurance capability is able to maintain that, so as to the technique effect of the parameters ability of General Promotion device.
Description
Technical field
The present invention relates to field of semiconductor devices, more particularly to a kind of igbt.
Background technology
Igbt is one of current high pressure, high current field core power semiconductor devices.In order to continuous
Improve device property, realize the optimal parameter performance of device, it is most important optimization effort to reduce break-over of device state saturation voltage drop
One of direction.
But present inventor during inventive technique scheme, has found above-mentioned technology extremely in the embodiment of the present application is realized
It has the following technical problems less：
After igbt carrier accumulation layer technology concentration of the prior art improves, cause insulated gate bipolar
Reduction that transistor is pressure-resistant.
The content of the invention
The embodiment of the present application solves insulated gate bipolar of the prior art by providing a kind of igbt
After transistor carrier accumulation layer technology concentration improves, the technical issues of causing igbt pressure-resistant reduction, reach
Conduction voltage drop is being greatly lowered meanwhile, it is capable to maintain original voltage endurance capability, so as to the parameters of General Promotion device
The technique effect of ability.
In view of the above problems, it is proposed that the embodiment of the present application is double in order to provide a kind of a kind of insulated gate for overcoming the above problem
Gated transistors, including：N+ emitters, Pwell regions, the Pwell regions are located at the lower section of the N+ emitters, wherein institute
It states and the first slot grid and the second slot grid is provided in Pwell regions；N drift regions, the N drift regions are located at the Pwell regions
Lower section；Carrier accumulation layer, the carrier accumulation layer are located at the lower section in the Pwell regions, and, the carrier accumulation layer
It is arranged between the first slot grid and the second slot grid；P implanted layers, the P implanted layers are located at the first slot grid and institute
State the lower sections of the second slot grid wherein, the transistor further includes：Without circle born of the same parents region, local grid are provided in the region without circle born of the same parents
Pole narrows bias structure, wherein, the local grid bias structure that narrows includes：First grid, the first grid are formed in bottom
Laterally broadening structure, and broadening direction is towards second grid；Second grid, the second grid form laterally broadening in bottom
Structure, and the broadening direction is towards the first grid.
Preferably, the transistor further includes：The N+ emitters include the first metal layer and the first oxide layer, wherein,
The top of the first grid is located at the engaging portion of the metal layer and oxide layer.
Preferably, the transistor further includes：The top of the second grid is located at the first metal layer and the second oxygen
Change the engaging portion of layer, wherein, first oxide layer and second oxide layer are respectively positioned at the both sides of the first metal layer.
Preferably, the transistor further includes：The first grid and second grid are in the broadening shape of transverse direction that bottom is formed
Into the spacing dimension of below 30nm.
The one or more technical solutions provided in the embodiment of the present application, have at least the following technical effects or advantages：
A kind of igbt provided by the embodiments of the present application, by N+ emitters, Pwell regions are described
Pwell regions are located at the lower section of the N+ emitters, wherein being provided with the first slot grid and the second slot grid in the Pwell regions；N
Drift region, the N drift regions are located at the lower section in the Pwell regions；Carrier accumulation layer, the carrier accumulation layer are located at institute
The lower section in Pwell regions is stated, and, the carrier accumulation layer is arranged between the first slot grid and the second slot grid；P is noted
Enter layer, the P implanted layers are located at the lower section of the first slot grid and the second slot grid wherein, and the transistor further includes：Nothing
Circle born of the same parents region is provided with local grid in the region without circle born of the same parents and narrows bias structure, wherein, local grid narrows bias structure
Including：First grid, the first grid form laterally broadening structure in bottom, and broadening direction is towards second grid；The
Two grids, the second grid form laterally broadening structure in bottom, and the broadening direction is towards the first grid.Solution
After igbt carrier accumulation layer technology concentration of the prior art of having determined improves, cause insulated gate bipolar transistor
The technical issues of managing pressure-resistant reduction has reached and conduction voltage drop is being greatly lowered meanwhile, it is capable to maintain original voltage endurance capability, from
And the technique effect of the parameters ability of General Promotion device.
Above description is only the general introduction of technical solution of the present invention, in order to better understand the technological means of the present invention,
And can be practiced according to the content of specification, and in order to allow above and other objects of the present invention, feature and advantage can
It is clearer and more comprehensible, below the special specific embodiment for lifting the present invention.
Description of the drawings
It in order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
There is attached drawing needed in technology description to be briefly described, it should be apparent that, the accompanying drawings in the following description is this hair
Some bright embodiments, for those of ordinary skill in the art, without creative efforts, can be with root
Other attached drawings are obtained according to these attached drawings.
Fig. 1 is a kind of structure diagram of igbt provided by the embodiments of the present application.
Drawing reference numeral explanation：N+ emitters 1, the first oxide layer 11, the second oxide layer 12, Pwell regions 2, N drift regions 3,
Carrier accumulation layer 4, P implanted layers 5, no circle born of the same parents region 6, local grid narrow bias structure 7, first grid 71, second grid
72。
Specific embodiment
It is brilliant to solve insulated gate bipolar of the prior art for a kind of igbt provided by the embodiments of the present application
After body pipe carrier accumulation layer technology concentration improves, the technical issues of causing igbt pressure-resistant reduction.
Technical solution in the embodiment of the present application, group method are as follows：N+ emitters, Pwell regions, the Pwell areas
Domain is located at the lower section of the N+ emitters, wherein being provided with the first slot grid and the second slot grid in the Pwell regions；N drift regions,
The N drift regions are located at the lower section in the Pwell regions；Carrier accumulation layer, the carrier accumulation layer are located at the Pwell
The lower section in region, and, the carrier accumulation layer is arranged between the first slot grid and the second slot grid；P implanted layers, institute
It states P implanted layers and is located at the lower sections of the first slot grid and the second slot grid wherein, the transistor further includes：Without Yuan Bao areas
Domain is provided with local grid in the born of the same parents region without circle and narrows bias structure, wherein, the local grid bias structure that narrows includes：
First grid, the first grid form laterally broadening structure in bottom, and broadening direction is towards second grid；Second gate
Pole, the second grid form laterally broadening structure in bottom, and the broadening direction is towards the first grid.Reach
Conduction voltage drop is being greatly lowered meanwhile, it is capable to maintain original voltage endurance capability, so as to the parameters energy of General Promotion device
The technique effect of power.
The exemplary embodiment of the disclosure will be described in detail belows.Although this application discloses one or more of exemplary
Embodiment, it being understood, however, that may be realized in various forms the disclosure without should be limited by embodiments set forth here.Phase
Instead, these embodiments are provided to facilitate a more thoroughly understanding of the present invention, and can completely pass the scope of the present disclosure
Up to those skilled in the art.
Embodiment one
A kind of igbt provided by the embodiments of the present application, igbt (Insulate-Gate
Bipolar Transistor-IGBT) abbreviation IGBT, combine power transistor (Giant Transistor-GTR) and electricity
The advantages of field of force effect transistor (Power MOSFET), there is good characteristic, application field is very extensive；IGBT is also three ends
Device:Grid, collector and emitter.IGBT is MOS structure bipolar device, belongs to the high speed performance with power MOSFET
With the power device of bipolar low resistive energy.The application range of IGBT generally all pressure-resistant more than 600V, more than electric current 10A,
Frequency is the region of more than 1kHz.It uses in industrial motor, civilian small-capacity motor, converter (inverter), camera more
The fields such as stroboscope, sensing heating (InductionHeating) electric cooker.As shown in Figure 1, the transistor includes：
N+ emitters 1；
Specifically, N+ emitters 1, Pwell2, N drift region 3 form field-effect tube (Field Effect
Transistor abridges (FET).IGBT structure increases P+ structures in bottom, realizes hole injection, forms the current-carrying of two kinds of polarity
Son conducting, the i.e. minority carrier (hole) of majority carrier (electronics) and reversed polarity participate in conduction, because of referred to herein as ambipolar crystalline substance
Body pipe, and electronic conduction is controlled by grid, therefore referred to as igbt (Insulate-Gate Bipolar
Transistor-IGBT)。
Pwell regions 2, the Pwell regions 2 are located at the lower section of the N+ emitters 1, wherein the Pwell regions 2
In be provided with the first slot grid 21 and the second slot grid 22；
Specifically, the Pwell regions 2 are p-well region, and semiconductor generally can be divided into intrinsic semiconductor, N-type semiconductor
And P-type semiconductor represents free from admixture doping, doped N-type impurity (P, As) and doped p-type impurity (B, Ga) if is in N respectively
P type island region is spread on type substrate, is just called p-well region；If spreading N-type region in P type substrate, just it is called N well regions；The Pwell
Region 2 is located at the lower section of the N+ emitters 1, wherein, 21 He of the first slot grid is internally provided in the Pwell regions 2
Second slot grid 22, due to igbt provided by the embodiments of the present application be based on using carrier storage layer structure and
What the groove gate type igbt of P injecting structures was completed, so, the igbt that the application provides
The first slot grid 21 and the second slot grid 22 are provided in Pwell regions 2.
N drift regions 3, the N drift regions 3 are located at the lower section in the Pwell regions 2；
Specifically, since the carrier properties and concentration on p type island region and N-type region both sides differ, the hole of p type island region is dense
Degree is big, and the electron concentration of N-type region is big, and diffusion motion is then generated at interface.The hole of p type island region is expanded to N-type region
It dissipates, it is negatively charged when losing hole；And the electronics of N-type region is spread to p type island region, the positively charged when losing electronics, so in P areas and
The intersection in N areas forms an electric field (being known as internal electric field).Under the action of internal electric field, electronics will drift about from P areas to N areas
Movement, drift motion is then made in hole from N areas to P areas.The region that drift motion is carried out in electronics is referred to as drift region, the N drifts
Move the lower section that area 3 is located at the Pwell regions 2.Low-doped N drift regions are mainly used for supporting high voltage in IGBT structure,
Conductance modulation effect is formed since carrier largely injects during conducting, so as to reduce conduction voltage drop.
Carrier accumulation layer 4, the carrier accumulation layer 4 are located at the lower section in the Pwell regions 2, and, the carrier
Accumulation layer 4 is arranged between the first slot grid 21 and the second slot grid 22；
Specifically, electrical current carriers claim carrier.In physics, carrier refer to can move freely with charge
Corpuscle, such as electronics and ion.In semiconductor physics, electronics loss causes the room left on covalent bond to be considered as
Carrier.By injecting certain density N-type carrier accumulation layer below the Pwell regions 2, and, the carrier is deposited
Reservoir 4 is arranged between the first slot grid 21 and the second slot grid 22, stops hole flow during conducting state, this side
Method can realize preferable conductance modulation effect, reduce break-over of device state saturation voltage drop.
P implanted layers 5, the P implanted layers 5 are located at the lower section of the first slot grid 21 and the second slot grid 22, the P notes
Enter layer and form ground potential.
Specifically, P is injected separately into the lower section of the first slot grid 21 and the second slot grid 22, forms P implanted layers
5, high concentration N-type carrier accumulation layer is can compensate in the concentration of p-type structure, can reach selects N-type carrier accumulation layer
Concentration can improve that an order of magnitude is other, while will not bring the degenerate case of voltage endurance capability, while P injection zones are become by grid
Narrow bias structure forms ground potential, so as to improve the transistor characteristic.
Wherein, the transistor further includes：It is described to narrow without being provided with local grid in circle born of the same parents region 6 without circle born of the same parents region 6
Bias structure 7, wherein, the local grid bias structure 7 that narrows includes：First grid 71, the first grid 71 are formed in bottom
Laterally broadening structure, and broadening direction is towards second grid 72；Second grid 72, the second grid 72 form horizontal stroke in bottom
To broadening structure, and the broadening direction is towards the first grid 71；The first grid 71 and second grid 72 are the bottom of at
The broadening spacing dimension for forming below 30nm of transverse direction that portion is formed.
Further, the transistor further includes：Described without in N+ emitters 1 corresponding to circle born of the same parents region, the N+ is sent out
Emitter-base bandgap grading 1 includes the first oxide layer 11 and the second oxide layer 12, wherein, the top of the first grid is located at the metal layer and oxygen
Change the engaging portion of layer.
Specifically, on the basis of existing structure is using carrier accumulation layer technology and gate bottom P injection zones,
The not rounded born of the same parents region of device adds local grid and narrows design structure 7.The structure is connected in device surface with emitter metal,
Ground connection biasing is formed, gate bottom forms the local adjacent grid size of part for becoming narrow structure, realizing 30nm, and technique is complete
It is compatible with existing power device manufacturing processing technic.
Embodiment two
In order to more clearly illustrate a kind of igbt, the embodiment of the present application additionally provides a kind of insulated gate
The operation principle of bipolar transistor is below described in detail a kind of operation principle of igbt.
Igbt described herein is in conducting state, since the grid in not rounded born of the same parents area locally narrows design
1 metallic ground of structure connection N+ emitters, so P implanted layers 5 can be grounded biasing connection structure, at this time due to ground connection electricity
Gesture acts on, and two neighboring P implanted layers 5 can be realized easily under relatively low concentration in device circle born of the same parents' structure mutually exhausts,
Form shielding construction effect, so when the transistor design N-type carrier accumulation layer 4 of high concentration can be selected to set
Meter, selected concentration can be higher than the prior art and use the selected N-type accumulation layer concentration of no ground P injecting structures situation,
Because the structure of herein described transistor be by, the shielding action of P implanted layers 5 carrys out isolating n-type carrier accumulation layer 4, so
When designed also without using excessively high P implantation concentrations.Transistor arrangement described herein will not be carried due to the N-type of high concentration
Flowing sub- 4 region of accumulation layer can not exhaust and cause the pressure-resistant degeneration of the transistor.The carrier accumulation layer 4 of high concentration can simultaneously
To stop almost all of hole carried flow, conductivity modulation effect is greatly strengthened.In addition, not rounded born of the same parents region in the structure design
The grid of use locally becomes narrow structure although there are earth-continuity access, but in actual transistor conducting state, due to being formed
The gate structure of tens local nano-scale spacing, so region design can effectively block the flowing in hole,
It will not cause the outflow in hole due to ground connection biasing.On the whole, the part that this new structure device uses in not rounded born of the same parents area
Grid becomes narrow structure, realizes the ground potential of P injection zones, and the shielding action formed can select very high N-type hole to hinder
Barrier concentration realizes splendid conductivity modulation effect, while device hole flow in not rounded born of the same parents region in conducting state is also had
Effect stops, while so as to reach the transistor turns saturation voltage drop approximation theory limit, the voltage endurance capability of device will not be by
To the technique effect of influence.
The one or more technical solutions provided in the embodiment of the present application, have at least the following technical effects or advantages：
A kind of igbt provided by the embodiments of the present application, by N+ emitters, Pwell regions are described
Pwell regions are located at the lower section of the N+ emitters, wherein being provided with the first slot grid and the second slot grid in the Pwell regions；N
Drift region, the N drift regions are located at the lower section in the Pwell regions；Carrier accumulation layer, the carrier accumulation layer are located at institute
The lower section in Pwell regions is stated, and, the carrier accumulation layer is arranged between the first slot grid and the second slot grid；P is noted
Enter layer, the P implanted layers are located at the lower section of the first slot grid and the second slot grid wherein, and the transistor further includes：Nothing
Circle born of the same parents region is provided with local grid in the region without circle born of the same parents and narrows bias structure, wherein, local grid narrows bias structure
Including：First grid, the first grid form laterally broadening structure in bottom, and broadening direction is towards second grid；The
Two grids, the second grid form laterally broadening structure in bottom, and the broadening direction is towards the first grid.Solution
After igbt carrier accumulation layer technology concentration of the prior art of having determined improves, cause insulated gate bipolar transistor
The technical issues of managing pressure-resistant reduction has reached and conduction voltage drop is being greatly lowered meanwhile, it is capable to maintain original voltage endurance capability, from
And the technique effect of the parameters ability of General Promotion device.
Although preferred embodiments of the present invention have been described, but those skilled in the art once know basic creation
Property concept, then can make these embodiments other change and modification.So appended claims be intended to be construed to include it is excellent
It selects embodiment and falls into all change and modification of the scope of the invention.
Obviously, various changes and modifications can be made to the invention without departing from essence of the invention by those skilled in the art
God and scope.In this way, if these modifications and changes of the present invention belongs to the scope of the claims in the present invention and its equivalent technologies
Within, then the present invention is also intended to comprising including these modification and variations.
It should be noted last that more than specific embodiment is merely illustrative of the technical solution of the present invention and unrestricted,
Although the present invention is described in detail with reference to example, it will be understood by those of ordinary skill in the art that, it can be to the present invention
Technical solution be modified or replaced equivalently, without departing from the spirit and scope of technical solution of the present invention, should all cover
Among scope of the presently claimed invention.
A kind of area determination method and device provided by the embodiments of the present application are as a result of by obtaining the first area week
Side, each road closest with it, and the mutual limitation of the position relationship according to each road, it is described so as to obtain
The specific location of first area, solve in the prior art using the predeterminable area in database and the registration of target area and
The problem of caused position inaccurate, and then can precisely obtain the technique effect of target specific location.
Claims (4)
1. a kind of igbt, which is characterized in that the transistor includes：
N+ emitters,
Pwell regions, the Pwell regions are located at the lower section of the N+ emitters, wherein being provided in the Pwell regions
One slot grid and the second slot grid；
N drift regions, the N drift regions are located at the lower section in the Pwell regions；
Carrier accumulation layer, the carrier accumulation layer are located at the lower section in the Pwell regions, and, the carrier accumulation layer
It is arranged between the first slot grid and the second slot grid；
P implanted layers, the P implanted layers are located at the lower section of the first slot grid and the second slot grid,
Wherein, the transistor further includes：
Without circle born of the same parents region, local grid is provided in the region without circle born of the same parents and is narrowed bias structure, wherein, local grid narrows partially
Putting structure includes：
First grid, the first grid form laterally broadening structure in bottom, and broadening direction is towards second grid；
Second grid, the second grid form laterally broadening structure in bottom, and the broadening direction is towards described first
Grid.
2. transistor as described in claim 1, which is characterized in that the transistor further includes：
The N+ emitters include the first metal layer and the first oxide layer, wherein, the top of the first grid is located at the gold
Belong to the engaging portion of layer and oxide layer.
3. transistor as claimed in claim 2, which is characterized in that the transistor further includes：
The top of the second grid is located at the engaging portion of the first metal layer and the second oxide layer, wherein, first oxygen
Change the both sides that layer and second oxide layer are located at the first metal layer respectively.
4. transistor as described in claim 1, which is characterized in that the transistor further includes：
The first grid and second grid are in the broadening spacing dimension for forming below 30nm of the transverse direction that bottom is formed.
Priority Applications (1)
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| CN113764511A (en) * | 2021-07-30 | 2021-12-07 | 西安电子科技大学 | Low-loss super-junction IGBT device with dynamic carrier channel and manufacturing method thereof |
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| EP2398058A2 (en) * | 2001-01-19 | 2011-12-21 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device |
| CN102386099A (en) * | 2010-08-30 | 2012-03-21 | 英飞凌科技奥地利有限公司 | Method for forming a semiconductor device, and a semiconductor with an integrated poly-diode |
| CN102683403A (en) * | 2012-04-24 | 2012-09-19 | 电子科技大学 | Trench gate charge storage type insulated gate bipolar transistor (IGBT) |
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| CN101694850A (en) * | 2009-10-16 | 2010-04-14 | 电子科技大学 | Carrier-storing grooved gate IGBT with P-type floating layer |
| CN102386099A (en) * | 2010-08-30 | 2012-03-21 | 英飞凌科技奥地利有限公司 | Method for forming a semiconductor device, and a semiconductor with an integrated poly-diode |
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| CN113764511A (en) * | 2021-07-30 | 2021-12-07 | 西安电子科技大学 | Low-loss super-junction IGBT device with dynamic carrier channel and manufacturing method thereof |
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