CN108122964B - Insulated gate bipolar transistor - Google Patents
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- CN108122964B CN108122964B CN201711415532.1A CN201711415532A CN108122964B CN 108122964 B CN108122964 B CN 108122964B CN 201711415532 A CN201711415532 A CN 201711415532A CN 108122964 B CN108122964 B CN 108122964B
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7398—Vertical transistors, e.g. vertical IGBT with both emitter and collector contacts in the same substrate side
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
- H01L29/0623—Buried supplementary region, e.g. buried guard ring
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
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Abstract
The application provides an insulated gate bipolar transistor, relates to the semiconductor device field, includes: the device comprises an N + emitter and a Pwell area, wherein a first grooved gate and a second grooved gate are arranged in the Pwell area; an N drift region; a carrier storage layer; a P injection layer; a non-round cell region having a local gate narrowing bias structure disposed therein, wherein the local gate narrowing bias structure comprises: the first grid electrode forms a transverse widening structure at the bottom, and the widening direction faces to the second grid electrode; and the second grid electrode forms a transversely widened structure at the bottom, and the widening direction faces to the first grid electrode. The technical problem that after the technical concentration of a current carrier storage layer of the insulated gate bipolar transistor in the prior art is improved, the withstand voltage of the insulated gate bipolar transistor is reduced is solved, the original withstand voltage capability can be maintained while the conduction voltage drop is greatly reduced, and therefore the technical effect of comprehensively improving various parameter capabilities of the device is achieved.
Description
Technical Field
The invention relates to the field of semiconductor devices, in particular to an insulated gate bipolar transistor.
Background
An insulated gate bipolar transistor is one of the core power semiconductor devices in the high-voltage and large-current fields at present. In order to improve the device characteristics continuously and achieve the best parametric performance of the device, reducing the on-state saturation voltage drop of the device is one of the most important optimization efforts.
However, in the process of implementing the technical solution of the invention in the embodiments of the present application, the inventors of the present application find that the above-mentioned technology has at least the following technical problems:
after the technical concentration of a current carrier storage layer of the insulated gate bipolar transistor in the prior art is improved, the withstand voltage of the insulated gate bipolar transistor is reduced.
Disclosure of Invention
The embodiment of the application provides an insulated gate bipolar transistor, and solves the technical problem that after the technical concentration of a current carrier storage layer of the insulated gate bipolar transistor in the prior art is improved, the withstand voltage of the insulated gate bipolar transistor is reduced, so that the original withstand voltage capability can be maintained while the conduction voltage drop is greatly reduced, and the technical effect of comprehensively improving various parameter capabilities of devices is achieved.
In view of the above problem, embodiments of the present application are proposed to provide an insulated gate bipolar transistor that overcomes the above problem, including: the device comprises an N + emitter and a Pwell region, wherein the Pwell region is positioned below the N + emitter, and a first grooved gate and a second grooved gate are arranged in the Pwell region; an N drift region located below the Pwell region; a carrier storage layer located below the Pwell region, the carrier storage layer being disposed between the first and second trenched gates; a P-implant layer located below the first and second trenched gates, wherein the transistor further comprises: a non-round cell region having a local gate narrowing bias structure disposed therein, wherein the local gate narrowing bias structure comprises: the first grid electrode forms a transverse widening structure at the bottom, and the widening direction faces to the second grid electrode; and the second grid electrode forms a transversely widened structure at the bottom, and the widening direction faces to the first grid electrode.
Preferably, the transistor further includes: the N + emitter comprises a first metal layer and a first oxidation layer, wherein the top end of the first grid electrode is located at the joint of the metal layer and the oxidation layer.
Preferably, the transistor further includes: the top end of the second gate is located at the joint of the first metal layer and the second oxide layer, wherein the first oxide layer and the second oxide layer are respectively located on two sides of the first metal layer.
Preferably, the transistor further includes: the lateral widening of the first gate and the second gate formed at the bottom results in a pitch dimension of 30nm or less.
One or more technical solutions provided in the embodiments of the present application have at least the following technical effects or advantages:
according to the insulated gate bipolar transistor provided by the embodiment of the application, an N + emitter and a Pwell region are arranged, the Pwell region is positioned below the N + emitter, and a first grooved gate and a second grooved gate are arranged in the Pwell region; an N drift region located below the Pwell region; a carrier storage layer located below the Pwell region, the carrier storage layer being disposed between the first and second trenched gates; a P-implant layer located below the first and second trenched gates, wherein the transistor further comprises: a non-round cell region having a local gate narrowing bias structure disposed therein, wherein the local gate narrowing bias structure comprises: the first grid electrode forms a transverse widening structure at the bottom, and the widening direction faces to the second grid electrode; and the second grid electrode forms a transversely widened structure at the bottom, and the widening direction faces to the first grid electrode. The technical problem that after the technical concentration of a current carrier storage layer of the insulated gate bipolar transistor in the prior art is improved, the withstand voltage of the insulated gate bipolar transistor is reduced is solved, the original withstand voltage capability can be maintained while the conduction voltage drop is greatly reduced, and therefore the technical effect of comprehensively improving various parameter capabilities of the device is achieved.
The foregoing description is only an overview of the technical solutions of the present invention, and the embodiments of the present invention are described below in order to make the technical means of the present invention more clearly understood and to make the above and other objects, features, and advantages of the present invention more clearly understandable.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and those skilled in the art can also obtain other drawings according to the drawings without creative efforts.
Fig. 1 is a schematic structural diagram of an insulated gate bipolar transistor according to an embodiment of the present disclosure.
The reference numbers illustrate: the semiconductor device comprises an N + emitter 1, a first oxidation layer 11, a second oxidation layer 12, a Pwell region 2, an N drift region 3, a carrier storage layer 4, a P injection layer 5, a round cell-free region 6, a local gate narrowing bias structure 7, a first gate 71 and a second gate 72.
Detailed Description
The insulated gate bipolar transistor provided by the embodiment of the application solves the technical problem that after the technical concentration of a carrier storage layer of the insulated gate bipolar transistor in the prior art is improved, the withstand voltage of the insulated gate bipolar transistor is reduced.
The technical scheme in the embodiment of the application has the following overall method: the device comprises an N + emitter and a Pwell region, wherein the Pwell region is positioned below the N + emitter, and a first grooved gate and a second grooved gate are arranged in the Pwell region; an N drift region located below the Pwell region; a carrier storage layer located below the Pwell region, the carrier storage layer being disposed between the first and second trenched gates; a P-implant layer located below the first and second trenched gates, wherein the transistor further comprises: a non-round cell region having a local gate narrowing bias structure disposed therein, wherein the local gate narrowing bias structure comprises: the first grid electrode forms a transverse widening structure at the bottom, and the widening direction faces to the second grid electrode; and the second grid electrode forms a transversely widened structure at the bottom, and the widening direction faces to the first grid electrode. The technical effects of greatly reducing the conduction voltage drop, maintaining the original voltage resistance and comprehensively improving the parameter capability of the device are achieved.
Exemplary embodiments of the present disclosure will be described in detail below. While the present application discloses one or more exemplary embodiments, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
Example one
According to the insulated gate bipolar Transistor, an insulated gate bipolar Transistor (insulated-gate bipolar Transistor-IGBT) is called as an IGBT for short, the advantages of a Power Transistor (Giant Transistor-GTR) and a Power field effect Transistor (Power MOSFET) are integrated, the insulated gate bipolar Transistor has good characteristics, and the application field is wide; an IGBT is also a three-terminal device, the gate, collector and emitter. The IGBT is a bipolar device with a MOS structure, and belongs to a power device with high-speed performance of a power MOSFET and bipolar low-resistance performance. The application range of the IGBT is generally in the region of a withstand voltage of 600V or more, a current of 10A or more, and a frequency of 1kHz or more. The present invention is widely used in the fields of industrial motors, small-capacity commercial motors, inverters, stroboscopes for cameras, induction heating (electric) cookers, and the like. As shown in fig. 1, the transistor includes:
an N + emitter 1;
specifically, the N + emitter 1, the Pwell2, and the N drift region 3 form a Field Effect Transistor (FET); IGBT structure adds a P + structure at the bottom to realize hole injection, and two polarities of carrier conduction are formed, i.e., a majority carrier (electron) and a minority carrier (hole) of opposite polarity participate in conduction, and thus the IGBT is called a bipolar transistor, and electron conduction is controlled by a Gate, and thus the IGBT is called an insulated-Gate bipolar transistor (IGBT).
A Pwell region 2, wherein the Pwell region 2 is located below the N + emitter 1, and a first trench gate 21 and a second trench gate 22 are disposed in the Pwell region 2;
specifically, the Pwell region 2 is a P-well region, and the semiconductor can be generally classified As an intrinsic semiconductor, an N-type semiconductor and a P-type semiconductor, which respectively represent impurity-free doping, N-type impurity doping (P, As) and P-type impurity doping (B, Ga), if a P-type region is diffused on an N-type substrate, it is called a P-well region; if an N-type region is diffused on a P-type substrate, the N-type region is called an N-well region; the Pwell region 2 is located below the N + emitter 1, wherein the first and second trenched gates 21 and 22 are disposed in the Pwell region 2, and since the insulated gate bipolar transistor provided in the embodiment of the present invention is implemented by a trench gate type insulated gate bipolar transistor using a carrier storage layer structure and a P-injection structure, the first and second trenched gates 21 and 22 are disposed in the Pwell region 2 of the insulated gate bipolar transistor provided in the present invention.
An N drift region 3, wherein the N drift region 3 is positioned below the Pwell region 2;
specifically, since the carrier properties and concentrations are different at both sides of the P-type region and the N-type region, the hole concentration of the P-type region is large, and the electron concentration of the N-type region is large, so that diffusion movement is generated at the interface. Holes in the P-type region diffuse to the N-type region and are negatively charged due to the loss of holes; electrons in the N-type region diffuse into the P-type region and become positively charged as a result of losing electrons, thus creating an electric field (referred to as an internal electric field) at the interface between the P-region and the N-region. Under the action of the internal electric field, electrons drift from the P region to the N region, and holes drift from the N region to the P region. The region where electrons drift is called a drift region, and the N drift region 3 is located below the Pwell region 2. The low-doped N drift region in the IGBT structure is mainly used for supporting high withstand voltage, and a conductance modulation effect is formed due to the fact that a large number of carriers are injected when the IGBT structure is conducted, so that conducting voltage drop can be reduced.
A carrier storage layer 4, the carrier storage layer 4 being located below the Pwell region 2, and the carrier storage layer 4 being disposed between the first and second grooved gates 21 and 22;
specifically, the current carrier is called a carrier. In physics, carriers refer to particles of matter that are free to move and carry an electric charge, such as electrons and ions. In semiconductor physics, electron loss results in vacancies left on covalent bonds that are considered carriers. By injecting an N-type carrier storage layer with a certain concentration below the Pwell region 2, and arranging the carrier storage layer 4 between the first groove grid 21 and the second groove grid 22, the hole flow in the on state is blocked, and the method can realize a better conductivity modulation effect and reduce the saturated voltage drop of the on state of the device.
Specifically, P is injected below the first trench gate 21 and the second trench gate 22 to form a P injection layer 5, a high-concentration N-type carrier storage layer can be compensated for by the concentration of the P-type structure, the N-type carrier storage layer selection concentration can be increased by a certain amount without degradation of the withstand voltage capability, and the P injection region is grounded by a gate narrowing bias structure, thereby improving the transistor characteristics.
Wherein the transistor further comprises: a round cell free region 6, wherein a local gate narrowing bias structure 7 is disposed in the round cell free region 6, wherein the local gate narrowing bias structure 7 comprises: a first gate 71, wherein the first gate 71 has a laterally widened structure at the bottom, and the widening direction faces the second gate 72; a second gate 72, wherein the second gate 72 has a laterally widened structure at a bottom thereof, and the widening direction is toward the first gate 71; the lateral widening of the first gate 71 and the second gate 72 formed at the bottom results in a pitch dimension of 30nm or less.
Further, the transistor further includes: in the N + emitter 1 corresponding to the round cell-free region, the N + emitter 1 includes a first oxide layer 11 and a second oxide layer 12, wherein a top end of the first gate is located at a joint of the metal layer and the oxide layer.
Specifically, a local gate narrowing design structure 7 is added in a non-circular cell area of a device on the basis that the existing structure adopts a carrier storage layer technology and a gate bottom P injection area. The structure is connected with emitter metal on the surface of a device to form grounding bias, a local narrowing structure is formed at the bottom of a grid, the size of a local adjacent grid of 30nm is realized, and the process is completely compatible with the manufacturing and processing process of the existing power device.
Example two
In order to illustrate an insulated gate bipolar transistor more clearly, the embodiments of the present application further provide an operating principle of the insulated gate bipolar transistor, and the operating principle of the insulated gate bipolar transistor is described in detail below.
In the on state of the insulated gate bipolar transistor, the gate local narrowing design structure of the non-round cell region is connected with the N + emitter 1 metal grounding, so that the P injection layer 5 can realize a grounding bias connection structure, at the moment, due to the action of the grounding potential, two adjacent P injection layers 5 in the round cell structure of the device can be easily mutually exhausted under lower concentration, and a shielding structure effect is formed, so that the design of the transistor can select the design of an N-type carrier storage layer 4 with extremely high concentration, and the selected concentration can be higher than the concentration of the N-type storage layer selected under the condition that the ungrounded P injection structure is adopted in the prior art. The transistor structure does not cause voltage resistance degradation of the transistor due to the fact that the high-concentration N-type carrier storage layer 4 region cannot be exhausted. Meanwhile, the high-concentration carrier storage layer 4 can block almost all hole carrier flow, and the conductivity modulation effect is greatly enhanced. In addition, although the local gate narrowing structure adopted by the non-circular cell region in the structural design has a grounding conduction path, the local gate structure with the size of tens of nanometers is formed when the transistor is in an actual on state, so that the regional design can effectively block the flow of holes, and the holes cannot flow out due to grounding bias. In general, the novel structure device adopts a local grid narrowing structure in a non-circular cell area to realize the grounding potential of a P injection area, the formed shielding effect can select high N-type hole blocking layer concentration to realize excellent conductance modulation effect, and simultaneously, the hole flow of the non-circular cell area is effectively blocked when the device is in a conducting state, so that the technical effect that the voltage resistance of the device cannot be influenced when the conduction saturation voltage drop of the transistor approaches the theoretical limit is achieved.
One or more technical solutions provided in the embodiments of the present application have at least the following technical effects or advantages:
according to the insulated gate bipolar transistor provided by the embodiment of the application, an N + emitter and a Pwell region are arranged, the Pwell region is positioned below the N + emitter, and a first grooved gate and a second grooved gate are arranged in the Pwell region; an N drift region located below the Pwell region; a carrier storage layer located below the Pwell region, the carrier storage layer being disposed between the first and second trenched gates; a P-implant layer located below the first and second trenched gates, wherein the transistor further comprises: a non-round cell region having a local gate narrowing bias structure disposed therein, wherein the local gate narrowing bias structure comprises: the first grid electrode forms a transverse widening structure at the bottom, and the widening direction faces to the second grid electrode; and the second grid electrode forms a transversely widened structure at the bottom, and the widening direction faces to the first grid electrode. The technical problem that after the technical concentration of a current carrier storage layer of the insulated gate bipolar transistor in the prior art is improved, the withstand voltage of the insulated gate bipolar transistor is reduced is solved, the original withstand voltage capability can be maintained while the conduction voltage drop is greatly reduced, and therefore the technical effect of comprehensively improving various parameter capabilities of the device is achieved.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the invention.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Finally, it should be noted that the above embodiments are only for illustrating the technical solutions of the present invention and not for limiting, and although the present invention has been described in detail with reference to examples, it should be understood by those skilled in the art that modifications or equivalent substitutions may be made on the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, which should be covered by the claims of the present invention.
According to the area determining method and device, the specific position of the first area is obtained by obtaining the roads which are peripheral to the first area and have the closest distance to the first area and limiting the position relation of the roads, the problem of inaccurate positioning caused by the contact ratio of the preset area and the target area in the database in the prior art is solved, and the technical effect of accurately obtaining the specific position of the target is achieved.
Claims (3)
1. An insulated gate bipolar transistor, the transistor comprising:
an emitter of N + is arranged on the substrate,
a Pwell region located below the N + emitter, wherein a first grooved gate and a second grooved gate are arranged in the Pwell region;
an N drift region located below the Pwell region;
a carrier storage layer located below the Pwell region, the carrier storage layer being disposed between the first and second trenched gates;
a P injection layer located below the first and second trenched gates;
a non-round cell region having a local gate narrowing bias structure disposed therein, wherein the local gate narrowing bias structure comprises:
the first grid electrode forms a transverse widening structure at the bottom, and the widening direction faces to the second grid electrode;
the second grid electrode forms a transverse widening structure at the bottom, and the widening direction faces to the first grid electrode;
wherein the P-implant region is formed at ground potential by the local gate narrowing bias structure;
the lateral widening of the first gate and the second gate formed at the bottom results in a pitch dimension of 30nm or less.
2. The transistor of claim 1, further comprising:
the N + emitter comprises a first metal layer and a first oxidation layer, wherein the top end of the first grid electrode is located at the joint of the metal layer and the oxidation layer.
3. The transistor of claim 2, further comprising:
the top end of the second gate is located at the joint of the first metal layer and the second oxide layer, wherein the first oxide layer and the second oxide layer are respectively located on two sides of the first metal layer.
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| CN201711415532.1A CN108122964B (en) | 2017-12-22 | 2017-12-22 | Insulated gate bipolar transistor |
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| CN201711415532.1A CN108122964B (en) | 2017-12-22 | 2017-12-22 | Insulated gate bipolar transistor |
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| CN101694850B (en) * | 2009-10-16 | 2011-09-14 | 电子科技大学 | Carrier-storing grooved gate IGBT with P-type floating layer |
| US8435853B2 (en) * | 2010-08-30 | 2013-05-07 | Infineon Technologies Ag | Method for forming a semiconductor device, and a semiconductor with an integrated poly-diode |
| CN102683403B (en) * | 2012-04-24 | 2015-05-27 | 电子科技大学 | Trench gate charge storage type insulated gate bipolar transistor (IGBT) |
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2017
- 2017-12-22 CN CN201711415532.1A patent/CN108122964B/en active Active
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