CN108121430A - A kind of soft boot-strap circuit in the charged pool path for applying to data collecting system - Google Patents
A kind of soft boot-strap circuit in the charged pool path for applying to data collecting system Download PDFInfo
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- CN108121430A CN108121430A CN201711387201.1A CN201711387201A CN108121430A CN 108121430 A CN108121430 A CN 108121430A CN 201711387201 A CN201711387201 A CN 201711387201A CN 108121430 A CN108121430 A CN 108121430A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/30—Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/28—Modifications for introducing a time delay before switching
- H03K17/284—Modifications for introducing a time delay before switching in field effect transistor switches
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/20—Pc systems
- G05B2219/24—Pc safety
- G05B2219/24031—Fpga takes over control if emergency or programmed stop, to shut down sequence
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- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Automation & Control Theory (AREA)
- Power Sources (AREA)
- Electronic Switches (AREA)
Abstract
The present invention discloses a kind of soft boot-strap circuit in the charged pool path for applying to data collecting system, it includes key circuit, CPU, Switching Power Supply, FPGA watchdog circuits, triple gate buffer, battery and PMOS tube power switching circuit, power supply handover module is for mains-supplied and battery powered switching, key circuit is used for system boot, CPU starting-up signals detect and the detection of FPGA starting-up signals, switching pmos enable circuit for controlling the enabled of PMOS tube power switching circuit, FPGA watchdog circuits are used to send off signal during system fault, CPU controls for system switching machine.The present invention is coordinated using hardware and software, and soft boot system is to set long-press that can just work for 2 seconds, greatly reduces the possibility of maloperation.The present invention can trigger shutdown in the case where cpu system crashes by the house dog of FPGA.The present invention can hang the slitless connection that battery powered realizes power supply.
Description
Technical field
The present invention relates to the soft of data collecting field more particularly to a kind of charged pool path for applying to data collecting system
Boot-strap circuit.
Background technology
The utilization of data collecting system is more and more wider, and present data collecting system uses soft boot-strap circuit mostly.But
The soft start of current much numbers more can be all more single.The better soft boot-strap circuit of function increase again many hardware into
This, implement it is also cumbersome, certainly maintainability also have a greatly reduced quality.
Following shortcoming exists in the prior art：1st, all there are unstable easy maloperations for most of soft boot-strap circuit.2nd, it is big
The trigger circuit of the soft boot-strap circuit in part needs independent power supply power supply.3rd, most of soft boot-strap circuit is powered without battery path
Circuit.4th, most of soft boot-strap circuit shutdown is all the direct hot junction for closing Switching Power Supply（Switching power source chip end）.5th, it is most of
Soft boot-strap circuit can not realize Switching Power Supply and the seamless power supply of battery.
The content of the invention
It is an object of the invention to overcome the deficiencies of the prior art and provide a kind of charged pools for applying to data collecting system
The soft boot-strap circuit in path, can take up space small, lightweight, hardware of charged pool, hardware it is reliable and stable, maintainable strong.
The technical solution adopted by the present invention is：
A kind of soft boot-strap circuit in the charged pool path for applying to data collecting system, including key circuit, CPU, switch electricity
Source, FPGA watchdog circuits, triple gate buffer, battery and PMOS tube power switching circuit,
Power supply handover module is for mains-supplied and battery powered switching, and key circuit is for system boot, CPU starting-up signals
Detection and the detection of FPGA starting-up signals, switching pmos enable circuit for controlling the enabled of PMOS tube power switching circuit,
FPGA watchdog circuits are used to send off signal during system fault, and CPU is configured with control instruction and is controlled for system switching machine,
Mains-supplied connecting valve power supply, Switching Power Supply connect battery by a charge management circuit, and CPU connects FPGA and sees respectively
Door dog circuit, triple gate buffer and key circuit, FPGA watchdog circuits connection triple gate buffer, triple gate buffer and
Key circuit connects PMOS switch and enables circuit respectively, and PMOS switch enables circuit, battery and Switching Power Supply and connects PMOS respectively
Pipe power switching circuit, PMOS tube power switching circuit are system power supply, and mains-supplied passes through city's electric signal isolation and shaping
Circuit connects PMOS tube power switching circuit.
Further, switching pmos, which enable circuit, includes resistance R3 and R12,
PMOS tube power switching circuit includes the first PMOS tube, the second PMOS tube, the 3rd PMOS tube, the 4th PMOS tube and the five or two
Pole pipe, the output terminal of battery connect the drain electrode of the first PMOS tube and the anode of the 5th diode respectively,
The cathode of 5th diode, the first PMOS tube connect one end of resistance R12 with the source electrode of the 4th PMOS tube, resistance R12's
The other end, the base stage of the first PMOS tube by the output terminal of charge management circuit connecting valve power supply,
Key circuit includes switch, the second diode, the 3rd diode, one end ground connection of switch, and the switch other end passes through resistance
R7 connects the cathode of the second diode and the 3rd diode respectively, and the anode of the second diode connects the base of the 4th PMOS tube respectively
Pole and the other end of resistance R12, the anode of the 3rd diode connect the button detection pin of CPU, the one of divider resistance R9 respectively
End and one end of divider resistance R13, the button detection pin of the other end connection FPGA of divider resistance R9, divider resistance R13's
The other end connects 3.3V DC power supplies,
The output terminal of Switching Power Supply connects the drain electrode of the second PMOS tube, and the source electrode of the second PMOS tube connects the source of the 3rd PMOS tube
Pole, the second PMOS tube connect one end of resistance R3 with the source electrode of the 3rd PMOS tube, other end connection city's electric signal of resistance R3 every
City's electric signal isolation and shaping circuit are connected respectively from the base stage with shaping circuit, the second PMOS tube and the 3rd PMOS tube,
City's electric signal isolation includes the second triode, the 3rd capacitance, the 6th capacitance, the 7th capacitance, the four or two pole with shaping circuit
Pipe, mains-supplied connect the anode of the 4th diode and one end of resistance R5 respectively by the 6th capacitance, and the 4th diode is born
Pole is by the base stage of resistance R18 the second triodes of connection, and for the cathode of the 4th diode by the 7th capacity earth, resistance R5's is another
One end is grounded, and the base stage of the other end of resistance R3, the second PMOS tube and the 3rd PMOS tube connects the current collection of the second triode respectively
Pole, by the 3rd capacity earth, the emitter of the second triode is grounded the collector of the second triode,
The charge management circuit includes the first diode and the first capacitance, and the output terminal of Switching Power Supply connects the first diode
Anode, the cathode of the first diode connect the base stage of resistance R10, the first capacitance and the first PMOS tube by resistance R6 respectively, electricity
The other end ground connection of R10 and the first capacitance is hindered,
Watchdog circuit includes the first triode, the second capacitance, the 4th capacitance and the 5th capacitance, and the button of CPU keeps pin to connect
One end of connecting resistance R17, the other end of resistance R17 connect the output terminal of triple gate buffer, one end of the second capacitance, electricity respectively
Hinder the other end ground connection of one end of R11 and one end of resistance R16, the second capacitance and resistance R11, the other end connection of resistance R16
The base stage of first triode, the emitter ground connection of the first triode, the collector of the first triode pass through resistance R15 connection resistance
The other end of R12, the triple gate of CPU enable pin and connect one end of resistance R4, one end and three of the 4th capacitance respectively by R8
The other end ground connection of the enabled pin of state door buffer, the grounding pin of triple gate buffer and the 4th capacitance, the house dog of CPU
Input pin connects the input terminal of triple gate buffer and one end of resistance R14, one end of the 5th capacitance, triple gate buffering respectively
The other end of the power end of device, the other end of resistance R4 and resistance R14 connects 3.3V DC power supplies respectively, the 5th capacitance it is another
End ground connection, the output terminal of triple gate buffer connect one end of resistance R1 and the other end of resistance R17 respectively, and resistance R1's is another
End connection 3.3V DC power supplies.
Further, power supply handover module is for mains-supplied and battery powered switching.
Further, triple gate buffer uses SGM7SZ125.
Further, the first PMOS tube, the second PMOS tube, the 3rd PMOS tube and the 4th PMOS tube use CSD25402.
Further, the first triode and the second triode use 2SC2712.
Further, the first diode, the second diode, the 3rd diode and the 4th diode using
1SS355。
Further, the 5th diode uses B140-13-F, and the 5th diode is the pre- power supply in battery powered circuit.
Further, the value of resistance R1 is 10M Ω, and the value of resistance R3, R4, R5 is 100K Ω, resistance R6, R7,
The value of R8, R9 are 100 Ω, and the value of resistance R10, R11, R12, R13, R14 are 10K Ω, and the value of resistance R15 is 10
The value of Ω, resistance R16, R17 are 1K Ω, and the value of resistance R18 is 470 Ω, and the value of capacitance C1, C2, C3, C4 and C5 are
The value of 100nF, capacitance C6 are 1 μ F, and capacitance C7 is 470nF.
The present invention is using above technical scheme, the second PMOS tube and the 3rd PMOS tube when acquisition system uses mains-supplied
Conducting, the first PMOS tube cut-off, when acquisition system use battery powered when the second PMOS tube and the 3rd PMOS tube end, first
PMOS tube turns on.The 4th PMOS tube conducting system normal power supply of two seconds, CPU loadings BIOS are switched at this time.The button detection of CPU
Pin POWER_KEY_CHECK detects push button signalling.CPU does the signal detected start holding processing, puts the button of CPU
It is low level to keep pin POWER_CONTROL, put triple gate enable pin CP_READY also for low level ensure at this time from
Unstable state influences before FPGA is not configured.FPGA is configured after loading BIOS, what FPGA configuration completion automatic runnings were set sees
Door dog circuit.CPU sets the house dog of specific time hello FPGA.And it puts triple gate and enables pin CP_READY as high level.Make
FPGA can discharge high level signal when CPU crash or exception allows the cut-off of the 4th PMOS tube so that system closedown.
The push button signalling test side of the button detection pin FP_POWER_CHECK of FPGA, effect are that some occur in CPU is more special
Fortuitous event under, long-press switch can trigger FPGA within 10 seconds shutdown action.Long-press is opened in the case of system normal operation
Closing 2 seconds can normal shutdown.Normal shutdown signal processing is to detect pin POWER_KEY_CHECK by the button of CPU to pass to
Processing is gone inside CPU.
The present invention is realized using hardware with software cooperation, is once just immediately opened different from other soft boot-strap circuit flickings
Flicking once just shuts down machine immediately again, is so easy to cause maloperation because encounter by mistake, soft boot system of the invention is to set
Putting long-press can just work for 2 seconds, greatly reduce the possibility of maloperation.The present invention can be in the case where cpu system crashes
Shutdown is triggered by the house dog of FPGA.The present invention can hang battery powered and realize that the slitless connection of power supply ensures the steady of system power supply
It is qualitative.
Description of the drawings
The present invention is described in further details below in conjunction with the drawings and specific embodiments；
Fig. 1 is a kind of structure diagram of the soft boot-strap circuit in the charged pool path for applying to data collecting system of the present invention；
Fig. 2 is a kind of circuit structure signal of soft boot-strap circuit in the charged pool path for applying to data collecting system of the present invention
Figure.
Specific embodiment
As shown in the figures 1 and 2, the invention discloses a kind of soft start electricity in charged pool path for applying to data collecting system
Road powers including key circuit, CPU, Switching Power Supply, FPGA watchdog circuits, triple gate buffer U6, battery and PMOS tube
Switching circuit,
Power supply handover module is for mains-supplied and battery powered switching, and key circuit is for system boot, CPU starting-up signals
Detection and the detection of FPGA starting-up signals, switching pmos enable circuit for controlling the enabled of PMOS tube power switching circuit,
FPGA watchdog circuits are used to send off signal during system fault, and CPU is configured with control instruction and is controlled for system switching machine,
Mains-supplied connecting valve power supply, Switching Power Supply connect battery by a charge management circuit, and CPU connects FPGA and sees respectively
Door dog circuit, triple gate buffer U6 and key circuit, FPGA watchdog circuits connection triple gate buffer U6, triple gate buffering
Device U6 and key circuit connect PMOS switch and enable circuit respectively, and PMOS switch enables circuit, battery and Switching Power Supply and connects respectively
PMOS tube power switching circuit is connect, PMOS tube power switching circuit is system power supply, and mains-supplied passes through city's electric signal isolation
PMOS tube power switching circuit is connected with shaping circuit.
Further, switching pmos, which enable circuit, includes resistance R3 and R12,
PMOS tube power switching circuit includes the first PMOS tube U2, the second PMOS tube U3, the 3rd PMOS tube U4, the 4th PMOS tube U5
The drain electrode of the first PMOS tube U2 is connected respectively with the 5th diode D5's with the 5th diode D5, the output terminal V_LI_BAT of battery
Anode,
One end of the source electrode connection resistance R12 of the cathode of 5th diode D5, the first PMOS tube U2 and the 4th PMOS tube U5, resistance
The other end of R12, the base stage of the first PMOS tube U2 by the output terminal of charge management circuit connecting valve power supply,
Key circuit includes switch K1, the second diode D2, the 3rd diode D3, switchs one end ground connection of K1, and switch K1 is another
End connects the cathode of the second diode D2 and the 3rd diode D3 by resistance R7 respectively, and the anode of the second diode D2 connects respectively
The base stage of the 4th PMOS tube U5 and the other end of resistance R12 are connect, the anode of the 3rd diode D3 connects the button detection of CPU respectively
One end of pin, one end of divider resistance R9 and divider resistance R13, the button detection of the other end connection FPGA of divider resistance R9
Pin, the other end connection 3.3V DC power supplies of divider resistance R13,
The output terminal of Switching Power Supply connects the drain electrode of the second PMOS tube U3, and the source electrode of the second PMOS tube U3 connects the 3rd PMOS tube U4
Source electrode, one end of the source electrode connection resistance R3 of the second PMOS tube U3 and the 3rd PMOS tube U4, the other end connection city of resistance R3
The base stage of electric signal isolation and shaping circuit, the second PMOS tube U3 and the 3rd PMOS tube U4 connect respectively city's electric signal isolation with it is whole
Shape circuit,
City's electric signal isolation and shaping circuit include the second triode Q2, the 3rd capacitance C3, the 6th capacitance C6, the 7th capacitance C7,
4th diode D4, mains-supplied AC_TRIG connect the anode of the 4th diode D4 and resistance R5 respectively by the 6th capacitance C6
One end, the cathode of the 4th diode D4 passes through the base stage of resistance R18 the second triodes of connection Q2, the cathode of the 4th diode D4
It is grounded by the 7th capacitance C7, the other end ground connection of resistance R5, the other end of resistance R3, the second PMOS tube U3 and the 3rd PMOS tube
The base stage of U4 connects the collector of the second triode Q2 respectively, and the collector of the second triode Q2 is grounded by the 3rd capacitance C3,
The emitter ground connection of second triode Q2,
The charge management circuit includes the first diode D1 and the first capacitance C1, the output terminal VIN+ connections first of Switching Power Supply
The anode of diode D1, the cathode of the first diode D1 connect resistance R10, the first capacitance C1 and first respectively by resistance R6
The other end ground connection of the base stage of PMOS tube U2, resistance R10 and the first capacitance C1,
FPGA watchdog circuits include pressing for the first triode Q1, the second capacitance C2, the 4th capacitance C4 and the 5th capacitance C5, CPU
Key keeps one end of pin POWER_CONTROL connection resistance R17, and the other end of resistance R17 connects triple gate buffer respectively
The output terminal of U6, one end of the second capacitance C2, one end of one end of resistance R11 and resistance R16, the second capacitance C2 and resistance R11
Other end ground connection, the other end of resistance R16 connects the base stage of the first triode Q1, the emitter ground connection of the first triode Q1,
The collector of first triode Q1 enables pin CP_ by the other end of resistance R15 connection resistance R12, the triple gate of CPU
READY connected respectively by R8 the enabled pin of one end of resistance R4, one end of the 4th capacitance C4 and triple gate buffer U6/
The other end ground connection of the grounding pin GND and the 4th capacitance C4 of OE, triple gate buffer U6, the house dog input pin FP_ of CPU
WD connects one end of the input terminal A and resistance R14 of triple gate buffer U6, one end of the 5th capacitance C5, triple gate buffering respectively
The other end of the power end VCC of device U6, the other end of resistance R4 and resistance R14 connect 3.3V DC power supplies, the 5th capacitance respectively
The other end ground connection of C5, the output terminal of triple gate buffer U6 connect one end of resistance R1 and the other end of resistance R17 respectively, electricity
Hinder the other end connection 3.3V DC power supplies of R1.
Further, power supply handover module is for mains-supplied AC_TRIG and battery powered switching.
Further, triple gate buffer U6 uses SGM7SZ125.
Further, the first PMOS tube U2, the second PMOS tube U3, the 3rd PMOS tube U4 and the 4th PMOS tube U5 are used
CSD25402。
Further, the first triode Q1 and the second triode Q2 uses 2SC2712.
Further, the first diode D1, the second diode D2, the 3rd diode D3 and the 4th diode D4 are used
It is 1SS355.
Further, it is the pre- confession in battery powered circuit that the 5th diode D5, which uses B140-13-F, the 5th diode D5,
Electricity.
Further, the value of resistance R1 is 10M Ω, and the value of resistance R3, R4, R5 is 100K Ω, resistance R6, R7,
The value of R8, R9 are 100 Ω, and the value of resistance R10, R11, R12, R13, R14 are 10K Ω, and the value of resistance R15 is 10
The value of Ω, resistance R16, R17 are 1K Ω, and the value of resistance R18 is 470 Ω, and the value of capacitance C1, C2, C3, C4 and C5 are
The value of 100nF, capacitance C6 are 1 μ F, and capacitance C7 is 470nF.
As shown in Fig. 2, the circuit of the present invention is divided into following components：1. U2, U3, U4, U5 are used for for P-channel metal-oxide-semiconductor
Mains-supplied switches with battery powered.2. R5, R18, C3, C6, C7, Q2, D4 and signal AC_TRIG are used to control leading for U3 and U4
It is logical.3. D1, R6, R10, C1 are for controlling the conducting of U2,4. D2, D3, R7, R9, R13, K1 start shooting for start and CPU and FPGA
Signal detection.5. R3, R12 are the control that biasing resistor is used for PMOS.6. by R1, R4, R8, R11, R14, R15, R16, R17,
Q1, C2, C4, C5, U6 composition CPU starts are kept and FPGA watchdog circuits.7. VIN+ is the output voltage of Switching Power Supply.V_
LI_BAT is cell output voltage.AC_TRIG triggers for alternating current.POWER_KEY_CHECK detects signal for CPU buttons.FP_
POWER_CHECK detects signal for FPGA buttons.POWER_CONTROL keeps signal for CPU buttons.CP_READY is CPU's
Triple gate enable signal.The house dog that FP_WD is FPGA exports signal.POW_FP_CTRL is the output signal of triple gate.D5 is
The pre- of battery powered circuit supplies electric diode.
The present invention using above technical scheme, when acquisition system uses mains-supplied AC_TRIG the second PMOS tube U3 and
3rd PMOS tube U4 turn on, the first PMOS tube U2 cut-off, when acquisition system use battery powered when the second PMOS tube U3 and the 3rd
PMOS tube U4 ends, the first PMOS tube U2 conductings.K1 the 4th PMOS tube U5 of two seconds conducting system normal power supplies are switched at this time,
CPU loads BIOS.The button detection pin POWER_KEY_CHECK of CPU detects push button signalling.CPU is to the signal that detects
Start holding processing is done, the button for putting CPU keeps pin POWER_CONTROLPOWER_CONTROL to put triple gate for low level
Unstable state influences before enabled pin CP_READYCP_READY is not configured from FPGA at this time for low level guarantee yet.Loading
FPGA is configured after BIOS, the watchdog circuit that automatic running is set is completed in FPGA configurations.CPU sets specific time to feed FPGA's
House dog.And it puts triple gate and enables pin CP_READYCP_READY as high level.Make FPGA when CPU crashes or is abnormal
High level signal can be discharged and allow the 4th PMOS tube U5 cut-offs so that system closedown.The button detection pin FP_ of FPGA
The push button signalling test side of POWER_CHECK, effect are that some occur more specifically under fortuitous event in CPU, long-press switch
The shutdown action that FPGA can be triggered in K110 seconds.Long-press switch K12 seconds can normal shutdown in the case of system normal operation.
Normal shutdown signal processing is to pass to inside CPU to go processing by the button detection pin POWER_KEY_CHECK of CPU.
The present invention is realized using hardware with software cooperation, is once just immediately opened different from other soft boot-strap circuit flickings
Flicking once just shuts down machine immediately again, is so easy to cause maloperation because encounter by mistake, soft boot system of the invention is to set
Putting long-press can just work for 2 seconds, greatly reduce the possibility of maloperation.The present invention can be in the case where cpu system crashes
Shutdown is triggered by the house dog of FPGA.The present invention can hang battery powered and realize that the slitless connection of power supply ensures the steady of system power supply
It is qualitative.
Claims (9)
1. a kind of soft boot-strap circuit in the charged pool path for applying to data collecting system, it is characterised in that：It includes button electricity
Road, CPU, Switching Power Supply, FPGA watchdog circuits, triple gate buffer, battery and PMOS tube power switching circuit,
Power supply handover module is for mains-supplied and battery powered switching, and key circuit is for system boot, CPU starting-up signals
Detection and the detection of FPGA starting-up signals, switching pmos enable circuit for controlling the enabled of PMOS tube power switching circuit,
FPGA watchdog circuits are used to send off signal during system fault, and CPU is configured with control instruction and is controlled for system switching machine,
Mains-supplied connecting valve power supply, Switching Power Supply connect battery by a charge management circuit, and CPU connects FPGA and sees respectively
Door dog circuit, triple gate buffer and key circuit, FPGA watchdog circuits connection triple gate buffer, triple gate buffer and
Key circuit connects PMOS switch and enables circuit respectively, and PMOS switch enables circuit, battery and Switching Power Supply and connects PMOS respectively
Pipe power switching circuit, PMOS tube power switching circuit are system power supply, and mains-supplied passes through city's electric signal isolation and shaping
Circuit connects PMOS tube power switching circuit.
2. a kind of soft boot-strap circuit in charged pool path for applying to data collecting system according to claim 1, special
Sign is：The switching pmos, which enable circuit, includes resistance R3 and R12,
PMOS tube power switching circuit includes the first PMOS tube, the second PMOS tube, the 3rd PMOS tube, the 4th PMOS tube and the five or two
Pole pipe, the output terminal of battery connect the drain electrode of the first PMOS tube and the anode of the 5th diode respectively,
The cathode of 5th diode, the first PMOS tube connect one end of resistance R12 with the source electrode of the 4th PMOS tube, resistance R12's
The other end, the base stage of the first PMOS tube by the output terminal of charge management circuit connecting valve power supply,
Key circuit includes switch, the second diode, the 3rd diode, one end ground connection of switch, and the switch other end passes through resistance
R7 connects the cathode of the second diode and the 3rd diode respectively, and the anode of the second diode connects the base of the 4th PMOS tube respectively
Pole and the other end of resistance R12, the anode of the 3rd diode connect the button detection pin of CPU, the one of divider resistance R9 respectively
End and one end of divider resistance R13, the button detection pin of the other end connection FPGA of divider resistance R9, divider resistance R13's
The other end connects 3.3V DC power supplies,
The output terminal of Switching Power Supply connects the drain electrode of the second PMOS tube, and the source electrode of the second PMOS tube connects the source of the 3rd PMOS tube
Pole, the second PMOS tube connect one end of resistance R3 with the source electrode of the 3rd PMOS tube, other end connection city's electric signal of resistance R3 every
City's electric signal isolation and shaping circuit are connected respectively from the base stage with shaping circuit, the second PMOS tube and the 3rd PMOS tube,
City's electric signal isolation includes the second triode, the 3rd capacitance, the 6th capacitance, the 7th capacitance, the four or two pole with shaping circuit
Pipe, mains-supplied connect the anode of the 4th diode and one end of resistance R5 respectively by the 6th capacitance, and the 4th diode is born
Pole is by the base stage of resistance R18 the second triodes of connection, and for the cathode of the 4th diode by the 7th capacity earth, resistance R5's is another
One end is grounded, and the base stage of the other end of resistance R3, the second PMOS tube and the 3rd PMOS tube connects the current collection of the second triode respectively
Pole, by the 3rd capacity earth, the emitter of the second triode is grounded the collector of the second triode,
The charge management circuit includes the first diode and the first capacitance, and the output terminal of Switching Power Supply connects the first diode
Anode, the cathode of the first diode connect the base stage of resistance R10, the first capacitance and the first PMOS tube by resistance R6 respectively, electricity
The other end ground connection of R10 and the first capacitance is hindered,
FPGA watchdog circuits include the first triode, the second capacitance, the 4th capacitance and the 5th capacitance, and the button holding of CPU is drawn
One end of foot connection resistance R17, the other end of resistance R17 connect the output terminal of triple gate buffer, the one of the second capacitance respectively
The other end ground connection of the one end at end, one end of resistance R11 and resistance R16, the second capacitance and resistance R11, the other end of resistance R16
The base stage of the first triode, the emitter ground connection of the first triode are connected, the collector of the first triode is connected by resistance R15
The other end of resistance R12, the triple gate of CPU enable pin and connect one end of resistance R4, one end of the 4th capacitance respectively by R8
With the enabled pin of triple gate buffer, the other end ground connection of the grounding pin of triple gate buffer and the 4th capacitance, CPU's sees
Door dog input pin connects the input terminal of triple gate buffer and one end of resistance R14, one end of the 5th capacitance, triple gate respectively
The other end of the power end of buffer, the other end of resistance R4 and resistance R14 connects 3.3V DC power supplies respectively, the 5th capacitance
The other end is grounded, and the output terminal of triple gate buffer connects one end of resistance R1 and the other end of resistance R17 respectively, resistance R1's
The other end connects 3.3V DC power supplies.
3. a kind of soft boot-strap circuit in charged pool path for applying to data collecting system according to claim 2, special
Sign is：The power supply handover module is for mains-supplied and battery powered switching.
4. a kind of soft boot-strap circuit in charged pool path for applying to data collecting system according to claim 2, special
Sign is：The triple gate buffer uses SGM7SZ125.
5. a kind of soft boot-strap circuit in charged pool path for applying to data collecting system according to claim 2, special
Sign is：First PMOS tube, the second PMOS tube, the 3rd PMOS tube and the 4th PMOS tube use CSD25402.
6. a kind of soft boot-strap circuit in charged pool path for applying to data collecting system according to claim 2, special
Sign is：First triode and the second triode use 2SC2712.
7. a kind of soft boot-strap circuit in charged pool path for applying to data collecting system according to claim 2, special
Sign is：First diode, the second diode, the 3rd diode and the 4th diode are using 1SS355.
8. a kind of soft boot-strap circuit in charged pool path for applying to data collecting system according to claim 2, special
Sign is：5th diode uses B140-13-F, and the 5th diode is the pre- power supply in battery powered circuit.
9. a kind of soft boot-strap circuit in charged pool path for applying to data collecting system according to claim 2, special
Sign is：The value of resistance R1 is 10M Ω, and the value of resistance R3, R4, R5 is 100K Ω, the value of resistance R6, R7, R8, R9
It is 100 Ω, the value of resistance R10, R11, R12, R13, R14 is 10K Ω, and the value of resistance R15 is 10 Ω, resistance R16,
The value of R17 is 1K Ω, and the value of resistance R18 is 470 Ω, and the value of capacitance C1, C2, C3, C4 and C5 is 100nF, capacitance
The value of C6 is 1 μ F, and capacitance C7 is 470nF.
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