CN109194317A - A kind of reset circuit and wearable device - Google Patents
A kind of reset circuit and wearable device Download PDFInfo
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- CN109194317A CN109194317A CN201811029710.1A CN201811029710A CN109194317A CN 109194317 A CN109194317 A CN 109194317A CN 201811029710 A CN201811029710 A CN 201811029710A CN 109194317 A CN109194317 A CN 109194317A
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- nand gate
- power supply
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/24—Resetting means
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- General Engineering & Computer Science (AREA)
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Abstract
The invention discloses a kind of reset circuit and wearable devices, it applies in the electronic product with charging interface and main control chip, such as wearable device, including NAND gate, the first input end of the NAND gate connects charging interface by capacitance, second input terminal connects the anode of storage capacitor, the pwm signal output pin of the anode connection main control chip of the storage capacitor, and connects DC power supply by resistance；The main control chip adjusts the duty ratio of the pwm signal of its output, makes the anodic potentials of storage capacitor when pwm signal is normal lower than critical potential V0, and for the NAND gate by its output end output reset signal, the reset signal low level is effective.Reset circuit of the invention is not necessarily to the individually designed reset key on product, only need to be by charging interface existing on product, i.e. controllable product resets in the case where external charge power supply, and circuit design is simple, compared to traditional reset circuit, there is greater flexibility and usability.
Description
Technical field
The invention belongs to reset circuit technical fields, specifically, being to be related to a kind of pass through to be inserted into charge power supply control electricity
The circuit design that sub- product resets.
Background technique
With the fast development of electronic technology, the type of portable electronic product is increasingly various, such as mobile phone, plate electricity
Brain, wearable device (such as Intelligent bracelet etc.) etc., bring great convenience to daily life.Current electronics produces
Product, in use often its system software run fly or misoperation etc. due to and cause what crashing occurred in product to ask
Topic, then causes product can not work normally, it is necessary to execute and the operation such as restart or reset.
Existing portable electronic product, the resetting technique used generally include two kinds: one is power-off restorations, that is,
The battery in electronic product is taken out, resets the circuit system in product because of power down；Another kind is the special reset electricity of design
Road generates reset signal using reset circuit, and control main control chip reset is restarted.Both reset modes, from the convenience of operation
Property angle consider that latter approach is obviously more convenient, but generally require to be separately configured on the shell of electronic product reset by
The hardware such as key are resetted to trigger the main control chip of interiors of products.This structure design needs to open on the shell of electronic product
Hole, on the one hand will affect the succinct and aesthetics of product appearance, and on the other hand also will increase that foreign matter, electrostatic etc. enters product can
Energy property, the deterioration of safety for causing product to use.In addition, for dressing electronic product, as user is to wearing product
The promotion of demand, it is desirable that wearing electronic product develops to miniaturization, multi-functional, high-performance direction, just because of this, many to dress
Electronic product design when physical button can not be set on product, this make product when actually using and being abnormal very
Difficulty controls product in such a way that key triggers and resets, and restores to operate normally.If user can not conveniently and efficiently control product
Restore normal, it will a degree of influence is generated on the degree of belief of product brand.
Based on this, need to design one kind it is not necessary that reset key is separately configured, without the battery extracted in electronic product, i.e.,
The circuit design of controllable system parking position accuracy.
Summary of the invention
The purpose of the present invention is to provide a kind of reset circuit, can by the way of being inserted into charge power supply control system it is quasi-
It really resets, to simplify the structure design of product, the reset of user is facilitated to operate.
In order to solve the above technical problems, the present invention is achieved by the following scheme:
In one aspect, it the invention proposes a kind of reset circuit, applies and is produced in the electronics with charging interface and main control chip
In product, the main control chip operating system program and the output pwm signal when operating normally；The reset circuit include with it is non-
The first input end of door, the NAND gate connects the charging interface by capacitance, and the second input terminal connects storage capacitor
Anode, the pwm signal output pin of the anode connection main control chip of the storage capacitor and connects direct current by resistance
Source；The main control chip adjusts the duty ratio of the pwm signal of its output, keeps the anodic potentials of storage capacitor normal in pwm signal
When be lower than critical potential V0, the critical potential V0 be less than the DC power supply current potential, and for the NAND gate distinguish input
The separation of the low and high level state of signal, for the NAND gate by its output end output reset signal, the reset signal is low
Level is effective.
When the NAND gate is the NAND gate of open-drain output, since this NAND gate is when exporting high level, high electricity
Flat current potential is determined by the pull-up power supply of the output end of external NAND gate, therefore, can use the reset of such NAND gate generation
Signal carries out making can control to the direct current regulation circuit in electronic product, to reach the whole system circuit power down to electronic product
The purpose of reset.Based on this, the output end of the NAND gate is connected to the direct current regulation circuit in electronic product by the present invention
Enable end, and pull-up circuit is connected, the direct current regulation circuit high level is enabled, generates needed for the circuit system in electronic product
Working power.
Further, the pull-up circuit includes pull-up resistor and pull-up power supply, and the output end of the NAND gate passes through institute
It states pull-up resistor and connects the pull-up power supply, the battery supply or battery supply that the pull-up power supply is electronic product are after dividing
Power supply.Since the pull-up power supply still has during circuit system resets, it can guarantee that direct current regulation circuit is being
It can enable to run again after system circuit power-off reset, working power needed for output system circuit, control system circuit is automatic
Restart operation.
It is high since this NAND gate is when exporting high level when the NAND gate is the NAND gate of non-open-drain output
The current potential of level is determined by the power supply of NAND gate, usually lower, can not be as enable signal to the direct current in electronic product
Voltage regulator circuit carries out making can control, and therefore, the present invention is using the reset signal of such NAND gate output to the master in electronic product
Control chip carries out reset control；That is, when the main control chip low level resets, it can be direct by the output end of the NAND gate
It is connected to the reset pin of main control chip；And when the main control chip high level resets, it can be by the output of the NAND gate
End connects the reset pin of main control chip by negater circuit, provides high level effective reset signal for main control chip.
It, can be in the charging when the current potential of charge power supply, which is higher than NAND gate, to be required the current potential upper limit value of input signal
Bleeder circuit is connected between interface and the first input end of the NAND gate, is passed through by the charge power supply that the charging interface accesses
After bleeder circuit partial pressure, then it is transmitted to the first input end of the NAND gate, by the first input end of the NAND gate
It is set to high level.
In order to carry out voltage clamping to the signal for being input to the NAND gate, to achieve the purpose that protect NAND gate, this hair
It is bright to be also set up in the reset circuit there are two clamp diode；Wherein, described in the cathode connection by the first clamp diode
The first input end of NAND gate, plus earth, to eliminate the negative pulse generated when charge power supply is extracted from charging interface；By second
The cathode of clamp diode connects the DC power supply, and anode connects the second input terminal of the NAND gate, is input to limitation
The current potential of second input terminal does not exceed the current potential of the DC power supply.
Based on above-mentioned reset circuit, the invention also provides a kind of wearable device, including charging interface, main control chip and
NAND gate；The main control chip operating system program and the output pwm signal when operating normally；First input of the NAND gate
End connects the charging interface by capacitance, and the second input terminal connects the anode of storage capacitor, and the storage capacitor is just
Pole connects the pwm signal output pin of main control chip, and connects DC power supply by resistance；The main control chip adjusts its output
Pwm signal duty ratio, make the anodic potentials of storage capacitor when pwm signal is normal lower than critical potential V0, it is described critical
Current potential V0 is less than the current potential of the DC power supply, and the boundary of the low and high level state for NAND gate differentiation input signal
Point, for the NAND gate by its output end output reset signal, the reset signal low level is effective.
On the other hand, it the invention also provides another reset circuit, applies with charging interface and master control
In the electronic product of chip, the main control chip operating system program and the output pwm signal when operating normally；The reset electricity
Road include with door and NMOS tube, it is described that the charging interface, the second input are connect by capacitance with the first input end of door
The anode of end connection storage capacitor, the pwm signal output pin of the anode connection main control chip of the storage capacitor, and pass through electricity
Resistance connection DC power supply；The main control chip adjusts the duty ratio of the pwm signal of its output, and the anodic potentials of storage capacitor is made to exist
It is lower than critical potential V0 when pwm signal is normal, the critical potential V0 is less than the current potential of the DC power supply, and is described and door
Distinguish the separation of the low and high level state of input signal；The grid that NMOS tube is connect with the output end of door, NMOS tube
Source electrode ground connection, drain electrode connection pull-up circuit, by the drain electrode output reset signal of the NMOS tube, the reset signal low level
Effectively.
Preferably, the drain electrode of the NMOS tube is connected to the enable end of the direct current regulation circuit in electronic product, it is described
Direct current regulation circuit high level is enabled, working power needed for generating the circuit system in electronic product.Utilize the leakage of NMOS tube
The reset signal of pole output carries out making can control to direct current regulation circuit, when system program runs winged, passes through and controls DC voltage-stabilizing
Circuit is out of service, can control the circuit system power-off reset in electronic product.
Further, the pull-up circuit includes pull-up resistor and pull-up power supply, and the drain electrode of the NMOS tube passes through described
Pull-up resistor connects the pull-up power supply, and the battery supply or battery supply that the pull-up power supply is electronic product are after dividing
Power supply.Select the power supply of battery supply or battery supply after dividing as the pull-up power supply, since the pull-up power supply is being
It is still had during system circuit reset, therefore can guarantee that direct current regulation circuit can make again after circuit system power-off reset
It can run, working power needed for output system circuit, control system circuit is restarted automatically operation.
Further, bleeder circuit, the first clamp diode and the second clamper two are additionally provided in the reset circuit
Pole pipe；The bleeder circuit is connected to the charging interface and described between the first input end of door, to passing through the charging
After the charge power supply of interface access is divided, it is transmitted to the first input end with door；First clamp diode
The cathode connection first input end with door, plus earth clamp down on the current potential lower limit value of input signal in 0V；Described second
The cathode of clamp diode connects the DC power supply, anode connection second input terminal with door, by the electricity of input signal
Position upper limit value clamps down on the current potential in the DC power supply, thus realizes voltage clamping protection to the input terminal of door.
Based on above-mentioned reset circuit, the invention also provides a kind of wearable device, including charging interface, main control chip,
With door and NMOS tube；The main control chip operating system program and the output pwm signal when operating normally；First with door
Input terminal connects the charging interface by capacitance, and the second input terminal connects the anode of storage capacitor, the storage capacitor
Anode connection main control chip pwm signal output pin, and DC power supply is connected by resistance；The main control chip adjusts it
The duty ratio of the pwm signal of output makes the anodic potentials of storage capacitor when pwm signal is normal lower than critical potential V0, described
Critical potential V0 is less than the current potential of the DC power supply, and is the boundary of the low and high level state that input signal is distinguished with door
Point；The grid that NMOS tube is connect with the output end of door, the source electrode ground connection of NMOS tube, drain electrode connection pull-up circuit pass through institute
The drain electrode output reset signal of NMOS tube is stated, the reset signal low level is effective.
Compared with prior art, the advantages and positive effects of the present invention are: reset circuit of the invention is not necessarily on product
Individually designed reset key, only need to be by charging interface existing on product, can be to production in the case where external charge power supply
Main control chip in product, which is realized, resets operation, and circuit design is simple, compared to traditional reset circuit, have more flexibilities and
Usability, and solve conventional RESET circuit because add Structure of need aperture brought by reset key, easily by sundries or
Electrostatic introduces the problems such as interiors of products, improves the safety and reliability that product uses, and be conducive to improvement user uses body
It tests.
After the detailed description of embodiment of the present invention is read in conjunction with the figure, other features and advantages of the invention will become more
Add clear.
Detailed description of the invention
Fig. 1 is the circuit diagram of the first embodiment of reset circuit proposed by the invention；
Fig. 2 is the circuit diagram of second of embodiment of reset circuit proposed by the invention；
Fig. 3 is the circuit diagram of the third embodiment of reset circuit proposed by the invention.
Specific embodiment
A specific embodiment of the invention is described in more detail with reference to the accompanying drawing.
The present invention is directed to the abnormal crash situation that user is encountered during using portable electronic product, proposes one
Kind can be by a scene most common in user's use process --- charging, to control the side of electronic product Rapid reset
Method.Using the repositioning method, without increasing reset key on electronic product, therefore the existing outer of electronic product will not be changed
It sees.When electronic product crashes, the charging interface of external charge power supply access electronic product, i.e., controllable electronics need to only be produced
Product automatically reset, and restart operation, easy to operate, easy to use.
For the present invention is using wearable device as the electronic product, by two specific embodiments, to the present invention
Reset circuit specific route design and its working principle be described in detail.
Embodiment one, as shown in Figure 1, the reset circuit of the present embodiment using NAND gate U1 cooperation charge power supply VBUS and
The pwm signal that main control chip MCU is exported when operating normally carries out circuit design, including NAND gate U1, capacitance C1, energy storage
The chief components such as capacitor C3, resistance R3, DC power supply VDD_1V8.Wherein, the NAND gate U1 is the knot with door and NOT gate
It closes, the one chip being integrated with door and NOT gate can be selected, one can also be selected to combine with door and a NOT gate in fact
It is existing.The NAND gate U1 of the present embodiment includes above two form.Capacitance C1 is connected to the first defeated of the NAND gate U1
Enter to hold between A and the charging interface (being illustrated by taking USB interface as an example) of wearable device, be accessed to by charging interface USB
Charge power supply VBUS carry out DC isolation, so that the first input end A of NAND gate U1 is only inserted into charging interface USB in charge power supply
Moment be set to high level, remaining time is low level.The second input terminal B connection storage capacitor C3 of NAND gate U1 is just
Pole, the cathode ground connection of storage capacitor C3.By the pwm signal output pin I/ of the anode connection main control chip MCU of storage capacitor C3
O, and DC power supply VDD_1V8 is connected to by resistance R3, the PWM exported using DC power supply VDD_1V8 and main control chip MCU
Signal carries out charge and discharge control to storage capacitor C3, by adjusting the duty ratio of pwm signal, makes the second input terminal of NAND gate U1
B only can not be set to high level during output pwm signal due to system program runs winged in main control chip.Thus one, when can
When wearable device crashes extremely and user performs charging operations to wearable device, two input terminals A, B of NAND gate U1 exist
The moment that charge power supply is inserted on charging interface USB is simultaneously high level, exports the effective reset signal MCU_RST of low level.
In order to tie up the current potential on storage capacitor C3 can always during main control chip MCU normal output pwm signal
It holds and thinks that input signal is that (the critical potential V0 right and wrong door U1 is distinguished low level critical potential V0 or less in NAND gate U1
Input signal is high level or low level separation, and amplitude is less than the current potential of DC power supply VDD_1V8.For example, direct current
Power vd D_1V8 is 1.8V, and critical potential V0 is 1.3V, when NAND gate U1 receives the input signal of 1.3V or more, is determined
Input signal is high level；When NAND gate U1 receives 1.3V input signal below, determine that input signal is low level),
The duty ratio that the pwm signal of its output can be adjusted by main control chip MCU, when pwm signal is high level, DC power supply
VDD_1V8 charges to storage capacitor C3 by resistance R3, increases the current potential on storage capacitor C3 anode.Storage capacitor C3's
When anodic potentials are also not up to the critical potential V0, pwm signal switchs to low level, and storage capacitor C3 passes through main control chip at this time
Pwm signal output pin I/O electric discharge, the current potential on storage capacitor C3 anode declines, therefore ensures that in the pwm signal normal phase
Between, the current potential on the second input terminal B of NAND gate U1 is always low.Pwm signal normally indicates the system journey in main control chip MCU
Sort run is normal, and during this period, no matter whether there is or not charge power supply VBUS access, the first inputs of NAND gate U1 on charging interface USB
End A on current potential be height be it is low, the output end Y of NAND gate U1 exports high level always, that is, reset signal MCU_RST is invalid.
When in main control chip MCU system program run fly, can not output pwm signal when, main control chip pwm signal output
Pin I/O keeps high potential or is in high-impedance state, at this point, storage capacitor C3 keeps charged state, until its anodic potentials is equal to directly
The current potential of galvanic electricity source VDD_1V8, charging terminate.When the anodic potentials of storage capacitor C3 are equal to the current potential of DC power supply VDD_1V8
When, the input signal that NAND gate U1 determines that its second input terminal B is received is high level, if user is not carried out charging during this period
Operation, then the current potential on the first input end A of NAND gate U1 is always low, and the output end Y of NAND gate U1 persistently exports high level,
I.e. invalid reset signal MCU_RST, thus wearable device maintains crash state.To restart wearable device reset, use
Charge power supply can be inserted on charging interface USB by family, in the moment of charging interface USB access charge power supply VBUS, connection
Current potential is got higher by low on the power circuit of charging interface USB, and the first input end of NAND gate U1 is applied to by capacitance C1
A keeps the current potential on the first input end A of NAND gate U1 high, runs through NAND Logic, make the electricity of the output end Y of NAND gate U1
Position is low, the generation effective reset signal MCU_RST of low level, to be resetted for controlling the circuit system in wearable device,
Restart operation.
Then, since charge power supply VBUS is DC power supply, under the action of capacitance C1 separated by direct communication, so that with non-
Current potential on the first input end A of door U1 switchs to low level again, and the output end Y of NAND gate U1 is set to high level again, resets control
System terminates, and wearable device enters normal charging process.
In view of current potential of the NAND gate U1 to input signal is limited, for charge power supply VBUS current potential be greater than with it is non-
It the case where door U1 institute's receptible maximum input voltage, can be in the first input end A of charging interface USB and the NAND gate U1
Between add bleeder circuit, such as divider resistance R1 is connected between charging interface USB and capacitance C1, by divider resistance
R2 is connected between the first input end A of NAND gate U1 and ground, is divided using divider resistance R1, R2 to charge power supply VBUS
Processing, with generate amplitude greater than critical voltage V0 and be less than NAND gate U1 receptible maximum input voltage input signal,
It is applied to the first input end A of NAND gate U1, the first input end A of NAND gate U1 is set to high potential.
It, can be in the first input end A connection filter capacitor C2 of NAND gate U1, with suppression for the stability for guaranteeing input signal
System interference.
In view of extracting the moment of charging interface USB in charge power supply VBUS, because of the presence of capacitance C1, it is possible to meeting
Negative pulse is generated in the first input end A of NAND gate U1, NAND gate U1 is caused to damage.For this purpose, the present embodiment is NAND gate U1's
First input end A connection the first clamp diode D1, as shown in Figure 1, by the cathode of the first clamp diode D1 be connected to it is non-
The current potential of the first input end A of NAND gate U1 is then clamped down in 0V or more, is avoided by the first input end A of door U1, plus earth
The appearance of negative pulse.
Similarly, it can connect two pole of the second clamper between the second input terminal B and DC power supply VDD_1V8 of NAND gate U1
Pipe D2, as shown in Figure 1, the cathode of the second clamp diode D2 is connected to DC power supply VDD_1V8, anode is connected to NAND gate
The second input terminal B of U1 then clamps down on the current potential of the second input terminal B of NAND gate U1 in 1.8V hereinafter, avoiding NAND gate U1
It is damaged by overvoltage impact
In order to control wearable device parking position accuracy using the reset signal MCU_RST of NAND gate U1 output, the present embodiment is proposed
Following two control mode:
One is for the NAND gate U1 of OD output (open-drain output), since this NAND gate is when exporting high level,
The current potential of high level is determined by the pull-up power supply of the output end Y of external NAND gate U1, therefore, can use such NAND gate U1 production
Raw reset signal MCU_RST carries out making can control to the direct current regulation circuit U2 in wearable device, wearable by controlling
Circuit system (including main control chip MCU and other power loads, such as various kinds of sensors etc.) instantaneous power-down in equipment, to reach
The purpose restarted is resetted to product.
Based on this, the present embodiment such as is connected by pull-up resistor R4 in the output end Y1 connection pull-up circuit of NAND gate U1
Pull-up power supply VSYS is met, as shown in Figure 1.When NAND gate U1 exports high level, pull-up power supply VSYS is by the output of NAND gate U1
End Y1 current potential is drawn high to the current potential of pull-up power supply VSYS.Select the input power Vin of direct current regulation circuit U2 as described upper
Power supply VSYS is drawn, it is possible thereby to which the reset signal MCU_RST that NAND gate U1 is exported is transmitted to DC voltage-stabilizing as enable signal
The enable end EN of circuit U 2.The direct current regulation circuit U2 high level is enabled, system program during normal operation, NAND gate U1
Export high level signal, the enabled operation of control direct current regulation circuit U2, work needed for generating the circuit system in wearable device
Make power supply, such as DC power supply VDD_1V8 etc., meets the power demand of each power load in circuit system.And it wearable ought set
When standby crash, since the reset signal MCU_RST of NAND gate U1 output is low level, direct current regulation circuit U2 is out of service, no
Output power supply again, at this time the circuit system power-off reset in wearable device.Then, the reset signal of NAND gate U1 output
MCU_RST switchs to high level again, and control direct current regulation circuit U2 is enabled to be run, working power needed for output system circuit,
Control system circuit restarts operation, completes the reset operation of wearable device.
After a power failure, output end Y is in high-impedance state to the NAND gate U1 of the present embodiment, in order to ensure direct current regulation circuit U2 exists
It can enable to run automatically after reset that system is powered down, be powered on and restarted with control system circuit, the present embodiment selects wearable device
In power supply after dividing of battery supply or battery supply as the pull-up power supply VSYS.Due to pull-up power supply VSYS
It is still had during circuit system power down, therefore, when circuit system resets, remains to power for direct current regulation circuit U2, and
It provides high level effective enable signal for direct current regulation circuit U2 after NAND gate U1 power down, makes direct current regulation circuit U2 again
It is enabled, it is recovered immediately after control system circuit power down, has not only achieved the purpose that abundant reset, but also wearable device is being occurred
When software anomaly, it can restore normal in the very short time of insertion charge power supply and start to charge, be not necessarily to other operation bidirectionals
(such as pull up charger etc.), it is convenient and efficient.
The second is for the NAND gate U1 of non-OD output (non-open-drain output), since this NAND gate U1 is being exported
When high level, the current potential of high level is determined by the power supply of NAND gate U1, usually lower, such as the DC power supply of 1.8V,
And the then more demanding current potential of enable signal needed for the direct current regulation circuit in wearable device, generally in 3.3V or more, because
This, can not be using the reset signal MCU_RST that NAND gate U1 is exported as enable signal, to the DC voltage-stabilizing electricity in wearable device
Road carries out making can control, and realizes the power-off reset of circuit system.
Based on the above reasons, the present embodiment exports non-OD NAND gate U1 and main control chip MCU cooperates, using such with
The reset signal MCU_RST of NOT gate U1 output carries out reset control to the main control chip MCU in wearable device, is led by control
Operation is restarted in system program reset in control chip MCU, to realize that the warm reset to wearable device controls.
In view of different types of main control chip MCU, there is different requirements to the low and high level state of reset signal.For
For the main control chip MCU that low level resets, as shown in Fig. 2, the output end Y of the NAND gate U1 can be connected directly to master
Reset pin/the RST for controlling chip MCU, when the system program exception of main control chip MCU operation, and charging interface USB insertion is charged
When power supply, a low level pulse is exported by NAND gate U1, control main control chip MCU reset is restarted, and realizes system reset.And
For the main control chip MCU that high level resets, negater circuit can be increased in the output end Y of NAND gate U1, by reversed
The reset pin of circuit connection main control chip MCU provides high level effective reset signal for main control chip MCU.
Embodiment two, compared with embodiment one, difference is the present embodiment: real using replacing with door U3 and NMOS tube Q1
Apply the NAND gate U1 design reset circuit in example one.
Specifically, wearable by being connected to the first input end IN1 of door U3 by the capacitance C1 of series connection with it
The charging interface USB of equipment, the anode of the second input terminal IN2 connection storage capacitor C3, the anode of the storage capacitor C3 is simultaneously
The pwm signal output pin I/O of main control chip MCU is connected, and DC power supply VDD_1V8 is connected to by resistance R3.It will be with door
The output end OUT of U3 is connected to the grid of NMOS tube Q1, the source electrode ground connection of NMOS tube Q1, and drain electrode passes through in pull-up resistor R4 connection
Power supply VSYS is drawn, the effective reset signal MCU_RST of low level is exported by the drain electrode of NMOS tube Q1, is transmitted to DC voltage-stabilizing electricity
The enable end EN of road U2, the direct current regulation circuit U2 high level is enabled, stops enabling by control direct current regulation circuit U2, real
Existing circuit system power-off reset.
The working principle of reset circuit shown in Fig. 3 is: when main control chip MCU is operated normally, output pwm signal is to energy storage
Capacitor C3 carries out charge and discharge control, makes to remain low level state with the second input terminal IN2 of door U3.At this point, no matter charging
Whether there is or not charge power supply accesses on interface USB, export low level signal always with door U3, control NMOS tube Q1 keeps off state.
During this period, the enable end EN of direct current regulation circuit U2 is pulled to pull-up power supply VSYS, DC voltage-stabilizing electricity by pull-up resistor R4
The enabled operation of road U2, carries out DC converting to pull-up power supply VSYS, work needed for generating the circuit system in wearable device
Power supply, such as DC power supply VDD_1V8 are powered for circuit system, electricity operation in control system circuit.
When software anomaly occurs for wearable device, main control chip MCU no longer output pwm signal, on storage capacitor C3
Current potential rises rapidly, and makes and the current potential of the second input terminal IN2 of door U3 height.During main control chip MCU crashes, if user holds
Charging operations are gone, the current potential in the moment of charging interface USB access charge power supply VBUS, with the first input end IN1 of door U3
It is set to height, high level signal is exported with door U3, controls NMOS tube Q1 transient switching, drag down the enable end EN of direct current regulation circuit U2
Current potential, control direct current regulation circuit U2 is out of service in a short time, no longer provides it for the circuit system in wearable device
Required working power re-powers operation after making circuit system power-off reset, realizes that the reset of wearable device is restarted.
As in the first embodiment, can further connect bleeder circuit R1, R2, the first pincers in the first input end IN1 with door U3
Position diode D1 and filter capacitor C2, connect the second clamp diode D2 in the second input terminal IN2 with door U3, be used for
The input signal of door U3 carries out voltage clamping processing, plays the role of protection and door U3.Specific connection relationship is as in the first embodiment, can
Referring to the associated description in embodiment one.
The present invention is different from the reset of existing software test means, and it is direct control system down circuitry and extensive for resetting operation
It is multiple, can thoroughly solve main control chip MCU or operative sensor communication abnormality can not software rejuvenation the case where.Of the invention is another
A feature is: when wearable device occurs to crash abnormal, it is a kind of exception that user, which might not have found to find side by side, this and electricity
Sub- product phenomenon out of power is much like.When user charges wearable device access charge power supply, wearable device will
It automatically resets and can charge normal, without can just product be made to restore after must removing from charger as other products, greatly
The operability restored when improving no key product exception greatly, is suitably applied in any type configured with charging interface
Electronic product in.
Certainly, the above description is not a limitation of the present invention, and the present invention is also not limited to the example above, this technology neck
The variations, modifications, additions or substitutions that the those of ordinary skill in domain is made within the essential scope of the present invention, also should belong to this hair
Bright protection scope.
Claims (10)
1. a kind of reset circuit is applied in the electronic product with charging interface and main control chip, the main control chip operation
System program and the output pwm signal when operating normally；It is characterized in that, the reset circuit includes NAND gate, it is described with it is non-
The first input end of door connects the charging interface by capacitance, and the second input terminal connects the anode of storage capacitor, described
The pwm signal output pin of the anode connection main control chip of storage capacitor, and DC power supply is connected by resistance；The master control core
Piece adjusts the duty ratio of the pwm signal of its output, makes the anodic potentials of storage capacitor when pwm signal is normal lower than critical potential
V0, the critical potential V0 are less than the current potential of the DC power supply, and the low and high level of input signal is distinguished for the NAND gate
The separation of state, for the NAND gate by its output end output reset signal, the reset signal low level is effective.
2. reset circuit according to claim 1, which is characterized in that the NAND gate is the NAND gate of open-drain output, institute
The enable end of the direct current regulation circuit in the output end connection electronic product of NAND gate is stated, and connects pull-up circuit, the direct current
Voltage regulator circuit high level is enabled, working power needed for generating the circuit system in electronic product.
3. reset circuit according to claim 2, which is characterized in that the pull-up circuit includes pull-up resistor and pull-up electricity
The output end in source, the NAND gate connects the pull-up power supply by the pull-up resistor, and the pull-up power supply is electronic product
Power supply after dividing of battery supply or battery supply.
4. reset circuit according to claim 1, which is characterized in that the NAND gate is the NAND gate of non-open-drain output,
When the main control chip low level resets, the reset pin of the output end connection main control chip of the NAND gate；As the master
When controlling the reset of chip high level, the output end of the NAND gate passes through the reset pin that negater circuit connects main control chip.
5. reset circuit according to any one of claim 1 to 4, which is characterized in that the charging interface with it is described
It is also connected with bleeder circuit between the first input end of NAND gate, the charge power supply accessed by the charging interface is via described
After bleeder circuit partial pressure, it is transmitted to the first input end of the NAND gate.
6. reset circuit according to any one of claim 1 to 4, which is characterized in that it further include two clamp diodes,
The cathode of first clamp diode connects the first input end of the NAND gate, plus earth；The cathode of second clamp diode
The DC power supply is connected, anode connects the second input terminal of the NAND gate.
7. a kind of reset circuit is applied in the electronic product with charging interface and main control chip, the main control chip operation
System program and the output pwm signal when operating normally；It is characterized in that, the reset circuit includes and door and NMOS tube, institute
It states and the charging interface is connect by capacitance with the first input end of door, the second input terminal connects the anode of storage capacitor,
The pwm signal output pin of the anode connection main control chip of the storage capacitor, and DC power supply is connected by resistance；The master
Control chip adjusts the duty ratio of the pwm signal of its output, makes the anodic potentials of storage capacitor when pwm signal is normal lower than critical
Current potential V0, the critical potential V0 are less than the current potential of the DC power supply, and are the height electricity that input signal is distinguished with door
The separation of level state；The grid that NMOS tube is connect with the output end of door, the source electrode ground connection of NMOS tube, drain electrode connection pull-up
Circuit, by the drain electrode output reset signal of the NMOS tube, the reset signal low level is effective.
8. reset circuit according to claim 7, which is characterized in that in the drain electrode connection electronic product of the NMOS tube
The enable end of direct current regulation circuit, the direct current regulation circuit high level is enabled, generates needed for the circuit system in electronic product
Working power；The pull-up circuit includes pull-up resistor and pull-up power supply, and the drain electrode of the NMOS tube passes through the pull-up electricity
Resistance connects the pull-up power supply, and the pull-up power supply is the power supply of the battery supply or battery supply of electronic product after dividing.
9. reset circuit according to claim 7 or 8, which is characterized in that further include:
Bleeder circuit is connected to the charging interface and described between the first input end of door, to passing through the charging
After the charge power supply of mouth access is divided, it is transmitted to the first input end with door；
First clamp diode, the cathode connection first input end with door, plus earth；
Second clamp diode, cathode connect the DC power supply, anode connection second input terminal with door.
10. a kind of wearable device characterized by comprising
Such as reset circuit described in any one of claims 1 to 6；Alternatively,
Reset circuit as described in any one of claim 7 to 9.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811029710.1A CN109194317B (en) | 2018-09-05 | 2018-09-05 | Reset circuit and wearable equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811029710.1A CN109194317B (en) | 2018-09-05 | 2018-09-05 | Reset circuit and wearable equipment |
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| CN109194317A true CN109194317A (en) | 2019-01-11 |
| CN109194317B CN109194317B (en) | 2022-08-16 |
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| CN201811029710.1A Active CN109194317B (en) | 2018-09-05 | 2018-09-05 | Reset circuit and wearable equipment |
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| CN111766929A (en) * | 2020-06-12 | 2020-10-13 | 安徽华米信息科技有限公司 | Reset circuit, method, device and electronic product |
| CN112165246A (en) * | 2020-08-21 | 2021-01-01 | 苏州浪潮智能科技有限公司 | Power supply chip self-restarting device, method and system |
| CN112433890A (en) * | 2020-12-11 | 2021-03-02 | 南昌勤胜电子科技有限公司 | Reset circuit, chip and electronic product |
| CN112711318A (en) * | 2020-12-26 | 2021-04-27 | 广东湾区智能终端工业设计研究院有限公司 | Reset control circuit and method and terminal |
| CN114352137A (en) * | 2021-12-15 | 2022-04-15 | 无锡市弘智创汽车零部件有限公司 | Sliding door lock and working method thereof |
| CN115001467A (en) * | 2022-08-08 | 2022-09-02 | 南昌龙旗信息技术有限公司 | Charging trigger reset control circuit for system abnormal crash |
| CN116048226A (en) * | 2023-01-13 | 2023-05-02 | 中科亿海微电子科技（苏州）有限公司 | FPGA chip reset circuit, method and equipment |
| CN116509387A (en) * | 2022-05-19 | 2023-08-01 | 广东健奥科技有限公司 | Finger-clamping pulse oximeter and antistatic method thereof |
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| CN111766929A (en) * | 2020-06-12 | 2020-10-13 | 安徽华米信息科技有限公司 | Reset circuit, method, device and electronic product |
| CN112165246A (en) * | 2020-08-21 | 2021-01-01 | 苏州浪潮智能科技有限公司 | Power supply chip self-restarting device, method and system |
| CN112433890A (en) * | 2020-12-11 | 2021-03-02 | 南昌勤胜电子科技有限公司 | Reset circuit, chip and electronic product |
| CN112711318A (en) * | 2020-12-26 | 2021-04-27 | 广东湾区智能终端工业设计研究院有限公司 | Reset control circuit and method and terminal |
| CN114352137A (en) * | 2021-12-15 | 2022-04-15 | 无锡市弘智创汽车零部件有限公司 | Sliding door lock and working method thereof |
| CN116509387A (en) * | 2022-05-19 | 2023-08-01 | 广东健奥科技有限公司 | Finger-clamping pulse oximeter and antistatic method thereof |
| CN116509387B (en) * | 2022-05-19 | 2024-03-19 | 广东健奥科技有限公司 | Finger-clamping pulse oximeter and antistatic method thereof |
| CN115001467A (en) * | 2022-08-08 | 2022-09-02 | 南昌龙旗信息技术有限公司 | Charging trigger reset control circuit for system abnormal crash |
| CN116048226A (en) * | 2023-01-13 | 2023-05-02 | 中科亿海微电子科技（苏州）有限公司 | FPGA chip reset circuit, method and equipment |
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