CN108091697A - 薄膜晶体管及其制造方法 - Google Patents

薄膜晶体管及其制造方法 Download PDF

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CN108091697A
CN108091697A CN201711304674.0A CN201711304674A CN108091697A CN 108091697 A CN108091697 A CN 108091697A CN 201711304674 A CN201711304674 A CN 201711304674A CN 108091697 A CN108091697 A CN 108091697A
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layer
tft
film transistor
thin film
patterning
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张锡明
陈玉仙
黄彦余
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Chunghwa Picture Tubes Ltd
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Chunghwa Picture Tubes Ltd
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Priority to US15/894,931 priority patent/US20190181163A1/en
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Abstract

本发明提供一种薄膜晶体管及其制造方法，该薄膜晶体管包括通道层、源极、漏极、绝缘层和栅极。通道层设置于衬底上。源极和漏极分离设置于通道层上。绝缘层覆盖源极、漏极和通道层。栅极设置于绝缘层上，其中通道层的相对两侧壁分别与源极的远离漏极的侧壁和漏极的远离源极的侧壁切齐。本发明的薄膜晶体管可改善薄膜晶体管于制作过程中的对位精准度，以使薄膜晶体管具有良好的品质。

Description

薄膜晶体管及其制造方法
技术领域
本发明涉及一种薄膜晶体管及其制造方法，尤其涉及一种顶栅极薄膜晶体管及其制造方法。
背景技术
液晶显示技术发展至今已经相当成熟，各个面板公司的主要竞争越来越趋向于品质的提升和成本的下降。光刻是制造薄膜晶体管(thin film transistor,TFT)的必须环节，在进行曝光时为了实现各层之间的图形相对位置符合要求，通常在衬底的周边上制作对位标记(alignment mark)，以保证对位的精确度。
然而，对位标记与薄膜晶体管的栅极或是源极/漏极由同一图案化金属层所形成，故在后续进行薄膜晶体管的制造工艺中(例如热处理工艺)，对位标记易受到影响而导致其与薄膜晶体管的栅极或是源极/漏极的相对位置产生偏差，从而产生对位不良的问题。
因此，如何提升薄膜晶体管于制作过程中的对位精准度，以使薄膜晶体管具有良好的品质，实为目前研发人员亟待解决的议题之一。
发明内容
本发明提供一种薄膜晶体管及其制造方法，其可改善薄膜晶体管于制作过程中的对位精准度，以使薄膜晶体管具有良好的品质。
本发明的一实施例提供一种薄膜晶体管，其包括通道层、源极、漏极、绝缘层以及栅极。通道层设置于衬底上。源极和漏极分离设置于通道层上。绝缘层覆盖源极、漏极和通道层。栅极设置于绝缘层上，其中通道层的相对两侧壁分别与源极的远离漏极的侧壁和漏极的远离源极的侧壁切齐。
根据本发明的一实施例所述，薄膜晶体管还包括对位标记，其设置于衬底上且与通道层相互分离。
根据本发明的一实施例所述，对位标记包括导体层以及半导体层。半导体层设置于衬底和导体层之间。
根据本发明的一实施例所述，半导体层与通道层由同一图案化半导体层所形成。
根据本发明的一实施例所述，导体层与源极和漏极由同一图案化导体层所形成。
本发明的一实施例提供一种薄膜晶体管的制造方法，其包括以下步骤。在衬底上形成通道材料层。在通道材料层上覆盖导体材料层，以于衬底上形成叠层。移除部分叠层，以形成相互分离的对位标记和图案化叠层，其中图案化叠层包括通道层和形成于通道层上的导体层。图案化导体层，以形成相互分离的源极和漏极，其中源极和漏极暴露出部分通道层。在源极、漏极和通道层上覆盖绝缘层。在绝缘层上形成栅极。
根据本发明的一实施例所述，在通道材料层上覆盖导体材料层之前，对通道材料层进行退火(annealing)工艺。
根据本发明的一实施例所述，形成相互分离的对位标记和图案化叠层的方法包括以下步骤。在叠层上形成图案化光刻胶层，其中图案化光刻胶层暴露部分叠层。移除图案化光刻胶层所暴露的部分叠层，以形成对位标记和图案化叠层。
根据本发明的一实施例所述，图案化光刻胶层具有第一部分和第二部分，且第一部分的厚度大于第二部分的厚度，在图案化导体层之前，移除图案化光刻胶层的第二部分，以暴露出部分导体层。
根据本发明的一实施例所述，形成图案化光刻胶层的方法包括以下步骤。在叠层上形成光刻胶层，以半色调掩模(half tone mask,HTM)对光刻胶层进行曝光显影工艺，以形成具有第一部分和第二部分的图案化光刻胶层。
基于上述，在本发明上述实施例所提出的薄膜晶体管及其制造方法中，对位标记与图案化叠层是通过移除部分由通道材料层和导体材料层所构成的叠层而同时形成。如此一来，对位标记与图案化叠层中的通道层和导体层(后续可经另一图案化工艺形成相互分离的源极和漏极)并无对位偏移的问题，并且在对通道材料层或是导体材料层进行其他处理时，也不会影响到对位标记，故不会造成对位不良的问题，从而让薄膜晶体管具有良好的品质。
为让本发明的上述特征和优点能更明显易懂，下文特举实施例，并配合附图作详细说明如下。
附图说明
包含附图以便进一步理解本发明，且附图并入本说明书中并构成本说明书的一部分。附图说明本发明的实施例，并与描述一起用于解释本发明的原理；
图1、图2A、图2B、图3、图4、图5A、图5B、图6A、图6B、图7A和图7B为依照本发明一实施例的薄膜晶体管的制造方法的示意图。
附图标号说明：
100：衬底；
102：通道材料层；
104：经处理的通道材料层；
106：导体材料层；
108：叠层；
110、112：图案化光刻胶层；
110A：第一部分；
110B：第二部分；
114、120：导体层；
116：图案化叠层；
118：半导体层；
H：退火工艺；
AM：对位标记；
CH：通道层；
S：源极；
D：漏极；
GI：绝缘层；
G：栅极；
TFT：薄膜晶体管；
SL：源极线；
GL：栅极线；
PV：钝化层；
C：接触窗；
PE：像素电极。
具体实施方式
现将详细地参考本发明的示范性实施例，示范性实施例的实例说明于附图中。只要有可能，相同元件符号在附图和描述中用来表示相同或相似部分。
参照本实施例的附图以更全面地阐述本发明。然而，本发明也可以各种不同的形式体现，而不应限于本文中所述的实施例。附图中的层与区域的厚度会为了清楚起见而放大。相同或相似的参考号码表示相同或相似的元件，以下段落将不再一一赘述。
图1、图2A、图2B、图3、图4、图5A、图5B、图6A、图6B、图7A和图7B为依照本发明一实施例的薄膜晶体管的制造方法的示意图。图2A为图2B沿A-A'线的剖面示意图。图5A为图5B沿B-B’线的剖面示意图。图6A为图6B沿C-C’线的剖面示意图。图7A为图7B沿D-D’线的剖面示意图，为了清楚表示薄膜晶体管与像素电极之间的相对位置，图7B省略了钝化层。
请参照图1，在衬底100上形成通道材料层102。衬底100可以是玻璃衬底、石英衬底或有机聚合物衬底。通道材料层102的材料可以是半导体材料，例如非晶硅、微晶硅、单晶硅、有机半导体材料、氧化物半导体材料或其他适合的材料。通道材料层102可以通过旋转涂布(spin coating)、狭缝涂布(slit coating)、溅镀(sputtering)或其组合的方式形成于衬底100上。举例来说，可以通过狭缝涂布的方式将溶液金属氧化物半导体(solutionmetal oxide semiconductor,SMO)涂布于衬底100上，以于衬底100上形成通道材料层102。如此一来，由于溶液金属氧化物半导体是涂布于无图案的衬底100上，故可避免在图案的高低差处(例如图案的边角处)产生由溶液金属氧化物半导体的流动性所导致的膜厚不均的问题。
接着，可选择性地对通道材料层102进行退火工艺H，以改善通道材料层102的结晶性，使得在后续形成源极和漏极的图案化工艺中，通道层(经图案化通道材料层102形成)对湿蚀刻工艺所使用的蚀刻剂具有良好的耐受性(durability)。蚀刻剂例如是铝酸、PAN蚀刻液或其组合。在一些实施例中，PAN蚀刻液包括磷酸、硝酸和乙酸。在一些实施例中，退火工艺H的温度为400℃。应注意的是，退火工艺H的温度若不足则无法改善通道材料层102的结晶性。在一些实施例中，还可对选择性地对通道材料层102进行其他适合的工艺。
请同时参照图2A和图2B，在通道材料层102上覆盖导体材料层106，以于衬底100上形成叠层108。在本实施例中，导体材料层106是形成于经处理的通道材料层104上。导体材料层106的材料可以是金属、金属氧化物、金属氮化物、金属氮氧化物或其组合。举例来说，导体材料层106的材料可以是钼(Mo)、铝(Al)、钛(Ti)或其组合。在本实施例中，导体材料层106可通过溅镀的方式形成于经处理的通道材料层104上，但本发明不以此为限，在其他实施例中也可采用其他适合的方式来形成导体材料层106。
接着，在叠层108上形成图案化光刻胶层110，其中图案化光刻胶层110暴露出部分叠层108(即叠层108中的导体材料层106)。在本实施例中，可通过半色调掩模(HTM)对形成于叠层108上的光刻胶层(未示出)进行曝光显影工艺，使得所形成的图案化光刻胶层110具有第一部分110A和第二部分110B，且可暴露出导体材料层106。在一些实施例中，图案化光刻胶层110的第一部分110A除了覆盖于后续欲形成的对位标记、源极和漏极的位置上之外，其还覆盖于后续欲形成的源极线的位置上；而图案化光刻胶层110的第二部分110B则覆盖于后续欲形成的源极和漏极之间的位置处。在一些实施例中，第一部分110A的厚度大于第二部分110B的厚度。
请同时参照图2A和图3，移除部分叠层108，以形成相互分离的对位标记AM和图案化叠层116，其中图案化叠层116包括通道层CH和形成于其上的导体层114，而对位标记AM包括半导体层118和形成于其上的导体层120。在本实施例中，是以图案化光刻胶层110为掩模，移除图案化光刻胶层110所暴露的部分叠层108，以形成对位标记AM和图案化叠层116。也就是说，通过同一掩模(即图案化光刻胶层110)来移除其所暴露的部分叠层108，可使得所形成的对位标记AM与图案化叠层116无对位偏移的问题。如此一来，可解决对位标记与栅极同时形成的情况下，对位标记易受到后续的制造工艺影响(例如对形成于栅极上的通道层进行热处理工艺)而产生对位不良的问题。换句话说，即便对通道材料层102或是导体材料层106进行其他额外的处理，也不会影响到后续形成的对位标记AM，故薄膜晶体管具有较佳的工艺裕度(process window)。在一些实施例中，移除部分叠层108的方法可以是以PAN为蚀刻液，通过湿蚀刻的方式移除图案化光刻胶层110所暴露的导体材料层106，以暴露出位于其下的通道材料层102。接着，以湿蚀刻或是干蚀刻的方式移除上述所暴露的通道材料层102，以形成相互分离的对位标记AM和图案化叠层116。在一些实施例中，可采用含有盐酸的蚀刻液，以湿蚀刻的方式移除上述所暴露的通道材料层102。在另一些实施例中，也可采用含有三氯化硼(BCl3)的气体，以干蚀刻的方式移除上述所暴露的通道材料层102。在一些实施例中，对位标记AM的半导体层118与图案化叠层116的通道层CH由同一图案化半导体层所形成。在一些实施例中，对位标记AM的导体层120与图案化叠层116的导体层114(后续可经另一图案化工艺形成相互分离的源极和漏极)由同一图案化导体层所形成。
请同时参照图3和图4，移除图案化光刻胶层110的第二部分110B，以暴露出部分导体层114。在一些实施例中，由于第一部分110A的厚度大于第二部分110B的厚度，因此，可同时对图案化光刻胶层110的第一部分110A和第二部分110B进行灰化(ashing)工艺，以移除第二部分110B并同时薄化第一部分110A。如此一来，薄化后的第一部分110A构成了暴露出部分导体层114的图案化光刻胶层112。如此一来，不须通过另一图案化工艺来制作用于形成源极和漏极的掩模，故不会产生对位不良的问题。
请同时参照图4、图5A和图5B，以图案化光刻胶层112为掩模，移除图案化光刻胶层112所暴露的导体层114，以形成相互分离的源极S、漏极D和与源极S连接的源极线SL，并暴露出通道层CH。如此一来，由于图案化光刻胶层112的图案与图案化光刻胶层110的图案大致相似，其差异只在于图案化光刻胶层112移除了图案化光刻胶层110的第二部分110B。也就是说，图案化光刻胶层110的第一部分110A的图案与图案化光刻胶层112的图案相同(两者差异仅在于厚度不同)，因此，以图案化光刻胶层112为掩模来形成相互分离的源极S和漏极D时，通道层CH的相对两侧壁S1、S2会分别与源极S的远离漏极D的侧壁S3和漏极D的远离源极S的侧壁S4切齐。
接着，在移除图案化光刻胶层112所暴露的导体层114之后(即图案化导体层114之后)，可通过灰化工艺移除图案化光刻胶层112。在一些实施例中，源极S和漏极D所暴露的通道层CH位于两者之间。在一些实施例中，对位标记AM的导体层120与源极S和漏极D由同一图案化导体层所形成。在一些实施例中，源极S与源极线SL由同一图案化导体层所形成。
请同时参照图6A和图6B，在源极S、漏极D和通道层CH上覆盖绝缘层GI。在一些实施例中，绝缘层GI还覆盖于衬底100和对位标记AM上。绝缘层GI的材料可以是无机介电材料、有机介电材料或其组合。举例来说，无机材料可以是氧化硅、氮化硅、氮氧化硅或其组合；有机材料可以是聚酰亚胺系树脂、环氧系树脂或压克力系树脂等高分子材料。绝缘层GI的形成方法可以是化学气相沉积法、旋转涂布法或其组合。
接着，在绝缘层GI上形成栅极G和与栅极G连接的栅极线GL，其中栅极G、绝缘层GI、源极S、漏极D和通道层CH构成了薄膜晶体管TFT。栅极G的材料可以是导电材料，例如金属、金属氧化物、金属氮化物、金属氮氧化物或其组合。举例来说，栅极G可以是钼(Mo)、铝(Al)、钛(Ti)或其组合。在一些实施例中，形成栅极G和栅极线GL的方法可以是通过溅镀的方式于绝缘层GI上形成导体层(未示出)，接着再图案化上述的导体层，以形成栅极G和栅极线GL。在一些实施例中，栅极G和栅极线GL由同一图案化导体层所形成。
请同时参照图7A和图7B，在绝缘层GI上形成钝化层PV。钝化层PV的材料可以是无机绝缘材料，例如氧化硅、氮化硅、氮氧化硅或其组合。钝化层的形成方法可以是化学气相沉积法、原子层化学气相沉积或其组合。接着，在钝化层PV和绝缘层GI中形成暴露漏极D的接触窗开口(对应接触窗C的位置)，并于其中填入导体材料，以形成接触窗C。接触窗C的材料可以是导电材料，例如金属、金属氧化物、金属氮化物、金属氮氧化物或其组合。在一些实施例中，形成接触窗开口的方法可以是采用含有四氟化碳(CF4)和氧气(O2)的气体进行干式蚀刻。之后，在钝化层PV上形成与接触窗C连接的像素电极PE。在一些实施例中，像素电极PE与接触窗C由同一图案化导体层所形成。
以下，将通过图6A及图6B来说明本实施例的薄膜晶体管TFT。此外，本实施例的薄膜晶体管虽然是以上述制造方法为例进行说明，但并不以此为限。
请同时参照图6A和图6B，薄膜晶体管TFT包括通道层CH、源极S、漏极D、绝缘层GI以及栅极G。通道层CH设置于衬底110上。源极S和漏极D分离设置于通道层CH上。绝缘层GI覆盖源极S、漏极D和通道层CH。栅极G设置于绝缘层GI上，其中通道层CH的相对两侧壁S1、S2分别与源极S的远离漏极D的侧壁S3和漏极D的远离源极S的侧壁S4切齐。在一些实施例中，对位标记AM设置于衬底100上且与薄膜晶体管TFT相互分离，并且对位标记AM包括半导体层118和导体层120，其中半导体层118设置于衬底100和导体层120之间。在一些实施例中，半导体层118与通道层CH由同一图案化半导体层所形成。在一些实施例中，导体层118与源极S和漏极D由同一图案化导体层所形成。
综上所述，上述实施例所述的薄膜晶体管及其制造方法中，对位标记与图案化叠层是通过移除部分由通道材料层和导体材料层所构成的叠层而同时形成。如此一来，对位标记与图案化叠层中的通道层和导体层(后续可经另一图案化工艺形成相互分离的源极和漏极)并无对位偏移的问题，并且在对通道材料层或是导体材料层进行其他处理时，也不会影响到对位标记，故不会造成对位不良的问题，从而让薄膜晶体管具有良好的品质。
最后应说明的是：以上各实施例仅用以说明本发明的技术方案，而非对其限制；尽管参照前述各实施例对本发明进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例技术方案的范围。

Claims (10)

1.一种薄膜晶体管，其特征在于，包括：
通道层，设置于衬底上；
源极和漏极，分离设置于所述通道层上；
绝缘层，覆盖所述源极、所述漏极和所述通道层；以及
栅极，设置于所述绝缘层上，
其中所述通道层的相对两侧壁分别与所述源极的远离所述漏极的侧壁和所述漏极的远离所述源极的侧壁切齐。
2.根据权利要求1所述的薄膜晶体管，还包括：
对位标记，设置于所述衬底上且与所述通道层相互分离。
3.根据权利要求2所述的薄膜晶体管，其中所述对位标记包括：
导体层；以及
半导体层，设置于所述衬底和所述导体层之间。
4.根据权利要求3所述的薄膜晶体管，其中所述半导体层与所述通道层由同一图案化半导体层所形成。
5.根据权利要求4所述的薄膜晶体管，其中所述导体层与所述源极和所述漏极由同一图案化导体层所形成。
6.一种薄膜晶体管的制造方法，其特征在于，包括：
在衬底上形成通道材料层；
在所述通道材料层上覆盖导体材料层，以于所述衬底上形成叠层；
移除部分所述叠层，以形成相互分离的对位标记和图案化叠层，其中所述图案化叠层包括通道层和形成于所述通道层上的导体层；
图案化所述导体层，以形成相互分离的源极和漏极，其中所述源极和所述漏极暴露出部分所述通道层；
在所述源极、所述漏极和所述通道层上覆盖绝缘层；以及
在所述绝缘层上形成栅极。
7.根据权利要求6所述的薄膜晶体管的制造方法，还包括：
在所述通道材料层上覆盖所述导体材料层之前，对所述通道材料层进行退火工艺。
8.根据权利要求6所述的薄膜晶体管的制造方法，其中形成相互分离的所述对位标记和所述图案化叠层的方法包括：
在所述叠层上形成图案化光刻胶层，其中所述图案化光刻胶层暴露部分所述叠层；以及
移除所述图案化光刻胶层所暴露的部分所述叠层，以形成所述对位标记和所述图案化叠层。
9.根据权利要求8所述的薄膜晶体管的制造方法，其中所述图案化光刻胶层具有第一部分和第二部分，且所述第一部分的厚度大于所述第二部分的厚度，在图案化所述导体层之前，移除所述图案化光刻胶层的所述第二部分，以暴露出部分所述导体层。
10.根据权利要求9所述的薄膜晶体管的制造方法，其中形成所述图案化光刻胶层的方法包括：
在所述叠层上形成光刻胶层，以半色调掩模对所述光刻胶层进行曝光显影工艺，以形成具有所述第一部分和所述第二部分的图案化光刻胶层。
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