CN108090015B - High-speed serial port communication method for heterogeneous interconnection of multiple types of interfaces - Google Patents
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Abstract
The invention belongs to the technical field of asynchronous serial communication, and discloses a high-speed serial port communication method for heterogeneous interconnection of multiple types of interfaces, which is characterized in that a sending unit and a receiving unit are realized in an FPGA (field programmable gate array), wherein the sending unit comprises a sending shift register, a sending data buffer area, a local gating switch, a channel state register and a channel number register, and the receiving unit comprises a receiving gating switch, a sampling clock counter, a receiving shift register and a receiving data buffer area; compared with Ethernet, PCI Express and RAPIDIO protocols, the method CAN effectively reduce the complexity of control information in the information transmission process, and has flexibility and higher transmission rate compared with RS-422, RS-422 and CAN.
Description
Technical Field
The invention belongs to the technical field of asynchronous serial communication, and particularly relates to a high-speed serial communication method for heterogeneous interconnection of multiple types of interfaces, which is suitable for serial communication with higher requirements on data rate, reliability and flexibility.
Background
With the improvement of the complexity of an embedded system, the reliability and the transmission efficiency of a multi-type interface heterogeneous interconnection system become more and more important; in the heterogeneous interconnection process of the multi-type interfaces, the information exchange adopts an asynchronous differential serial communication mode, and the realization methods of the mode generally comprise two modes, one mode is to realize asynchronous serial communication through FPGA internal logic, and the other mode is to adopt an external serial communication chip; although the programming of the external serial communication chip is relatively simple, the hardware cost and the design cost are increased, so that the communication mode of realizing the asynchronous serial port by adopting the internal logic of the FPGA is more widely applied.
In an embedded system, a plurality of asynchronous Serial data transmission methods are provided, high-speed Serial standards such as Ethernet, high-speed peripheral component interconnect standard extension (PCI Express) and high-speed Serial input/output interface (Serial RAPIDIO) are used on the basis of a Serial deserializing technology, although the data transmission rate is high, the consumption resources are more, the protocol is complex and the transmission efficiency is low; although the low-rate standards such as RS-422, CAN and the like have simple protocols, long transmission distances and convenient networking, the communication rate is low, the flexibility of multipoint communication is limited, and no better data flow control measures exist, so that the method is mostly applied to industrial control occasions.
At present, the asynchronous serial communication interface is mainly realized in a single-ended mode and a differential mode. Low Voltage Differential Signaling (LVDS), a low voltage swing differential signaling technique, has the advantages of high data transmission rate, low power, and strong noise suppression, and thus becomes the most commonly used structure in high-speed asynchronous serial communication.
Disclosure of Invention
Aiming at the defects or shortcomings in the prior art, the invention aims to provide a high-speed serial port communication method for multi-type interface heterogeneous interconnection, which has the advantages of easiness in design, low power consumption, high efficiency, high reliability and high flexibility and provides an effective solution for embedded system heterogeneous interconnection.
A high-speed serial port communication method for heterogeneous interconnection of multiple types of interfaces realizes a sending unit and a receiving unit in an FPGA, wherein the sending unit comprises a sending shift register, a sending data buffer area, a local gating switch, a channel state register and a channel number register, the receiving unit comprises a receiving gating switch, a sampling clock counter, a receiving shift register and a receiving data buffer area, the communication method comprises a sending part and a receiving part, and the specific process is as follows:
(1) a transmission section:
step 1.1, determining that a sender comprises N channels, and selecting a local sending channel from a plurality of receiving data channels appointed by a receiver, wherein the local sending channel is one of the plurality of receiving data channels appointed by the receiver; the number of the local sending channel is a local channel number, and then a channel corresponding to the local channel number is gated by using a local gating switch according to the sending channel number;
step 1.2, determining data to be sent and a local channel state, wherein the local channel state indicates that a receiver informs a sender of an optional channel which can be used for sending the data; then respectively writing the local channel state, the local channel number and the data to be sent into a corresponding channel state register, a channel number register and a sending data buffer area;
step 1.3, carrying out protocol encapsulation on data to be sent in a data sending buffer area, and recording the encapsulated data to be sent as a protocol frame;
step 1.4, writing the protocol frame into a sending shift register in sequence according to bytes, and then sending the highest-order data in the sending shift register while shifting to the right;
(2) a receiving section:
step 2.1, the receiving party receives data with high and low level changes and records the data as serial data; performing clock calibration on the serial data to obtain serial data after clock calibration;
step 2.2, writing the serial data after clock calibration into a receiving shift register as a register value, and then outputting the register value in the receiving shift register in parallel to be recorded as parallel data output by the receiving shift register;
step 2.3, analyzing the parallel data output by the receiving shift register to respectively obtain a sender channel number, a sender channel state and data to be received, and writing the data to be received into a receiving data buffer area;
step 2.4, switching the receiving gating switch to a corresponding channel according to the sender channel number registered in the sender channel number register, recording as a channel M, and simultaneously reading out information in the sender channel state register through the channel M; the channel M is one of N channels of the receiving party;
and 2.5, switching the receiving gating switch to a corresponding channel M according to the channel number M registered in the channel number register of the sending party, and then sending the data to be received in the received data buffer area out through the channel M.
The invention has the beneficial effects that:
compared with Ethernet, PCI Express and RAPIDIO protocols, the method can effectively reduce the complexity of control information in the information transmission process; compared with protocols such as RS-422, CAN and the like, the method has higher flexibility and higher transmission rate; in addition, the method of the invention adopts efficient and flexible protocol encapsulation, which not only can improve the resource utilization rate of the FPGA, but also is beneficial to enhancing the reliability and flexibility of data transmission.
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The present invention will be described in further detail with reference to the accompanying drawings and specific embodiments.
FIG. 1 is a schematic block diagram of a high-speed serial communication method for heterogeneous interconnection of multiple types of interfaces;
FIG. 2 is a block diagram of a frame format without data segments;
FIG. 3 is a block diagram of a data segment frame format;
FIG. 4 is a schematic diagram of sampling of the sampling clock counter Sample _ Cnt when the received data is not shifted;
FIG. 5 shows the received data being shifted by an amount less than N1A sampling schematic diagram of a sampling clock counter Sample _ Cnt at +1 system clocks;
FIG. 6 is a drawing showingThe received data is shifted by more than N1A sampling schematic diagram of the sampling clock counter Sample Cnt at +1 system clocks.
Detailed Description
Referring to fig. 1, a schematic block diagram of a high-speed serial communication method for heterogeneous interconnection of multiple types of interfaces is shown; the high-speed serial port communication method for multi-type interface heterogeneous interconnection is characterized in that the communication method comprises a sending part and a receiving part, and the specific process is as follows:
(1) a transmission section:
step 1.1, determining that a sender comprises N channels, and selecting a local sending channel from a plurality of receiving data channels appointed by a receiver, wherein the local sending channel is one of the plurality of receiving data channels appointed by the receiver; the number of the local sending channel is the local channel number, and then the channel corresponding to the local channel number is gated by using the local gating switch according to the sending channel number.
Step 1.2, determining data to be sent and a local channel state, wherein the local channel state refers to channels from which a sender can send data to a receiver, namely the receiver informs the sender of optional channels which can be used for sending the data to be sent; and then respectively writing the local channel state, the local channel number and the data to be sent into a corresponding channel state register, a channel number register and a sending data buffer area, and then carrying out next protocol frame encapsulation.
Step 1.3, encapsulating the protocol frame; in the transmission process, as long as the physical lines of the two communication parties of the sender and the receiver are communicated, data always exist on the two-way data link TX and the two-way data link RX for transmission, wherein TX represents a data link of the sender, and RX represents a data link of the receiver; and carrying out protocol encapsulation on the data to be sent in the data sending buffer area, and recording the encapsulated data to be sent as a protocol frame.
Specifically, in the sending process, a channel is obtained from the received state of the receiving channel of the other party, data to be sent is written into a corresponding sending data buffer area through the channel, then the data to be sent in the sending data buffer area is encapsulated in the format of fig. 2 or fig. 3 according to the frame format, and the encapsulated data to be sent is recorded as a protocol frame.
If the sending data buffer does not have data to be transmitted, the protocol frame omits a data segment, and sets the local channel number to be a default value of 0, and at this time, it is set that a data link of the sending party transmits a frame format without the data segment, where the frame format without the data segment includes a frame header 7E, a frame tail 7F, a local channel number, and a local receiving channel state, as shown in fig. 2; if the sending buffer has data to be transmitted, the frame format is as shown in fig. 3, and at this time, the frame format of the data segment transmitted on the data link of the sending party is set to include a frame header 7E, a frame trailer 7F, a local channel number, a local receiving channel state and a data segment, where the data segment is the data to be transmitted in the sending data buffer.
And step 1.4, sequentially writing the protocol frames into the transmission shift register according to bytes, and then transmitting the highest-order data of the transmission shift register while shifting to the right.
Specifically, the sending shift register is determined to be an 8-bit register, the 7 th bit is determined to be the highest bit, and the 0 th bit is determined to be the lowest bit, and the protocol frames are written into the sending shift register in sequence according to bytes; if the sending shift register receives data of one byte, a corresponding shift counter is started immediately, and the initial value of the shift counter is set to be 0; when the Shift counter Shift _ cnt counts to 7, the Shift counter Shift _ cnt is cleared, the highest bit of the transmission Shift register is output to the serial transmission end, the data with the number of 0 in the transmission Shift register to the data with the number of 6 are respectively shifted to the right by one bit, and the data with the number of 0 after being shifted to the right by one bit is subjected to 0 supplementing processing.
Traversing all bytes in the protocol frame until all data bits of the transmission shift register are output in series; wherein, the data bit is the bit data stored in the corresponding transmission shift register; thus, the highest data in the transmission shift register is transmitted while shifting to the right.
(2) A receiving section:
step 2.1, the receiving party receives data with high and low level changes and records the data as serial data; recording the received data as serial data; and performing clock calibration on the serial data to obtain the serial data after clock calibration.
Specifically, serial data calibration is mainly used to solve the problems of serial data offset and jitter during the receiving process; performing clock calibration on the serial data to obtain serial data after clock calibration, wherein the process is as follows:
in the receiving process, firstly setting the frequency of a system clock to be 8 times of the serial data rate, then sampling the serial data by using the system clock, finally carrying out XOR operation on the data obtained by sampling in the front and the back system clocks, if the result of the XOR operation is equal to 1, determining that the serial data on a data link of a receiving party is turned from high to low or from low to high, and setting a value N at the moment1Assigning the value to a sampling clock counter Sample _ Cnt, and starting to perform self-decreasing operation on the sampling clock counter Sample _ Cnt, wherein the self-decreasing operation is performed by 1 every time; if the result of the XOR operation is not equal to 1, then the value N is set2Assigning to a sampling clock counter Sample _ Cnt to perform self-decreasing operation, wherein the self-decreasing operation is 1 every time; the system clock is a clock provided for the FPGA by an FPGA external device.
When passing through N1The serial data received by a system clock receiver is stable, and when a sampling clock counter is reduced to 0, the received serial data is sampled for one time; if the serial data corresponding to the time when the Sample clock counter Sample _ Cnt is reduced to 0 from zero is not inverted, 7 is assigned to the Sample clock counter Sample _ Cnt, and the self-reduction is restarted, and is reduced by 1 each time.
And taking the serial data corresponding to the sampling clock counter when the sampling clock counter is reduced to 0 as the serial data after clock calibration.
Since the frequency of the system clock is 8 times the serial data rate, the sampling clock counter Sample _ Cnt is generally selected to be 2-6Sampling is carried out; to ensure that the calibrated compression offset and the expansion offset are as consistent as possible; set value N in the present embodiment1Get 2, set value N2And 8, taking the sum.
In the receiving process, the receiving part receives the serial data for a time duration greater than or less than N2The system clock indicates that the serial data received by the receiver has an offset; otherwise no offset occurs.
When the serial data received by the receiving side is not shifted, the sampling clock counter Sample _ Cnt is a continuous cycle self-decrement number and samples the serial data only once, as shown in fig. 4.
When the serial data received by the receiver is offset and the offset is less than N1At +1 system clocks, the sampling clock counter Sample _ Cnt count value will be discontinuous, but still Sample the serial data only once, as shown in fig. 5.
When the received data is deviated and the deviation is larger than N1At +1 system clocks, not only will the sampling clock counter Sample _ Cnt count value be intermittent, but also the sampling number of serial data will not be 1, as shown in fig. 6; wherein N is1Is a fixed value, N2Is the ratio of the system clock to the serial data rate.
And 2.2, writing the serial data after clock calibration into the receiving shift register as a register value, and outputting the register value in the receiving shift register in parallel to be recorded as parallel data output by the receiving shift register.
Specifically, after serial data after clock calibration is obtained, sampling is firstly carried out to obtain sampling data, then the sampling data are stored to the 0 th bit of the receiving shift register, and then the 0 th bit to the 6 th bit of the receiving shift register are respectively shifted to the right by one bit; and when one byte of sampling data received by the receiving shift register is full, the sampling data is used as a register value, and the register value in the receiving shift register is parallelly output to the next stage for protocol analysis.
And 2.3, analyzing the parallel data output by the receiving shift register to respectively obtain a sender channel number, a sender channel state and data to be received, and writing the data to be received into a received data buffer area.
Specifically, receiving and analyzing register values in a receiving shift register and outputting the register values in parallel; firstly, capturing a frame header, if the byte in the parallel output receiving shift register is the frame header 7E, sending the 1 st byte received later as a sending party channel number into a sending party channel number register, and sending the 2 nd byte received later as a sending party channel state into a sending party channel state register.
If the 3 rd byte received after the frame header 7E is the frame tail 7F, the protocol frame is ended, and the protocol frame has no data to be received; if the 3 rd byte received after the frame header is not the frame trailer 7F, then the 3 rd byte will be written as data to be received into the received data buffer to be read.
Step 2.4, obtaining the state information of the sender channel: switching the receiving gating switch to a corresponding channel according to the sender channel number registered in the sender channel number register, marking as a channel M, and simultaneously reading information in the sender channel state register through the channel M; channel M is one of the N channels of the receiver.
Step 2.5, acquiring data sent by a sender: and switching the receiving gating switch to the corresponding channel M according to the channel number M registered in the channel number register of the sending party, and then sending out the data to be received in the received data buffer area through the channel M.
Claims (5)
1. A high-speed serial port communication method for heterogeneous interconnection of multiple types of interfaces realizes a sending unit and a receiving unit in an FPGA, wherein the sending unit comprises a sending shift register, a sending data buffer area, a local gating switch, a channel state register and a channel number register, and the receiving unit comprises a receiving gating switch, a sampling clock counter, a receiving shift register and a receiving data buffer area, and is characterized in that the communication method comprises a sending part and a receiving part, and the specific process is as follows:
(1) a transmission section:
step 1.1, determining that a sender comprises N channels, and selecting a local sending channel from a plurality of receiving data channels appointed by a receiver, wherein the local sending channel is one of the plurality of receiving data channels appointed by the receiver; the number of the local sending channel is a local channel number, and then a channel corresponding to the local channel number is gated by using a local gating switch according to the local channel number;
step 1.2, determining data to be sent and a local channel state, wherein the local channel state indicates that a receiver informs a sender of an optional channel which can be used for sending the data; then respectively writing the local channel state, the local channel number and the data to be sent into a corresponding channel state register, a channel number register and a sending data buffer area;
step 1.3, carrying out protocol encapsulation on data to be sent in a data sending buffer area, and recording the encapsulated data to be sent as a protocol frame;
in step 1.3, the protocol frame is obtained by the following process:
in the sending process, a channel is obtained from the received state of the receiving channel of the other side, data to be sent is written into a corresponding sending data buffer area through the channel, then the data to be sent in the sending data buffer area is packaged according to a frame format, and the packaged data to be sent is recorded as a protocol frame;
if the sending data buffer zone does not have data to be transmitted, the protocol frame omits a data segment, and the number of a local channel is set as a default value 0, and at the moment, a data-segment-free frame format is set to be transmitted on a data link of a sending party, wherein the data-segment-free frame format comprises a frame head, a frame tail, a local channel number and a local receiving channel state; if the sending buffer area has data to be sent, setting a frame format of a data segment transmitted on a data link of a sending party at the moment, wherein the frame format of the data segment comprises a frame head, a frame tail, a local channel number, a local receiving channel state and a data segment, and the data segment is the data to be sent in the sending data buffer area;
packaging the process (1), and recording the packaged data as a protocol frame;
step 1.4, writing the protocol frame into a sending shift register in sequence according to bytes, and then sending the highest-order data in the sending shift register while shifting to the right;
the process of step 1.4 is:
(1.4.1) determining that the sending shift register is a Q-bit register, determining that a Q-1 bit is a highest bit and a 0 th bit is a lowest bit, and sequentially writing the protocol frames into the sending shift register according to bytes; if the sending shift register receives data of one byte, a corresponding shift counter is started to count immediately, and the initial value of the shift counter is set to be 0; when the shift counter counts to Q-1, the shift counter is cleared, the highest bit of the transmission shift register is output to the serial transmission end, the data with the number of 0 in the transmission shift register to the data with the number of Q-2 are respectively shifted to the right, and the data bit with the number of 0 after being shifted to the right is subjected to 0 supplementing processing;
(1.4.2) traversing all bytes in the protocol frame until all data bits of the transmission shift register are output in series, and transmitting the highest-order data in the transmission shift register while shifting to the right;
(2) a receiving section:
step 2.1, the receiving party receives data with high and low level changes and records the data as serial data; performing clock calibration on the serial data to obtain serial data after clock calibration;
step 2.2, writing the serial data after clock calibration into a receiving shift register as a register value, and then outputting the register value in the receiving shift register in parallel to be recorded as parallel data output by the receiving shift register;
step 2.3, analyzing the parallel data output by the receiving shift register to respectively obtain a sender channel number, a sender channel state and data to be received, and writing the data to be received into a receiving data buffer area;
step 2.4, switching the receiving gating switch to a corresponding channel according to the sender channel number registered in the sender channel number register, recording as a channel M, and simultaneously reading out information in the sender channel state register through the channel M; the channel M is one of N channels of the receiving party;
and 2.5, switching the receiving gating switch to a corresponding channel M according to the channel number M registered in the channel number register of the sending party, and then sending the data to be received in the received data buffer area out through the channel M.
2. The method according to claim 1, wherein in step 2.1, the clock-calibrated serial data is obtained by:
in the receiving process, firstly setting the frequency of a system clock to be P times of the rate of serial data, then sampling the serial data by using the system clock, finally carrying out XOR operation on the data obtained by sampling in the front and the back system clocks, if the result of the XOR operation is equal to 1, determining that the serial data on a data link of a receiving party is turned from high to low or from low to high, and setting a value N at the moment1Assigning the value to a sampling clock counter, and starting to perform self-decreasing operation on the sampling clock counter, wherein the self-decreasing operation is performed by 1 every time; if the result of the XOR operation is not equal to 1, then the value N is set2Assigning a value to a sampling clock counter to perform self-decreasing operation, wherein the self-decreasing operation is performed by 1 every time; the system clock is a clock provided for the FPGA by an FPGA external device;
when passing through N1The serial data received by the system clock receiver is stable, and when the sampling clock counter is reduced to 0, the received serial data is sampled for one time; if the corresponding serial data is not inverted when the sampling clock counter is reduced to 0, N is added2Assigning a value to a sampling clock counter, restarting self-decreasing, and self-decreasing by 1 each time; n is a radical of2Is a positive integer greater than 0;
taking the serial data corresponding to the sampling clock counter when the sampling clock counter is reduced to 0 as the serial data after clock calibration; wherein P is a positive integer greater than 0.
3. The method according to claim 2, wherein in step 2.1, the serial data further comprises:
receiving serial data for a duration greater than or less than N2The clock of the system is used for synchronizing the system clock,the serial data received by the receiving part is deviated; otherwise, no offset occurs;
when the serial data received by the receiver is not deviated, the sampling clock counter is a continuous cycle self-decrement number and only samples the serial data once;
when the serial data received by the receiver is offset and the offset is less than N1When +1 system clocks, the count value of the sampling clock counter will be interrupted, but at this time, serial data is still sampled only once;
when the received data is deviated and the deviation is larger than N1When +1 system clocks, the counting value of the sampling clock counter is discontinuous, and the sampling frequency of the serial data is 1; wherein N is1And N2Respectively positive integers greater than 0.
4. The high-speed serial port communication method for multi-type interface heterogeneous interconnection according to claim 1, wherein the specific process of step 2.2 is as follows:
after serial data after clock calibration is obtained, sampling is firstly carried out to obtain sampling data, then the sampling data are stored to the 0 th bit of the receiving shift register, and the 0 th bit to the Q-2 th bit of the receiving shift register are respectively shifted to the right by one bit; when one byte of sampling data received by the receiving shift register is full, the sampling data is used as a register value, and the register value in the receiving shift register is output in parallel; wherein Q is a set integer.
5. The high-speed serial port communication method for multi-type interface heterogeneous interconnection according to claim 1, wherein the specific process of step 2.3 is as follows:
firstly, capturing a frame header, if the byte in the parallel output receiving shift register is the frame header, sending the 1 st byte received later as a sender channel number into a sender channel number register, and sending the 2 nd byte received later as a sender channel state into a sender channel state register;
if the 3 rd byte received after the frame head is the frame tail, the protocol frame is ended, and the protocol frame has no data to be received; if the 3 rd byte received after the frame header is not the frame end, the 3 rd byte will be written as the data to be received into the received data buffer to be read.
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| CN112769427B (en) * | 2021-04-07 | 2021-10-08 | 北京中科芯蕊科技有限公司 | Self-clocking asynchronous system |
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