CN108089157A - A kind of multi-channel digital control delayer - Google Patents
A kind of multi-channel digital control delayer Download PDFInfo
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- CN108089157A CN108089157A CN201711309630.7A CN201711309630A CN108089157A CN 108089157 A CN108089157 A CN 108089157A CN 201711309630 A CN201711309630 A CN 201711309630A CN 108089157 A CN108089157 A CN 108089157A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
- G01S7/02—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S13/00
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- Radar, Positioning & Navigation (AREA)
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Abstract
The invention discloses a kind of multi-channel digital control delayer, including：For carrying out the numerical control delay component of delay process to signal；For the power supply being powered to multi-channel digital control delayer；For controlling the control chip of multi-channel digital control delayer；Numerical control delay component includes, the first amplifier, time-delay mechanism, numerical-control attenuator, the second amplifier, RF switch；Time-delay mechanism includes four delay units, and the multistage delay of progress is mutually combined by four delay units.A kind of multi-channel digital control delayer of the present invention, using carrying out corner cut treated microstrip line as delay component, multistage delay is realized by multiple delay units, disclosure satisfy that radar work when input/output standing-wave ratio, the performance requirement of dynamic range, in signal frequency in 3~5.5GHz, the maximum delay mean square error of multi-channel digital control delayer is 0.1052ns, radar system is greatly reduced in the position beam space dispersion of off-center frequency point in use, improves the overall performance of radar.
Description
Technical field
Technical field more particularly to a kind of multi-channel digital control delayer the present invention relates to digitally programmable delayer.
Background technology
During radar scanning is carried out, in order to meet the actual demand of wideband wide scan, it is necessary to using phase shifter pair
Wave beam is scanned, and in traditional radar system, beam scanning is carried out using phase shifter only in array element grade, and phase shifter can not
The position wave beam in off-center frequency point is solved the problem of there are spatial dispersion, and big mouth can not also be solved by phase shifter
Existing for the array antenna of footpath the problem of aperture fill time.
Therefore, the prior art has yet to be improved and developed.
The content of the invention
In view of above-mentioned deficiencies of the prior art, it is an object of the invention to provide a kind of multi-channel digital control delayers, it is intended to
Radar system of the prior art is solved in the position of off-center frequency point, there are holes there are spatial dispersion, array antenna for wave beam
The problem of footpath transition time.
To achieve the above object, specific technical solution is as follows by the present invention：
A kind of multi-channel digital control delayer, wherein, multi-channel digital control delayer includes：
For carrying out the numerical control delay component of delay process to signal；
For the power supply being powered to multi-channel digital control delayer；
For controlling the control chip of multi-channel digital control delayer；
The numerical control delay component includes, the first amplifier, time-delay mechanism, numerical-control attenuator, the second amplifier, RF switch；
Input terminal passes sequentially through the first amplifier, time-delay mechanism, numerical-control attenuator, the second amplifier, RF switch and output terminal
It is connected；
Comprising four delay units in the time-delay mechanism, the multistage delay of progress is mutually combined by four delay units.
The multi-channel digital control delayer, wherein, the control chip is opened with time-delay mechanism, numerical-control attenuator, radio frequency
Pass is connected.
The multi-channel digital control delayer, wherein, the time-delay mechanism specifically includes：First delay unit, second prolongs
Shi Danyuan, balanced device, the 3rd amplifier, the 3rd delay unit, the 4th delay unit；
First amplifier passes sequentially through the first delay unit, the second delay unit, balanced device, the 3rd amplifier, the 3rd prolongs
Shi Danyuan, the 4th delay unit are connected with numerical-control attenuator.
The multi-channel digital control delayer, wherein, the power supply and the first amplifier, time-delay mechanism, numerical-control attenuator,
Second amplifier, RF switch, control chip are connected.
The multi-channel digital control delayer, wherein, first delay unit include the first single-pole double-throw switch (SPDT), second
Single-pole double-throw switch (SPDT), the first microstrip line；Described first single-pole double-throw switch (SPDT) one end is connected with the first amplifier, second end and first
Microstrip line one end is connected, and the 3rd end is connected with the second single-pole double-throw switch (SPDT) first end；The first microstrip line other end and second
Single-pole double-throw switch (SPDT) second end is connected；The 3rd end of second single-pole double-throw switch (SPDT) is connected with the second delay unit.
The multi-channel digital control delayer, wherein, second delay unit include the 3rd single-pole double-throw switch (SPDT), the 4th
Single-pole double-throw switch (SPDT), the second microstrip line；Described 3rd single-pole double-throw switch (SPDT) one end is connected with the first delay unit, second end and the
Two microstrip line one end are connected, and the 3rd end is connected with the 4th single-pole double-throw switch (SPDT) first end；The second microstrip line other end and
Four single-pole double-throw switch (SPDT) second ends are connected；The 3rd end of 4th single-pole double-throw switch (SPDT) is connected with balanced device.
The multi-channel digital control delayer, wherein, the 3rd delay unit include the 5th single-pole double-throw switch (SPDT), the 6th
Single-pole double-throw switch (SPDT), the 3rd microstrip line；Described 5th single-pole double-throw switch (SPDT) one end is connected with the 3rd amplifier, second end and the 3rd
Microstrip line one end is connected, and the 3rd end is connected with the 6th single-pole double-throw switch (SPDT) first end；The 3rd microstrip line other end and the 6th
Single-pole double-throw switch (SPDT) second end is connected；The 3rd end of 6th single-pole double-throw switch (SPDT) is connected with the 4th delay unit.
The multi-channel digital control delayer, wherein, the 4th delay unit include the 7th single-pole double-throw switch (SPDT), the 8th
Single-pole double-throw switch (SPDT), the 4th microstrip line；Described 7th single-pole double-throw switch (SPDT) one end is connected with the 3rd delay unit, second end and the
Four microstrip line one end are connected, and the 3rd end is connected with the 8th single-pole double-throw switch (SPDT) first end；The 4th microstrip line other end and
Eight single-pole double-throw switch (SPDT) second ends are connected；The 3rd end of 8th single-pole double-throw switch (SPDT) is connected with numerical-control attenuator.
The multi-channel digital control delayer, wherein, first microstrip line, the second microstrip line, the 3rd microstrip line and
Four microstrip lines are serpentine configuration, and corner carries out corner cut processing.
Advantageous effect：
A kind of multi-channel digital control delayer of the present invention, can using corner cut treated microstrip line is carried out as delay component
Meet radar work when input/output standing-wave ratio, the performance requirement of dynamic range, and signal frequency 3 GHz~
When in 5.5GHz, maximum delay mean square error when multi-channel digital control delayer works is 0.1052ns, in use thunder
Position beam space dispersion up to system in off-center frequency point is greatly reduced, and improves the overall performance of radar.
Description of the drawings
Fig. 1 is the structure diagram of the multi-channel digital control delayer of the present invention.
Fig. 2 is the structure diagram of the time-delay mechanism of the multi-channel digital control delayer of the present invention.
Fig. 3 is the microstrip line turning performance analysis chart of the multi-channel digital control delayer of the present invention.
Fig. 4 is the first delay unit structure chart of the multi-channel digital control delayer of the present invention.
Fig. 5 is the second delay unit structure chart of the multi-channel digital control delayer of the present invention.
Fig. 6 is the 3rd delay unit structure chart of the multi-channel digital control delayer of the present invention.
Fig. 7 is the 4th delay unit structure chart of the multi-channel digital control delayer of the present invention.
Fig. 8 is the structure chart of the balanced device of the multi-channel digital control delayer of the present invention.
Fig. 9 is the delay performance analysis figure of the multi-channel digital control delayer of the present invention.
Figure 10 is the performance analysis chart of the multi-channel digital control delayer of the present invention.
Specific embodiment
The present invention provides a kind of multi-channel digital control delayer, to make the purpose of the present invention, technical solution and effect more clear
Chu, clearly, the present invention is described in more detail below.It should be appreciated that specific embodiment described herein is only used to solve
The present invention is released, is not intended to limit the present invention.
- Figure 10 is please referred to Fig.1, Fig. 1 is the structure diagram of the multi-channel digital control delayer of the present invention；Fig. 2 is the present invention
Multi-channel digital control delayer time-delay mechanism structure diagram；Fig. 3 is the micro-strip of the multi-channel digital control delayer of the present invention
Line turning performance analysis chart；Fig. 4 is the first delay unit structure chart of the multi-channel digital control delayer of the present invention；Fig. 5 is this hair
Second delay unit structure chart of bright multi-channel digital control delayer；Fig. 6 is the 3 of the multi-channel digital control delayer of the present invention
Delay unit structure chart；Fig. 7 is the 4th delay unit structure chart of the multi-channel digital control delayer of the present invention；Fig. 8 is the present invention
Multi-channel digital control delayer balanced device structure chart；Fig. 9 is the delay performance point of the multi-channel digital control delayer of the present invention
Analysis figure；Figure 10 is the performance analysis chart of the multi-channel digital control delayer of the present invention.As described in Figure, a kind of multi-channel digital control delay
Device, wherein, the multi-channel digital control delayer includes, and numerical control delay component 10, power supply 20 controls chip 30.
Numerical control delay component 10 is used to carry out signal delay process, and four delay units are included in the time-delay mechanism,
The multistage delay of progress is mutually combined by four delay units.
Power supply 20 is used to be powered multi-channel digital control delayer；Control chip 30 is used to that multi-channel digital control to be controlled to be delayed
Device；During specifically used, input terminal input radar signal carries out signal delay process by multi-channel digital control delayer,
And signal exports by treated.
The numerical control delay component specifically includes, the first amplifier 110, time-delay mechanism 120, numerical-control attenuator 130, and second
Amplifier 140, RF switch 150；Input terminal pass sequentially through the first amplifier 110, time-delay mechanism 120, numerical-control attenuator 130,
Second amplifier 140, RF switch 150 are connected with output terminal；
The time-delay mechanism that the present invention uses, it can be ensured that the delay precision of signal input/output, and insertion damage can be reduced
Consumption, meets requirement of the radar system to input/output standing-wave ratio.Input signal is amplified by the first amplifier to ensure
System gain, and control noise coefficient.Since the delay circuit that in different delayed time state, signal passes through is different through length, in order to
Ensure under different delayed time state, the fluctuation range of gain, adds in numerical-control attenuator after time-delay mechanism when control system works
To compensate the system gain of different delayed time position.In order to ensure dynamic range and further improve system overall gain, it is delayed in numerical control
The second amplifier is added in after device.
In specific embodiment, numerical-control attenuator uses six numerical-control attenuator HMC624ALP4, with insertion loss
It is small（Under 0dB states）, the characteristics of attenuation accuracy is high, this numerical-control attenuator has the attenuation of 0dB~31.5dB, and precision is
0.5dB。
Using MGA-30989, this amplifier has the first amplifier and the second amplifier in numerical control delay component
High Linear gain function in 2~6GHz of frequency range.
For the ease of system detectio, the RF switch in digitally programmable delayer is Pe4246 SPST, is controlled by 5V voltages
System.The insertion loss of RF switch is less than 2dB, and isolation is more than 40dB under the frequency of 4.5GHz, and the compression point for inputting 1dB is big
In 30dBm.
In a particular embodiment, the control chip 30 and time-delay mechanism 120, numerical-control attenuator 130, the second amplifier
140th, RF switch 150 is connected.By controlling chip respectively to time-delay mechanism, numerical-control attenuator, the second amplifier and radio frequency
Switch is controlled, it is ensured that each unit cooperates in equipment.
In a particular embodiment, the time-delay mechanism 120 specifically includes：First delay unit 121, the second delay unit
122, balanced device 123, the 3rd amplifier 124, the 3rd delay unit 125, the 4th delay unit 126；
First amplifier 110 passes sequentially through the first delay unit 121, the second delay unit 122, balanced device the 123, the 3rd and puts
Big device 124, the 3rd delay unit 125, the 4th delay unit 126 are connected with numerical-control attenuator 130.
Since the low cut of the first amplifier is small, high frequency attenuation is big, is added in time-delay mechanism for this feature
Weighing apparatus to improve sensibility of the system gain to frequency, and adds in the 3rd amplifier to ensure the dynamic of system after the equalizer
Scope and system gain.3rd amplifier uses MGA-30989, this amplifier has the high line in 2~6GHz of frequency range
Property gain function.
First delay unit, the second delay unit, the delay duration not phase of the 3rd delay unit and the 4th delay unit
Together, the first delay unit, the second delay unit, the 3rd delay unit, the 4th delay unit, four delay units mutually group are passed through
It closes and carries out multistage delay.By the first delay unit, the second delay unit, the 3rd delay unit, the 4th delay unit to input
Signal carries out multistage delay, so that multi-channel digital control delayer has larger reference time delay.
In more specific embodiment, the balanced device is symmetrical structure, and the resistance value of balanced device is the Ω of R1=R2=161,
Using the film resistor of 0603 encapsulation, Fig. 8 is the structure chart of the balanced device of the multi-channel digital control delayer of the present invention, wherein each portion
Point dimensions length value see the table below.
Since the shape of balanced device is bilateral symmetry, by above-mentioned dimensions length value, balanced device can be determined
Full-size, wherein 1mil be mil, 1mil=0.0254mm.
In a particular embodiment, 20 and first amplifier 110 of power supply, time-delay mechanism 120, numerical-control attenuator 130,
Two amplifiers 140, RF switch 150, control chip 30 are connected.It is declined by power supply to the first amplifier, time-delay mechanism, numerical control
Subtract device, the second amplifier, RF switch, control chip to be powered, to ensure each unit normal operation.
The 3rd amplifier in this component can generate high line using MGA-30989 in the frequency range of 2~6GHz
Property gain.
In a specific embodiment, first delay unit 121 includes the first single-pole double-throw switch (SPDT) 1211, the second hilted broadsword
Commutator 1213, the first microstrip line 1212；Described first single-pole double-throw switch (SPDT), 1211 one end is connected with the first amplifier 110,
Second end is connected with 1212 one end of the first microstrip line, and the 3rd end is connected with 1213 first end of the second single-pole double-throw switch (SPDT)；Described
One microstrip line, 1212 other end is connected with 1213 second end of the second single-pole double-throw switch (SPDT)；Second single-pole double-throw switch (SPDT) 1,213
Three ends are connected with the second delay unit 122.
In numerical control time delay process, the first single-pole double-throw switch (SPDT) and the second single-pole double-throw switch (SPDT) are to realize that signal is being delayed
The switching of position cabling and reference bit cabling, and pass through the position that is delayed and realize delay function with the delay inequality with reference to interdigit.It walks delay position
Line i.e. the first microstrip line, what is be connected directly between reference bit cabling i.e. the first single-pole double-throw switch (SPDT) and the second single-pole double-throw switch (SPDT) leads
Line.
The first single-pole double-throw switch (SPDT) and the second single-pole double-throw switch (SPDT) in the present invention use HMC232LP4.
In a specific embodiment, second delay unit 122 includes the 3rd single-pole double-throw switch (SPDT) 1221, the 4th hilted broadsword
Commutator 1223, the second microstrip line 1222；Described 3rd single-pole double-throw switch (SPDT), 1221 one end and 121 phase of the first delay unit
Even, second end is connected with 1222 one end of the second microstrip line, and the 3rd end is connected with 1223 first end of the 4th single-pole double-throw switch (SPDT)；It is described
Second microstrip line, 1222 other end is connected with 1223 second end of the 4th single-pole double-throw switch (SPDT)；4th single-pole double-throw switch (SPDT) 1223
3rd end is connected with balanced device 123.
In a specific embodiment, the 3rd delay unit 125 includes the 5th single-pole double-throw switch (SPDT) 1251, the 6th hilted broadsword
Commutator 1253, the 3rd microstrip line 1252；Described 5th single-pole double-throw switch (SPDT), 1251 one end is connected with the 3rd amplifier 124,
Second end is connected with 1252 one end of the 3rd microstrip line, and the 3rd end is connected with 1253 first end of the 6th single-pole double-throw switch (SPDT)；Described
Three microstrip lines, 1252 other end is connected with 1253 second end of the 6th single-pole double-throw switch (SPDT)；6th single-pole double-throw switch (SPDT) 1,253
Three ends are connected with the 4th delay unit 126.
In a specific embodiment, the 4th delay unit 126 includes the 7th single-pole double-throw switch (SPDT) 1261, the 8th hilted broadsword
Commutator 1263, the 4th microstrip line 1262；Described 7th single-pole double-throw switch (SPDT), 1261 one end and 125 phase of the 3rd delay unit
Even, second end is connected with 1262 one end of the 4th microstrip line, and the 3rd end is connected with 1263 first end of the 8th single-pole double-throw switch (SPDT)；It is described
4th microstrip line, 1262 other end is connected with 1263 second end of the 8th single-pole double-throw switch (SPDT)；8th single-pole double-throw switch (SPDT) 1263
3rd end is connected with numerical-control attenuator 130.
Following table is each time delay process size：
By the first delay unit, the second delay unit, the 3rd delay unit, the 4th delay unit stack combinations, at most may be used
Realize the delay process operation of 9.375ns, minimum delay time is 0.625ns, therefore the delay of the delayer in the present invention
Resolution ratio is 0.625ns, and the absolute value of delay precision is 0.35ns.
In a specific embodiment, the multi-channel digital control delayer includes 2-20 groups numerical control delay component 10.Wherein, institute
It states numerical control delay component 10 with power supply 20 to be connected, the numerical control delay component 10 is connected with control chip 30.
In the particular embodiment, using 8 groups of numerical controls delay component composition multi-channel digital control delayers, eight passages are realized
Numerical control is delayed.
The operation result that 15 delay states are carried out to digitally programmable delayer carries out the attenuation of error analysis, wherein numerical-control attenuator
Value is arranged to 0db.
By upper table carry out analysis as can be seen that digitally programmable delayer run 15 delay states in, 4.0 GHz~
In the range of 5.0GHz, maximum delay mean square error is 0.1052ns, and the duration curve of upper rheme delay state is as shown in Figure 9.Cause
This uses eight passage digitally programmable delayers, in wider frequency range, can effectively control maximum delay mean square deviation, solve reality
In the application process of border the problem of wave beam spatial dispersion.
Upper table is the output gain of this delayer, and by upper table as can be seen that after attenuation compensation, maximum output gain is
23.84dB, minimum output gain is 22.90dB, therefore delayer has the characteristics that preferable output gain, meets system
Use demand, attenuation curve are as shown in Figure 10.
In more specific embodiment, first microstrip line, the second microstrip line, the 3rd microstrip line and the 4th microstrip line are equal
For serpentine configuration, and corner carries out corner cut processing.In order to save space, the first microstrip line, the second microstrip line, the 3rd micro-strip
Line and the 4th microstrip line use snakelike cabling.Corner cut processing is carried out by the corner to microstrip line, passes through the data in Fig. 3
It can obtain, in wider frequency range, input return loss can be reduced by carrying out corner cut processing to the corner of microstrip line
With output return loss, and it is actually subjected to system reverse transfer loss during the work time and positive transmission loss satisfaction
It asks.
In practical work process of the present invention, pass through the first microstrip line, the second microstrip line, the 3rd microstrip line and the 4th micro-strip
Line realizes system delay, and first microstrip line, the second microstrip line, the 3rd microstrip line and the 4th microstrip line are laid in medium base
On plate, the medium substrate uses the microwave material of low-loss Rogers4350B, effective dielectric constant 3.48.Medium
The thickness of substrate is 0.254mm, covers copper thickness for 17 μm, most long delay link is 5ns, be can be calculated by analysis, maximum is prolonged
The length of the microstrip line of Shi Huanjie is 912mm.
In conclusion the invention discloses a kind of multi-channel digital control delayer, including：For carrying out delay process to signal
Numerical control delay component；For the power supply being powered to multi-channel digital control delayer；For controlling multi-channel digital control delayer
Control chip；The numerical control delay component includes, the first amplifier, time-delay mechanism, numerical-control attenuator, and the second amplifier is penetrated
Frequency switchs；Comprising four delay units in the time-delay mechanism, the multistage delay of progress is mutually combined by four delay units.This
A kind of multi-channel digital control delayer of invention using corner cut treated microstrip line is carried out as delay component, is prolonged by multiple
Shi Danyuan realizes multistage delay, input/output standing-wave ratio, the performance requirement of dynamic range when disclosure satisfy that radar work, and
When signal frequency is in 3 GHz~5.5GHz, maximum delay mean square error when multi-channel digital control delayer works is
0.1052ns, in use radar system be greatly reduced in the position beam space dispersion of off-center frequency point, improve
The overall performance of radar.
It should be appreciated that the application of the present invention is not limited to the above, it for those of ordinary skills, can
To be improved or converted according to the above description, all these modifications and variations should all belong to the guarantor of appended claims of the present invention
Protect scope.
Claims (9)
1. a kind of multi-channel digital control delayer, which is characterized in that the multi-channel digital control delayer includes：
For carrying out the numerical control delay component of delay process to signal；
For the power supply being powered to multi-channel digital control delayer；
For controlling the control chip of multi-channel digital control delayer；
The numerical control delay component includes, the first amplifier, time-delay mechanism, numerical-control attenuator, the second amplifier, RF switch；
Input terminal passes sequentially through the first amplifier, time-delay mechanism, numerical-control attenuator, the second amplifier, RF switch and output terminal
It is connected；
Comprising four delay units in the time-delay mechanism, the multistage delay of progress is mutually combined by four delay units.
2. multi-channel digital control delayer according to claim 1, which is characterized in that control chip and the time-delay mechanism,
Numerical-control attenuator, RF switch are connected.
3. multi-channel digital control delayer according to claim 1, which is characterized in that the time-delay mechanism specifically includes：The
One delay unit, the second delay unit, balanced device, the 3rd amplifier, the 3rd delay unit, the 4th delay unit；
First amplifier passes sequentially through the first delay unit, the second delay unit, balanced device, the 3rd amplifier, the 3rd prolongs
Shi Danyuan, the 4th delay unit are connected with numerical-control attenuator.
4. multi-channel digital control delayer according to claim 1, which is characterized in that the power supply and the first amplifier prolong
When device, numerical-control attenuator, the second amplifier, RF switch, control chip be connected.
5. multi-channel digital control delayer according to claim 3, which is characterized in that first delay unit includes first
Single-pole double-throw switch (SPDT), the second single-pole double-throw switch (SPDT), the first microstrip line；Described first single-pole double-throw switch (SPDT) one end and the first amplifier
It is connected, second end is connected with first microstrip line one end, and the 3rd end is connected with the second single-pole double-throw switch (SPDT) first end；Described first is micro-
The band line other end is connected with the second single-pole double-throw switch (SPDT) second end；The 3rd end of second single-pole double-throw switch (SPDT) and the second delay are single
Member is connected.
6. multi-channel digital control delayer according to claim 3, which is characterized in that second delay unit includes the 3rd
Single-pole double-throw switch (SPDT), the 4th single-pole double-throw switch (SPDT), the second microstrip line；Described 3rd single-pole double-throw switch (SPDT) one end and the first delay are single
Member is connected, and second end is connected with second microstrip line one end, and the 3rd end is connected with the 4th single-pole double-throw switch (SPDT) first end；Described second
The microstrip line other end is connected with the 4th single-pole double-throw switch (SPDT) second end；The 3rd end of 4th single-pole double-throw switch (SPDT) and balanced device phase
Even.
7. multi-channel digital control delayer according to claim 3, which is characterized in that the 3rd delay unit includes the 5th
Single-pole double-throw switch (SPDT), the 6th single-pole double-throw switch (SPDT), the 3rd microstrip line；Described 5th single-pole double-throw switch (SPDT) one end and the 3rd amplifier
It is connected, second end is connected with the 3rd microstrip line one end, and the 3rd end is connected with the 6th single-pole double-throw switch (SPDT) first end；Described 3rd is micro-
The band line other end is connected with the 6th single-pole double-throw switch (SPDT) second end；The 3rd end of 6th single-pole double-throw switch (SPDT) and the 4th delay are single
Member is connected.
8. multi-channel digital control delayer according to claim 3, which is characterized in that the 4th delay unit includes the 7th
Single-pole double-throw switch (SPDT), the 8th single-pole double-throw switch (SPDT), the 4th microstrip line；Described 7th single-pole double-throw switch (SPDT) one end and the 3rd delay are single
Member is connected, and second end is connected with the 4th microstrip line one end, and the 3rd end is connected with the 8th single-pole double-throw switch (SPDT) first end；Described 4th
The microstrip line other end is connected with the 8th single-pole double-throw switch (SPDT) second end；The 3rd end of 8th single-pole double-throw switch (SPDT) and numerical control attenuation
Device is connected.
9. multi-channel digital control delayer according to claim 8, which is characterized in that first microstrip line, the second micro-strip
Line, the 3rd microstrip line and the 4th microstrip line are serpentine configuration, and corner carries out corner cut processing.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111130670A (en) * | 2020-01-15 | 2020-05-08 | 西安电子科技大学 | Signal path signal transmission system, method and device for wireless channel experiment |
| CN111537971A (en) * | 2020-06-22 | 2020-08-14 | 中国电子科技集团公司第十四研究所 | Circuit and method for quickly compensating amplitude-phase characteristics of delay assembly |
| CN114124132A (en) * | 2021-11-11 | 2022-03-01 | 上海航天科工电器研究院有限公司 | Radio frequency receiving and transmitting assembly with time delay function |
| CN115308520A (en) * | 2022-10-10 | 2022-11-08 | 杭州三海电子有限公司 | Method, program and circuit for determining delay time of multichannel sequential sampling current |
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| CN114124132A (en) * | 2021-11-11 | 2022-03-01 | 上海航天科工电器研究院有限公司 | Radio frequency receiving and transmitting assembly with time delay function |
| CN115308520A (en) * | 2022-10-10 | 2022-11-08 | 杭州三海电子有限公司 | Method, program and circuit for determining delay time of multichannel sequential sampling current |
| CN115308520B (en) * | 2022-10-10 | 2023-01-24 | 杭州三海电子有限公司 | Method, program and circuit for determining delay time of multichannel sequential sampling current |
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