CN108076586B - Circuit board and method for manufacturing the same - Google Patents
Circuit board and method for manufacturing the same Download PDFInfo
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- CN108076586B CN108076586B CN201611186918.5A CN201611186918A CN108076586B CN 108076586 B CN108076586 B CN 108076586B CN 201611186918 A CN201611186918 A CN 201611186918A CN 108076586 B CN108076586 B CN 108076586B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 19
- 238000000034 method Methods 0.000 title claims description 45
- 229910052751 metal Inorganic materials 0.000 claims abstract description 49
- 239000002184 metal Substances 0.000 claims abstract description 49
- 239000000758 substrate Substances 0.000 claims abstract description 36
- 238000009713 electroplating Methods 0.000 claims description 31
- 239000004020 conductor Substances 0.000 claims description 8
- 239000000945 filler Substances 0.000 claims description 8
- 230000000149 penetrating effect Effects 0.000 claims description 7
- 230000000873 masking effect Effects 0.000 claims description 5
- 229920002120 photoresistant polymer Polymers 0.000 claims description 4
- 230000007423 decrease Effects 0.000 claims description 2
- 238000005553 drilling Methods 0.000 description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 5
- 229910052802 copper Inorganic materials 0.000 description 5
- 239000010949 copper Substances 0.000 description 5
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 239000011347 resin Substances 0.000 description 4
- 229920005989 resin Polymers 0.000 description 4
- 229910052718 tin Inorganic materials 0.000 description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 3
- 238000013461 design Methods 0.000 description 3
- 238000007747 plating Methods 0.000 description 3
- 238000012546 transfer Methods 0.000 description 3
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- 230000000052 comparative effect Effects 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000003292 glue Substances 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 239000012811 non-conductive material Substances 0.000 description 2
- 229910052763 palladium Inorganic materials 0.000 description 2
- 238000007639 printing Methods 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 239000011135 tin Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000012993 chemical processing Methods 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000004381 surface treatment Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/0929—Conductive planes
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
- Manufacturing Of Printed Wiring (AREA)
- Structure Of Printed Boards (AREA)
Abstract
The invention provides a circuit board, which comprises a substrate. A metal layer is located on a surface of the substrate. A conductive layer is located on the metal layer and includes a first conductive layer and a second conductive layer. The through holes comprise a dense area and a loose area, and penetrate through the conductive layer, the metal layer and the substrate. The conductive layer has a substantially flat upper surface, and an interface exists at the junction of the first conductive layer and the second conductive layer. The invention also provides a manufacturing method of the circuit board.
Description
Technical Field
The present invention relates to a circuit board and a method for manufacturing the same, and more particularly, to a circuit board having a conductive layer with a uniform thickness and a method for manufacturing the same.
Background
Printed Circuit Boards (PCBs) are circuit boards in which conductive wiring for connecting circuit parts is patterned according to circuit design, and then an electrical conductor is formed on an insulator by mechanical and chemical processing, surface treatment, and the like. The circuit pattern is formed by printing, photolithography, etching, plating, etc. to form precise wiring, which is used as an assembly platform for supporting electronic components and interconnecting circuits between the components.
At present, the number of via holes in the inner layer of the carrier plate is more and more, and the number of via holes in the inner layer is concentrated in a wafer implanting area due to functional design factors of products, so that the density distribution of via holes between layers is uneven. Because of the influence of uneven distribution, the high dense hole number region disperses current in the electroplating process, and the low dense hole number region concentrates current, so that the phenomenon that the thickness of the conductive layer is uneven after the electroplating is performed on the hole number dense region and the hole number loose region is caused, the resistance value and the impedance of a product are influenced, and the stability of the tin ball implanting/tin paste printing during subsequent processes such as packaging is also influenced.
Therefore, there is a need to develop a circuit board having a conductive layer with a uniform thickness and a method for manufacturing the same.
Disclosure of Invention
According to an embodiment, the present invention provides a circuit board, including a substrate; a metal layer on a surface of the substrate; a conductive layer on the metal layer, including a first conductive layer and a second conductive layer; the through holes comprise a dense area and a loose area and penetrate through the conducting layer, the metal layer and the substrate; the conductive layer has a substantially flat upper surface, and an interface exists at the junction of the first conductive layer and the second conductive layer.
According to another embodiment, the present invention provides a method of manufacturing a circuit board, including: forming a metal layer on a surface of a substrate; forming a plurality of through holes penetrating through the metal layer and the substrate, wherein the through holes comprise a dense area and a loose area; performing a first electroplating to form a first conductive layer on the metal layer and in the through holes, wherein the first conductive layer comprises a recessed area corresponding to the dense area; forming a shielding layer on the first conductive layer; forming an opening in the shielding layer to expose the recessed region of the first conductive layer; performing a second electroplating to form a second conductive layer in the opening to cover the first conductive layer; removing the shielding layer; forming a filler in the through holes; and performing a planarization process to remove a portion of the first conductive layer and a portion of the second conductive layer.
According to another embodiment, the present invention provides a method of manufacturing a circuit board, including: forming a metal layer on a surface of a substrate; forming a plurality of through holes penetrating through the metal layer and the substrate, wherein the through holes comprise a dense area and a loose area; forming a shielding layer on the metal layer; forming an opening in the shielding layer to expose part of the metal layer and the dense region; performing a first electroplating to form a first conductive layer in the opening; removing the shielding layer; performing second electroplating to form a second conductive layer covering the first conductive layer and the metal layer and located in the through holes; forming a filler in the through holes; and performing a planarization process to remove a portion of the first conductive layer and a portion of the second conductive layer.
In order to make the aforementioned and other objects, features and advantages of the present invention comprehensible, preferred embodiments accompanied with figures are described in detail below:
drawings
FIGS. 1A-1E are schematic cross-sectional views illustrating intermediate stages of a method for manufacturing a circuit board according to a first embodiment of the present invention;
FIGS. 2A-2E are schematic cross-sectional views illustrating intermediate stages of a method for manufacturing a circuit board according to a second embodiment of the present invention;
FIGS. 3A-3B show the results of analysis by a roughness measuring instrument after electroplating and leveling of a circuit board manufactured by the prior art;
FIGS. 4A-4B show the results of the thickness gauge analysis after electroplating and leveling of the circuit board manufactured according to the first embodiment of the present invention; and
fig. 5A-5B show the results of the thickness gauge analysis after plating and leveling of the circuit board manufactured according to the second embodiment of the present invention.
Description of reference numerals:
100. 200-substrate
102. 202 to surface
110. 210-metal layer
120. 220-through hole
122. 222-dense region
124. 224-loosening zone
130. 250-first conductive layer
140. 230-shielding layer
150. 240-opening
160. 260 to the second conductive layer
170. 270-conductive layer
172. 272 to upper surface
180. 280-filling holes
S1, S2-interface
Detailed Description
The following describes a circuit board and a method of manufacturing the same according to an embodiment of the present invention. It should be understood, however, that the description herein of specific embodiments is provided for illustration only, and not for the purpose of limiting the invention as defined by the appended claims. In the drawings and the description of the embodiments of the present invention, the same reference numerals are used to designate the same or similar components.
The invention utilizes two electroplating processes to additionally plate the conductive layer on the area with smaller electroplating density, so that the thickness of the conductive layer in the hole number dense area is higher than that of the conductive layer in the hole number loose area, and the uniformity of the whole conductive layer is effectively improved after the subsequent leveling process.
Referring to fig. 1E, a cross-sectional view of the circuit board according to the first embodiment of the invention is shown. In the present embodiment, the circuit board includes a substrate 100, a metal layer 110 on the substrate 100, a conductive layer 170 on the metal layer 110, and a plurality of filling holes 180, including a dense region 122 and a loose region 124, penetrating through the conductive layer 170, the metal layer 110, and the substrate 100. The substrate 100 has an opposite surface 102. In the present embodiment, the substrate 100 may be made of a resin material.
In one embodiment, the second conductive layer 160 is located on the first conductive layer 130. In the present embodiment, the interface S1 existing at the adjacent position of the first conductive layer 130 and the second conductive layer 160 is a concave interface, the cross-sectional profile of the first conductive layer 130 is a concave shape, and the cross-sectional profile of the second conductive layer 160 is a convex shape, as shown in fig. 1E.
Fig. 2E is a schematic cross-sectional view of a circuit board according to a second embodiment of the invention. In the present embodiment, the circuit board includes a substrate 200, a metal layer 210 on the substrate 200, a conductive layer 270 on the metal layer 210, and a plurality of filling holes 280 including a dense region 222 and a loose region 224 penetrating the conductive layer 270, the metal layer 210, and the substrate 200. The substrate 200 has an opposite surface 202. In the present embodiment, the substrate 200 may be made of a resin material.
The difference from the circuit board shown in fig. 1E is that in the present embodiment, the first conductive layer 250 and the second conductive layer 260 are both located on the metal layer 210, the first conductive layer 250 is located in the dense region 222 of the filling hole 280, and the second conductive layer 260 is located in the loose region 224 of the filling hole 280. In the present embodiment, the interface S2 existing at the joint of the first conductive layer 250 and the second conductive layer 260 is a vertical interface, as shown in fig. 2E.
Compared with the circuit board manufactured by the prior art, the circuit board manufactured by the invention has the problem that the thickness of the conductive layer is not uniform, so that the phenomenon that the thickness of the conductive layer is too thin is generated after the leveling process.
Fig. 1A to 1E are schematic cross-sectional views illustrating intermediate stages of a circuit board manufacturing method according to a first embodiment of the present invention.
Referring to fig. 1A, a substrate 100 having an opposite surface 102 is provided. In the present embodiment, the substrate 100 may be made of a resin material. A metal layer 110 is formed on the surface 102 of the substrate 100. Next, a plurality of vias 120 may be formed through the metal layer 110 and the substrate 100 by a laser or mechanical drilling process, wherein the vias 120 include a dense region 122 and a loose region 124. After the laser or mechanical drilling process, a step of removing the glue residue may be performed to remove the residues (not shown) in the through holes 120 after the laser or mechanical drilling process.
Next, referring to fig. 1B, a first conductive layer 130 is formed on the metal layer 110 and in the through holes 120 by a first electroplating process, wherein the first conductive layer 130 includes a recessed region 132 corresponding to the dense region 122. The contour of the recessed region 132 may decrease from the two sides toward the center. A seed layer (not shown) may be conformally formed on the metal layer 110 and in the vias 120 prior to the first electroplating.
Referring to fig. 1C, an image transfer process is performed to form a shielding layer 140 on the first conductive layer 130. The masking layer 140 may be a photoresist layer, such as a dry film. Next, an opening 150 is formed in the shielding layer 140 by exposure and development processes to expose the recessed region 132 of the first conductive layer 130. Then, a second electroplating is performed on the exposed first conductive layer 130 to form a second conductive layer 160 in the opening 150, covering the first conductive layer 130. An interface S1 exists where the first conductive layer 130 and the second conductive layer 160 abut. The interface S1 is a concave interface, and the cross-sectional profile of the first conductive layer 130 is concave, and the cross-sectional profile of the second conductive layer 160 is convex, as shown in fig. 1C. Wherein the profile of the interface S1 is the same as the profile of the recessed region 132.
It is noted that the thickness of the second conductive layer 160 can be adjusted according to the degree of the recess 132 of the first conductive layer 130. In the present embodiment, the thickness of the second conductive layer 160 is greater than or equal to the depth of the recess 132.
Next, referring to fig. 1D, the shielding layer 140 is removed.
Referring to fig. 1E, a filler is formed in the through holes 120. The filler may be a conductive material or a non-conductive material. Next, a planarization process is performed to remove a portion of the first conductive layer 130 and a portion of the second conductive layer 160, thereby forming a conductive layer 170 and a plurality of filling holes 180. Conductive layer 170 has a substantially planar surface 172.
As shown in fig. 1E, the overall conductive layer 170 has a uniform thickness, and compared to the uneven thickness of the conductive layer caused by the uneven distribution of the via holes in the prior art, the thickness difference of the conductive layer 170 in the circuit board of this embodiment is significantly reduced, thereby achieving the purpose of improving the uniformity of the overall conductive layer.
The embodiment provides an effective solution to the problem that the prior art only performs electroplating once to form a conductive layer, which often results in uneven thickness of the conductive layer. In the embodiment, the conductive layer is formed by two times of electroplating, because the first conductive layer 130 has the recessed region 132, the second conductive layer 160 is formed by the second electroplating to fill the recessed region 132, and the thickness of the conductive layer in the hole number dense region is higher than that in the hole number loose region, and then a flat conductive layer 170 is formed by the subsequent leveling process, thereby improving the uniformity of the entire conductive layer and the stability of the subsequent process.
FIGS. 2A-2E are schematic cross-sectional views illustrating intermediate stages of a circuit board manufacturing method according to a second embodiment of the present invention.
Referring to fig. 2A, a substrate 200 having an opposite surface 202 is provided. In the present embodiment, the substrate 200 may be made of a resin material. A metal layer 210 is formed on the surface 202 of the substrate 200. Next, a plurality of through holes 220 may be formed through the metal layer 210 and the substrate 200 by a laser or mechanical drilling process, wherein the through holes 220 include a dense region 222 and a loose region 224. After the laser or mechanical drilling process, a step of removing the glue residue may be performed to remove the residues (not shown) in the through holes 220 after the laser or mechanical drilling process.
Next, referring to fig. 2B, a shielding layer 230 is formed on the metal layer 210. The masking layer 230 may be a photoresist layer, such as a dry film. A seed layer (not shown) may also be conformally formed on the metal layer 210 and in the vias 220 before the masking layer 230 is formed on the metal layer 210. Then, an image transfer process is performed to form an opening 240 in the shielding layer 230 by an exposure and development process, exposing a portion of the metal layer 210 and the dense region 222. Next, a first electroplating is performed to form a first conductive layer 250 in the opening 240.
It should be noted that the thickness of the first conductive layer 250 can be adjusted according to the conductive layer thickness difference known in the art. In the present embodiment, the thickness of the first conductive layer 250 is greater than or equal to the difference in the thicknesses of the conductive layers known in the prior art.
Next, referring to fig. 2C, the shielding layer 230 is removed.
Referring to fig. 2D, a second electroplating is performed to form a second conductive layer 260 covering the first conductive layer 250 and the metal layer 210, and the second conductive layer 260 is formed in the through holes 220. An interface S2 exists where the first conductive layer 250 and the second conductive layer 260 abut. Interface S2 is a vertical interface, as shown in FIG. 2D.
Referring to fig. 2E, a filler is formed in the through holes 220. The filler may be a conductive material or a non-conductive material. Next, a planarization process is performed to remove a portion of the first conductive layer 250 and a portion of the second conductive layer 260, thereby forming a conductive layer 270 and a plurality of filling holes 280.
Thus, the circuit board according to the second embodiment of the present invention is completed, and as can be seen from fig. 2E, the overall conductive layer 270 has a uniform thickness, compared to the phenomenon of non-uniform thickness of the conductive layer due to non-uniform via hole distribution in the prior art, in the circuit board according to the present embodiment, the thickness difference of the conductive layer 270 is significantly reduced, so as to achieve the purpose of improving the uniformity of the overall conductive layer.
It is noted that, due to the influence of the uneven distribution of the number of holes, the second conductive layer 260 also has a phenomenon that the thickness is thin in the area with dense number of holes and thick in the area with loose number of holes. However, in the present embodiment, the first conductive layer 250 is formed in advance in the hole-dense region to compensate for the expected thickness difference, so that the conductive layer thickness in the hole-dense region is greater than that in the hole-loose region after the second conductive layer 260 is formed by electroplating, and then a flat conductive layer 270 is formed by a subsequent planarization process to improve the uniformity of the entire conductive layer and the stability of the subsequent processes. Therefore, the present embodiment also provides an effective solution to the problem that the thickness of the conductive layer is not uniform due to the formation of the conductive layer by electroplating twice.
Due to functional design factors of products, the number of the inner-layer through holes is more and more designed and is concentrated in a crystal planting area, so that the number of the inner-layer through holes is unevenly distributed, and the phenomenon that the thickness of a conductive layer is uneven after electroplating is caused in a hole number dense area and a hole number loose area. The circuit board manufacturing method provided by the invention utilizes two electroplating processes to be matched with the image transfer process, and additionally plates the conducting layer on the area with smaller electroplating density, so that the thickness of the conducting layer in the hole number dense area is higher than that of the conducting layer in the hole number loose area, and after the subsequent leveling process, the thickness difference of the conducting layers in the hole number dense area and the hole number loose area can be greatly reduced, and the uniformity of the whole conducting layer is effectively improved. When the thickness of the conductive layer is uniform, the stable line width can be maintained when the subsequent line forming etching process is carried out, and the situation that the line width is unstable or residues exist is avoided. After the thickness uniformity of the conductive layer is improved, the stability of subsequent processes such as packaging process can be further improved.
Comparative examples and examples are provided below to illustrate the differences between the prior art circuit board and the circuit board provided by the present invention:
comparative example
Fig. 3A and 3B show the results of analysis of the roughness measuring instrument after electroplating and after leveling, respectively, of the circuit board manufactured by the prior art. As can be seen from FIGS. 3A and 3B, the conductive layer had a dishing value of about-15 μm after plating and about-10 μm after planarization in the circuit board manufactured by the prior art.
Example 1
Fig. 4A and 4B show the results of the thickness meter analysis after the circuit board manufactured according to the first embodiment of the present invention is electroplated and flattened. As can be seen from FIGS. 4A and 4B, the dishing values of the conductive layer after electroplating (corresponding to the structure shown in FIG. 1D) and the dishing values of the conductive layer after planarization (corresponding to the structure shown in FIG. 1E) are about +10 μm and about-3 μm for the circuit board manufactured according to the first embodiment of the present invention.
Example 2
Fig. 5A and 5B show the results of the thickness meter analysis after the circuit board manufactured according to the second embodiment of the present invention is electroplated and flattened. As can be seen from FIGS. 5A and 5B, the circuit board manufactured according to the second embodiment of the present invention has a dishing value of about +5 μm for the conductive layer after electroplating (corresponding to the structure shown in FIG. 2D), and a dishing value of about-4 μm for the conductive layer after planarization (corresponding to the structure shown in FIG. 2E).
As is apparent from the above results summarized in table 1 below, when comparing the circuit boards manufactured according to the prior art and the circuit boards manufactured according to the present invention, the difference in the thickness of the conductive layer after planarization is significantly smaller than that of the conductive layer according to the prior art, and the uniformity of the thickness of the conductive layer (copper layer) of the circuit boards manufactured according to the first and second embodiments of the present invention is greatly improved.
TABLE 1
Although the present invention has been described with reference to a few preferred embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (12)
1. A circuit board, comprising:
a substrate;
a metal layer on a surface of the substrate;
a conductive layer, located on the metal layer, including a first conductive layer and a second conductive layer; and
a plurality of through holes, including a dense region and a loose region, penetrating the conductive layer, the metal layer, and the substrate,
wherein the conductive layer has a flat upper surface, and an interface exists at the adjacent position of the first conductive layer and the second conductive layer;
wherein the first conductive layer and the second conductive layer are both located on the metal layer, the first conductive layer is located in the dense region of the plurality of through holes, and the second conductive layer is located in the loose region of the plurality of through holes; alternatively, the first and second electrodes may be,
the first conductive layer and the second conductive layer are both positioned on the metal layer, the first conductive layer is positioned in the loose area and the dense area of the through holes, the second conductive layer is positioned in the dense area of the through holes, and the second conductive layer covers part of the first conductive layer.
2. The circuit board of claim 1, wherein the first conductive layer and the second conductive layer can be composed of the same or different conductive materials.
3. The circuit board of claim 1, wherein the interface is a concave interface, and the cross-sectional profile of the first conductive layer is concave and the cross-sectional profile of the second conductive layer is convex.
4. The circuit board of claim 1, wherein the interface is a vertical interface.
5. A method of manufacturing a circuit board, comprising:
forming a metal layer on a surface of a substrate;
forming a plurality of through holes penetrating through the metal layer and the substrate, wherein the plurality of through holes comprise a dense area and a loose area;
performing a first electroplating to form a first conductive layer on the metal layer and in the plurality of through holes, wherein the first conductive layer comprises a recessed area corresponding to the dense area;
forming a shielding layer on the first conductive layer;
forming an opening in the shielding layer to expose the recessed region of the first conductive layer;
performing a second electroplating to form a second conductive layer in the opening to cover the first conductive layer;
removing the shielding layer;
forming a filler in the through holes; and
a planarization process is performed to remove a portion of the first conductive layer and a portion of the second conductive layer.
6. The method for manufacturing a circuit board according to claim 5, further comprising:
a seed layer is conformally formed on the metal layer and in the plurality of vias prior to the first electroplating.
7. The method according to claim 5, wherein the masking layer is a photoresist layer.
8. The method for manufacturing a circuit board according to claim 5, wherein the height of the recessed area decreases from two sides to the center.
9. A method of manufacturing a circuit board, comprising:
forming a metal layer on a surface of a substrate;
forming a plurality of through holes penetrating through the metal layer and the substrate, wherein the plurality of through holes comprise a dense area and a loose area;
forming a shielding layer on the metal layer;
forming an opening in the shielding layer to expose part of the metal layer and the dense region;
performing a first electroplating to form a first conductive layer in the opening;
removing the shielding layer;
performing second electroplating to form a second conductive layer covering the first conductive layer and the metal layer, wherein the second conductive layer is positioned in the through holes;
forming a filler in the through holes; and
a planarization process is performed to remove a portion of the first conductive layer and a portion of the second conductive layer.
10. The method for manufacturing a circuit board according to claim 9, further comprising:
before the shielding layer is formed on the metal layer, a seed layer is conformally formed on the metal layer and in the plurality of through holes.
11. The method of claim 9, wherein the masking layer is a photoresist layer.
12. The method according to claim 9, wherein a vertical interface exists between the first conductive layer and the second conductive layer after the planarization process.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW105136583A TWI605733B (en) | 2016-11-10 | 2016-11-10 | Printed circuit board and methods for forming the same |
| TW105136583 | 2016-11-10 |
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| Publication Number | Publication Date |
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| CN108076586A CN108076586A (en) | 2018-05-25 |
| CN108076586B true CN108076586B (en) | 2020-06-05 |
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| CN201611186918.5A Active CN108076586B (en) | 2016-11-10 | 2016-12-20 | Circuit board and method for manufacturing the same |
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|---|---|
| JP (1) | JP6573332B2 (en) |
| CN (1) | CN108076586B (en) |
| TW (1) | TWI605733B (en) |
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| CN110769617B (en) * | 2018-07-27 | 2020-12-29 | 北大方正集团有限公司 | Aperture compensation method and device in PCB |
| JP7502170B2 (en) | 2020-12-14 | 2024-06-18 | イビデン株式会社 | Method for manufacturing printed wiring board |
| JP7502173B2 (en) | 2020-12-21 | 2024-06-18 | イビデン株式会社 | Method for manufacturing printed wiring board |
| CN114980568A (en) * | 2021-02-20 | 2022-08-30 | 嘉联益电子(昆山)有限公司 | Method for manufacturing circuit board circuit structure with through hole and manufactured circuit board circuit structure with through hole |
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| JP2005311182A (en) * | 2004-04-23 | 2005-11-04 | Shinko Electric Ind Co Ltd | Board and semiconductor device |
| CN101278392A (en) * | 2005-12-27 | 2008-10-01 | 揖斐电株式会社 | Multilayer printed wiring board |
| CN101697666A (en) * | 2009-10-16 | 2010-04-21 | 深圳崇达多层线路板有限公司 | Circuit board plating device and method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05145221A (en) * | 1991-11-20 | 1993-06-11 | Matsushita Electric Ind Co Ltd | Manufacture of printed circuit board |
| TWI334750B (en) * | 2007-06-06 | 2010-12-11 | Unimicron Technology Corp | Circuit board and process thereof |
| TWI455954B (en) * | 2008-05-07 | 2014-10-11 | Taiyo Holdings Co Ltd | a thermosetting resin composition for hole filling, a combination unit of the composition and a photocurable thermosetting resin composition for forming a solder resist layer, and a printed circuit board |
| TWI626863B (en) * | 2015-04-30 | 2018-06-11 | Circuit board structure |
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2016
- 2016-11-10 TW TW105136583A patent/TWI605733B/en active
- 2016-12-20 CN CN201611186918.5A patent/CN108076586B/en active Active
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2017
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005311182A (en) * | 2004-04-23 | 2005-11-04 | Shinko Electric Ind Co Ltd | Board and semiconductor device |
| JP4291729B2 (en) * | 2004-04-23 | 2009-07-08 | 新光電気工業株式会社 | Substrate and semiconductor device |
| CN101278392A (en) * | 2005-12-27 | 2008-10-01 | 揖斐电株式会社 | Multilayer printed wiring board |
| CN101697666A (en) * | 2009-10-16 | 2010-04-21 | 深圳崇达多层线路板有限公司 | Circuit board plating device and method |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201818790A (en) | 2018-05-16 |
| TWI605733B (en) | 2017-11-11 |
| CN108076586A (en) | 2018-05-25 |
| JP6573332B2 (en) | 2019-09-11 |
| JP2018078273A (en) | 2018-05-17 |
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