KR20140048692A - Manufacturing methods of printed circuit board - Google Patents

Manufacturing methods of printed circuit board Download PDF

Info

Publication number
KR20140048692A
KR20140048692A KR1020120114944A KR20120114944A KR20140048692A KR 20140048692 A KR20140048692 A KR 20140048692A KR 1020120114944 A KR1020120114944 A KR 1020120114944A KR 20120114944 A KR20120114944 A KR 20120114944A KR 20140048692 A KR20140048692 A KR 20140048692A
Authority
KR
South Korea
Prior art keywords
hole
layer
resist layer
forming
post
Prior art date
Application number
KR1020120114944A
Other languages
Korean (ko)
Inventor
권칠우
Original Assignee
삼성전기주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 삼성전기주식회사 filed Critical 삼성전기주식회사
Priority to KR1020120114944A priority Critical patent/KR20140048692A/en
Publication of KR20140048692A publication Critical patent/KR20140048692A/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings
    • H05K3/285—Permanent coating compositions
    • H05K3/287—Photosensitive compositions
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4007—Surface contacts, e.g. bumps
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4673—Application methods or materials of intermediate insulating layers not specially adapted to any one of the previous methods of adding a circuit layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/099—Coating over pads, e.g. solder resist partly over pads

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

Forming a first resist layer having a first through hole on an upper surface of the carrier, a second through hole communicating with the first through hole on an upper surface of the first resist layer, and a third not communicating with the first through hole Forming a second resist layer having a through hole, forming a metal post in a first post hole including the first through hole and the second through hole, and a second post hole including the third through hole Forming a circuit pattern on an upper surface of the second resist layer, forming an insulating layer on an upper surface of the second resist layer, removing the carrier, and removing the first resist layer and the second resist layer Removing.

Description

MANUFACTURING METHODS OF PRINTED CIRCUIT BOARD

The present invention relates to a method of manufacturing a printed circuit board.

IC boards are used as mediators for mounting IC chips on electronic boards. There are wire bonding and flip chip bonding methods for connecting an IC substrate. However, according to the recent trend of higher performance of electronic products, a flip chip bonding method that has excellent electrical connection characteristics and can cope with more input / output is preferred. Flip chip bonding is a method of forming solder bumps on a substrate and connecting them through reflow or thermocompression.

In order to cope with miniaturization of a circuit and bump pitch, solder bumping technology is being researched, and research into bumping technology using copper posts (Cu post) is being actively conducted.

Background art of the present invention is disclosed in Republic of Korea Patent Publication No. 10-1138592 (2012.05.10).

The present invention solves the problem that the height of the metal post cannot be precisely controlled due to the plating deviation generated in the plating process for forming the metal post, and provides a method of manufacturing a printed circuit board capable of forming metal posts of various heights. There is a purpose.

According to an embodiment of the present invention, a method of manufacturing a printed circuit board may include forming a first resist layer having a first through hole on an upper surface of a carrier, and communicating the first through hole on an upper surface of the first resist layer. Forming a second resist layer having a second through hole and a third through hole not in communication with the first through hole, a first post hole including the first through hole and the second through hole, and the third through hole Forming a metal post in a second post hole including a through hole, forming a circuit pattern on an upper surface of the second resist layer, forming an insulating layer on an upper surface of the second resist layer, and forming the carrier And removing the first resist layer and the second resist layer.

The metal posts may have different heights so as to correspond to depths of the first post hole and the second post hole, respectively.

And forming a seed layer in the first post hole and the second post hole before forming the metal post, wherein the forming the metal post may be performed by electroplating based on the seed layer. The method may include filling a conductive material in the first post hole and the second post hole.

The method may further include forming a via hole in the insulating layer after forming the insulating layer on the top surface of the second resist layer and forming a build up layer on the top surface of the insulating layer.

The carrier may include an insulating resin layer and a copper foil layer formed on an upper surface of the insulating resin layer.

Removing the carrier may include removing the insulating resin layer from the copper foil layer and removing the copper foil layer from the first resist layer.

The method may further include forming a solder resist layer on the insulating layer to expose a portion of the circuit pattern and the metal post after removing the first resist layer and the second resist layer.

The present invention eliminates the need for a planarization process by forming metal posts having a uniform height, and also prevents a height variation that has been generated during the conventional planarization process, and has the effect of implementing metal posts of various heights.

1 is a cross-sectional view showing a printed circuit board manufactured by a method for manufacturing a printed circuit board according to an embodiment of the present invention.
2 to 10 are diagrams showing a method of manufacturing a printed circuit board according to an embodiment of the present invention in the order of processes.

BRIEF DESCRIPTION OF THE DRAWINGS The present invention is capable of various modifications and various embodiments, and specific embodiments are illustrated in the drawings and described in detail in the detailed description. It is to be understood, however, that the invention is not to be limited to the specific embodiments, but includes all modifications, equivalents, and alternatives falling within the spirit and scope of the invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

The terms first, second, etc. may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In the present invention, the term "comprises" or "having ", etc. is intended to specify that there is a feature, number, step, operation, element, But do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof.

Hereinafter, a printed circuit board manufactured by a method of manufacturing a printed circuit board according to an embodiment of the present invention will be described with reference to the accompanying FIG. 1.

1 is a view showing a printed circuit board manufactured by a method of manufacturing a printed circuit board according to an embodiment of the present invention.

Referring to FIG. 1, a printed circuit board 10 manufactured by a method of manufacturing a printed circuit board according to an exemplary embodiment of the present invention includes an insulating layer 100.

The insulating layer 100 may be made of a composite polymer resin commonly used as an interlayer insulating material.

The insulating layer 100 includes metal posts 110a and 110b and a circuit pattern 120.

The metal posts 110a and 110b protrude upward from the insulating layer 100 to electrically connect the electronic component to be mounted on the printed circuit board 10 and the circuit pattern 120.

The metal posts 110a and 110b have a constant post shape in which the upper diameter and the lower diameter are constant, and the constant here does not mean that they are exactly the same mathematically, but a slight change in diameter due to processing errors occurring in the substrate manufacturing process. It is used to mean.

The metal posts 110a and 110b may have various heights depending on the required height. For example, the height of the metal post 110a corresponds to twice the height of the metal post 110b. As described later, the heights of the metal posts 110a and 110b are determined according to the depths of the first post hole 46 and the second post hole 48 formed in the manufacturing process of the printed circuit board, and the first post hole. The depth of the 46 is equal to the sum of the depths of the first through hole 32 and the second through hole 42 included in the first post hole 46 and the depth of the second post hole 48. Is equal to the depth of the third through hole 44 included in the second post hole 48. That is, the height of the metal post may be variously formed according to the number of through holes included in the post hole in which the metal post is formed. Although not shown in FIG. 1, the number of through holes included in the post hole by additionally stacking a resist layer is illustrated. It will be appreciated that by increasing the width, metal posts of various heights can be formed.

The metal posts 110a and 110b may be copper posts made of copper.

The circuit pattern 120 is buried in the upper surface of the insulating layer 100 to perform the wiring function of the electric circuit to be implemented by the printed circuit board 10, and to the metal post (110a, 110b) Is connected.

A solder resist layer 300 may be formed on an upper surface of the insulating layer 100 to expose a portion of the circuit pattern, for example, a connection pad (not shown) and the metal posts 110a and 110b.

The printed circuit board 10 may include a build up layer 200 which is built up on the bottom surface of the insulating layer 100. In this case, the insulating layer 100 is referred to as an upper circuit layer, and the via layer 130 is formed in the insulating layer 100 to electrically connect the circuit pattern 130 and the build-up layer 200.

The build-up layer 200 includes a lower circuit layer electrically connected to the upper circuit layer through the via hole 130, and although not shown in FIG. 1, at least one internal circuit between the upper circuit layer and the lower circuit layer. Circuit layer may be further included.

The build up layer 200 may be formed, for example, in the order of seed plating, dry film stacking, wiring pattern formation, electroplating, dry film peeling, interlayer insulating material or preflag stacking, and the like. The detailed description thereof will be omitted.

Hereinafter, a method of manufacturing a printed circuit board according to an exemplary embodiment of the present invention will be described with reference to FIGS. 2 to 10. In the following description, the vertical direction is indicated based on the referenced drawings. In the present embodiment, for convenience of description, the manufacturing process of the printed circuit board is performed only on one side of the carrier. This may be done.

2 to 10 are diagrams showing a method of manufacturing a printed circuit board according to an embodiment of the present invention in the order of processes.

First, in order to prevent the printed circuit board from bending during the manufacturing process of the printed circuit board, a carrier 20 that performs a support function is prepared.

Referring to FIG. 2, the carrier 20 may be formed by stacking a copper foil layer 24 on an upper surface of the insulating resin layer 22. As will be described later, the copper foil layer 24 may be used as the basis of the electroplating when the electroplating is performed to form the metal posts 110a and 110b.

Next, the first resist layer 30 having the first through hole 32 is formed on the carrier 20.

The first resist layer 30 may be formed of a dry film of a photosensitive material.

Referring to FIG. 3, the first resist layer 30 is laminated or coated on the carrier 20, and a pattern of the first through hole 32 is formed on the top surface of the first resist layer 30. The first through hole 32 may be processed by covering the light blocking film (not shown) and exposing and developing the same.

Next, a second through hole 42 communicating with the first through hole 32 and a third through hole not communicating with the first through hole 32 on the upper surface of the first resist layer 30. A second resist layer 40 having 44 is formed.

The second resist layer 40 may be formed of a dry film of a photosensitive material.

Referring to FIG. 4, the second resist layer 40 is laminated or coated on an upper surface of the first dry film 30, and the second through hole 42 and the upper surface of the second resist layer 40 are formed. The second through hole 42 and the third through hole 44 may be processed by covering the light blocking film (not shown) on which the pattern of the third through hole 44 is formed and exposing and developing the third through hole 44. In this case, the hole formed by the first through hole 32 and the second through hole 42 communicating with the first through hole 32 is referred to as a first post hole 46 and the third through hole ( The hole made of 44 is referred to as a second post hole 48.

Although not shown in FIG. 4, an additional resist layer having a through hole may be formed on the top surface of the second resist layer 40 to form post holes having various heights.

Next, metal posts 110a and 110b are formed in the first post hole 46 and the second post hole 48.

Referring to FIG. 5, the method may further include forming a seed layer 50 in the first post hole 46 and the second post hole 48 before forming the metal posts 110a and 110b. The metal posts 110a and 110b may be electroplated based on the seed layer 50 to fill a conductive material in the first post hole 46 and the second post hole 48. Can be formed.

The seed layer 50 may be formed by a sputtering process.

Next, the circuit pattern 120 is formed on the upper surface of the second resist layer 40.

The circuit pattern 120 may be formed through a development and an exposure process after laminating or applying a dry film on the upper surface of the second resist layer 40 and covering the mast film thereon, without being limited thereto. It can be formed by the process.

Next, the insulating layer 100 is laminated on the upper surface of the second resist layer 40.

Referring to FIG. 6, an insulating layer 100 may be formed on an upper surface of the second resist layer 40, and a build-up layer 200 may be formed on an upper surface of the insulating layer 100. In the case of forming the build-up layer 200, a via hole 130 is formed in the insulating layer 100.

Next, the carrier 20 is separated from the first resist layer 30.

Referring to FIGS. 7 and 8, the carrier 20 may include an insulating resin layer 22 and a copper foil layer 24 formed on an upper surface of the insulating resin layer, and may be insulated from the copper foil layer 24. The carrier 20 can be separated from the first resist layer 30 by removing the resin layer 22 and removing the copper foil layer 24 from the first resist layer 30.

The copper foil layer 24 may be used as a seed layer which is a base of electroplating in the process of forming the metal post 110a.

Next, the first resist layer 30 and the second resist layer 40 are separated from the insulating layer 100.

Referring to FIG. 9, the first resist layer 30 and the second resist layer 40 may be removed from the insulating layer 100 using a stripping solution (not shown).

Next, a solder resist layer 300 may be formed on the insulating layer 100 so that a part of the circuit pattern 120 and the metal posts 110a and 110b are exposed.

Referring to FIG. 10, after the solder resist layer 300 is formed, a portion of the circuit pattern 120 and the metal posts 110a and 110b exposed to the outside may be prevented from being oxidized in air and to improve conductivity. It can be surface treated with OSP.

It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the appended claims and their equivalents. And such changes are, of course, within the scope of the claims.

10: printed circuit board
20: carrier
22: insulating resin layer
24: copper foil layer
30: first resist layer
32: first through hole
40: second resist layer
42: second through hole
44: third through hole
46: first post hole
48: second post hole
50: seed layer
100: insulating layer
110a, 110b: metal post
120: circuit pattern
130: Via Hole
200: build up floor
300: solder resist layer

Claims (7)

Forming a first resist layer having a first through hole on an upper surface of the carrier;
Forming a second resist layer having a second through hole communicating with the first through hole and a third through hole not communicating with the first through hole on an upper surface of the first resist layer;
Forming a metal post in the first post hole including the first through hole and the second through hole and the second post hole including the third through hole;
Forming a circuit pattern on an upper surface of the second resist layer;
Forming an insulating layer on an upper surface of the second resist layer;
Removing the carrier; And
Removing the first resist layer and the second resist layer.
The method of claim 1,
The metal post has a different height so as to correspond to the depth of the first post hole and the second post hole, respectively.
The method of claim 1,
Prior to forming the metal post,
Forming a seed layer in the first post hole and the second post hole;
Forming the metal post,
And filling a conductive material into the first post hole and the second post hole by performing electroplating based on the seed layer.
The method of claim 1,
After forming the insulating layer on the upper surface of the second resist layer,
Forming a via hole in the insulating layer; And
Forming a build-up layer on the upper surface of the insulating layer further comprising the step of manufacturing a printed circuit board.
The method of claim 1,
The carrier
Insulating resin layer; And
And a copper foil layer formed on the upper surface of the insulating resin layer.
6. The method of claim 5,
Removing the carrier,
Removing the insulating resin layer from the copper foil layer; And
And removing the copper foil layer from the first resist layer.
The method of claim 1,
After removing the first resist layer and the second resist layer,
And forming a solder resist layer on the insulating layer to expose a portion of the circuit pattern and the metal posts.
KR1020120114944A 2012-10-16 2012-10-16 Manufacturing methods of printed circuit board KR20140048692A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020120114944A KR20140048692A (en) 2012-10-16 2012-10-16 Manufacturing methods of printed circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020120114944A KR20140048692A (en) 2012-10-16 2012-10-16 Manufacturing methods of printed circuit board

Publications (1)

Publication Number Publication Date
KR20140048692A true KR20140048692A (en) 2014-04-24

Family

ID=50654658

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020120114944A KR20140048692A (en) 2012-10-16 2012-10-16 Manufacturing methods of printed circuit board

Country Status (1)

Country Link
KR (1) KR20140048692A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11569158B2 (en) 2020-08-19 2023-01-31 Samsung Electronics Co., Ltd. Semiconductor package

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11569158B2 (en) 2020-08-19 2023-01-31 Samsung Electronics Co., Ltd. Semiconductor package

Similar Documents

Publication Publication Date Title
US20130008705A1 (en) Coreless package substrate and fabrication method thereof
US9917025B2 (en) Printed wiring board and method for manufacturing printed wiring board
US8785789B2 (en) Printed circuit board and method for manufacturing the same
KR101516072B1 (en) Semiconductor Package and Method of Manufacturing The Same
US9247654B2 (en) Carrier substrate and manufacturing method thereof
US20150098204A1 (en) Printed wiring board, method for manufacturing printed wiring board and package-on-package
KR100966336B1 (en) High density substrate and manufacturing method thereof
KR20060061227A (en) Method of manufacturing a circuit substrate and method of manufacturing a structure for mounting electronic parts
KR101204233B1 (en) A printed circuit board comprising embeded electronic component within and a method for manufacturing
US9793200B2 (en) Printed wiring board
TWI384925B (en) Structure of embedded-trace substrate and method of manufacturing the same
KR20150064976A (en) Printed circuit board and manufacturing method thereof
KR102194718B1 (en) Embedded board and method of manufacturing the same
JP2016100599A (en) Printed circuit board and method of manufacturing the same, and electronic component module
JP5989329B2 (en) Method for manufacturing printed circuit board
US9491871B2 (en) Carrier substrate
JP6699043B2 (en) Printed circuit board, manufacturing method thereof, and electronic component module
US20150156882A1 (en) Printed circuit board, manufacturing method thereof, and semiconductor package
KR102207272B1 (en) Printed circuit board and method of manufacturing the same, and electronic component module
US20160021749A1 (en) Package board, method of manufacturing the same and stack type package using the same
JP2013058775A (en) Semiconductor package substrate and method of manufacturing the same
EP2071622A2 (en) Package for semiconductor device and method of manufacturing the same
KR20160084666A (en) Printed circuit board, semiconductor package and method of manufacturing the same
KR20140048692A (en) Manufacturing methods of printed circuit board
KR20130057803A (en) Printed circuit board for semiconductor package and method for the same

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E601 Decision to refuse application