CN108076585A - Board structure of circuit and its manufacturing method - Google Patents
Board structure of circuit and its manufacturing method Download PDFInfo
- Publication number
- CN108076585A CN108076585A CN201611014475.1A CN201611014475A CN108076585A CN 108076585 A CN108076585 A CN 108076585A CN 201611014475 A CN201611014475 A CN 201611014475A CN 108076585 A CN108076585 A CN 108076585A
- Authority
- CN
- China
- Prior art keywords
- layer
- circuit
- plate face
- board structure
- metal pad
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4007—Surface contacts, e.g. bumps
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/05—Patterning and lithography; Masks; Details of resist
- H05K2203/0502—Patterning and lithography
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
The present invention discloses a kind of board structure of circuit and its manufacturing method, and wherein board structure of circuit includes substrate, circuit and independent metal pad.The substrate includes the first plate face and the second plate face positioned at opposite side.The circuit is arranged at the first plate face of substrate with independent metal pad, and the independent metal pad is set in distance with circuit and mutually electrically isolates.Wherein, the independent metal pad includes the joint part for being arranged at the first plate face and the hard gold layer being formed on above-mentioned joint part.The present invention provides a kind of board structure of circuit with independent metal pad as a result,.In addition, the present invention separately provides a kind of board structure of circuit manufacturing method.
Description
Technical field
The present invention relates to a kind of circuit board more particularly to a kind of board structure of circuit and its manufacturer with independent metal pad
Method.
Background technology
Available circuit harden structure substantially follows Fig. 1 to be illustrated to step shown in Fig. 3 when golden finger is shaped
It is as follows.Such as Fig. 1, metal layer 2a is formed on substrate 1a, and metal layer 2a is included and is treated gold-plated area 21a and non-gold-plated area 22a,
And positioned at the above-mentioned non-gold-plated area 22a for treating gold-plated area 21a both sides covered with soldermask layer 3a.Such as Fig. 2, in the to be plated of metal layer 2a
Layer gold 4a is formed on golden area 21a, and above-mentioned layer gold 4a includes mac function 41a and invalid block 42a.Such as Fig. 3, work(is removed
Partial invalidity block 42a and non-gold-plated area 22a on the upside of energy block 41a.
According to upper described, available circuit harden structure 100a is also left connected in the two opposite sides of the mac function 41a of layer gold 4a
The invalid block 42a (such as Fig. 3) connect, and available circuit harden structure 100a must also be removed in the step of Fig. 3 and completed to plate
The block of gold.Therefore, available circuit harden structure 100a obviously generates many unnecessary noble metals (such as：Gold) waste.
Then, inventors believe that drawbacks described above can improve, spy concentrates on studies and coordinates the utilization of the principles of science, carries finally
Go out a kind of design rationally and be effectively improved the present invention of drawbacks described above.
The content of the invention
It is an object of the invention to provide a kind of board structure of circuit and its manufacturing method, for effectively improving available circuit
The issuable missing of harden structure institute.
In order to achieve the above object, the present invention discloses a kind of board structure of circuit, including：One substrate includes positioned at opposite side
One first plate face and one second plate face；One circuit is arranged at first plate face of the substrate；And an independent metal pad,
Be arranged at first plate face of the substrate, the independent metal pad be set in distance with the circuit and mutually electrically every
From；Wherein, the independent metal pad includes the joint part for being arranged at first plate face and is formed on the joint part
A hard gold layer.
Preferably, the joint part include the layers of copper that is arranged at first plate face and the connection layers of copper with it is described
One nickel layer of hard gold layer, the layers of copper have identical height with the circuit.
Preferably, the layers of copper side wall is uncoated in the hard gold layer, and the width of the layers of copper is from neighbouring described the
One plate face is directed away from first plate face and gradually reduces.
Preferably, the outside left of the hard gold layer protrudes out the layers of copper.
Preferably, the board structure of circuit further comprises there is the soldermask layer for being arranged at first plate face, described anti-
Layer is around on the outside of the independent metal pad, and the circuit is at least partly embedded in the soldermask layer, and the independence
Metal gasket is not in contact in the soldermask layer.
Preferably, the hard gold layer compared to first plate face height not less than the soldermask layer compared to described the
The height of one plate face.
The embodiment of the present invention also discloses a kind of board structure of circuit manufacturing method, including：One substrate is provided and is arranged at described
A conductive layer on substrate；Wherein, the substrate includes one first plate face and one second plate face positioned at opposite side, described to lead
Electric layer is arranged at first plate face；A bond layer is formed on a predetermined block of the conductive layer and is arranged at the key
Tie a hard gold layer of layer；And by the Conductive Layer Etch into the predetermined block and be separated from each other with the predetermined block one
Circuit；Wherein, the predetermined block, the bond layer and the hard gold layer are collectively referred to as an independent metal pad.
Preferably, a pattern layer is provided on the conductive layer；Wherein, the pattern layer has a figure hole, with naked
Reveal the predetermined block of the conductive layer；Sequentially shaped on the predetermined block in the figure hole it is described bond layer with
The hard gold layer then removes the pattern layer.
Preferably, a shielding layer is formed on a scheduled circuit block of the hard gold layer and the conductive layer, and etched
The conductive layer position not covered by the shielding layer, so that the conductive layer is configured to the predetermined block and the line
Road then removes the shielding layer.
Preferably, the method for manufacturing circuit board further comprises：A soldermask layer is formed in first plate face, and makes institute
Soldermask layer is stated around on the outside of the independent metal pad and at least part of the circuit is embedding in the inner.
In conclusion board structure of circuit and its manufacturing method disclosed in the embodiment of the present invention, can need not remove any hard
Layer gold and form independent metal pad, and the independent metal pad will not connect any invalid block, to avoid board structure of circuit
Generate unnecessary noble metal (such as：Gold) waste.
Furthermore since the board structure of circuit of the present embodiment is during independent metal pad is formed, without as existing with
Non- gold-plated area is as the guiding for treating gold-plated area, so any position that the board structure of circuit of the present embodiment can be on substrate is formed
There is independent metal pad, and then make external form, size, position and the density of the independent metal pad on substrate, be less affected by limitation,
For being effectively facilitated the development of board structure of circuit.
For that can be further understood that the feature of the present invention and technology contents, please refer to the following detailed descriptions related to the present invention
With attached drawing, but these explanations are only used for illustrating the present invention rather than make any limitation to protection scope of the present invention with attached drawing.
Description of the drawings
Fig. 1 is the manufacturing step (one) of available circuit harden structure；
Fig. 2 is the manufacturing step (two) of available circuit harden structure；
Fig. 3 is the manufacturing step (three) of available circuit harden structure；
Fig. 4 A are the schematic diagram of the step S110 of board structure of circuit manufacturing method of the present invention；
Fig. 4 B are schematic cross-sectional views of Fig. 4 A along IVB-IVB hatching lines；
Fig. 5 A are the schematic diagram of the step S120 and step S130 of board structure of circuit manufacturing method of the present invention；
Fig. 5 B are schematic cross-sectional views of Fig. 5 A along VB-VB hatching lines；
Fig. 6 A are the schematic diagram of the step S140 of board structure of circuit manufacturing method of the present invention；
Fig. 6 B are schematic cross-sectional views of Fig. 6 A along VIB-VIB hatching lines；
Fig. 7 A are the schematic diagram of the step S150 of board structure of circuit manufacturing method of the present invention；
Fig. 7 B are schematic cross-sectional views of Fig. 7 A along II B-V of V, II B hatching lines；
Fig. 8 A are the schematic diagram of the step S160 of board structure of circuit manufacturing method of the present invention；
Fig. 8 B are schematic cross-sectional views of Fig. 8 A along III B-V of V, III B hatching lines；
Fig. 8 C are the close-up schematic view at the III C positions of V in Fig. 8 B.
Symbol description
[prior art]
100a：Available circuit harden structure
1a：Substrate
2a：Metal layer
21a：Treat gold-plated area
22a：Non- gold-plated area
3a：Soldermask layer
4a：Layer gold
41a：Mac function
42a：Invalid block
[embodiment of the present invention]
100：Board structure of circuit
1：Substrate
11：First plate face
12：Second plate face
13：Perforation
2’：Scheduled circuit block
2：Circuit
3：Independent metal pad
31’：Predetermined block
31：Layers of copper
32：It is bonded layer (nickel layer)
33：Hard gold layer
34：Joint part
4：Soldermask layer
41：Perforate
10：Conductive layer
20：Pattern layer
201：Figure hole
30：Shielding layer
H1、H2：Highly
Specific embodiment
Fig. 4 A to Fig. 8 C are referred to, is the embodiment of the present invention, need to first illustrate, mentioned by the present embodiment respective figure
Correlated measure and external form, only be used for specifically describe embodiments of the present invention, in order to understand present disclosure rather than
For limiting to protection scope of the present invention.
The present embodiment provides a kind of board structure of circuit 100 and its manufacturing method, foregoing circuit harden structure 100 is, for example, to apply
In servomechanism or semiconductor test etc., but the present invention is not limited.Furthermore the present embodiment for ease of understanding, it is following to incite somebody to action
Each step of first general description board structure of circuit manufacturing method is (such as：Step S110~step S160), then followed by introduction
The construction feature of the board structure of circuit 100.Wherein, when illustrating each step of board structure of circuit manufacturing method, attached drawing is only
Using partial block as signal, this is not to limit to the quantity of the present invention and practical range.
Step S110：It refers to shown in Fig. 4 A and Fig. 4 B, a substrate 1 and the conduction being arranged on the substrate 1 is provided
Layer 10.Wherein, the substrate 1 includes one first plate face 11 (1 top surface of substrate in such as Fig. 4 B) positioned at opposite side and one the
Two plate faces 12 (1 bottom surface of substrate in such as Fig. 4 B), and the conductive layer 10 is arranged at the first plate face 11 of aforesaid substrate 1.
It further says, the conductive layer 10 of the present embodiment is entire first plate face that substrate is formed in by copper plating mode
11, but the present invention is not only restricted to this.For example, in the embodiment not illustrated one, the conductive layer 10 can also be passed through
Copper foil pressing mode forms in the first plate face 11 of substrate 1.
Furthermore the substrate 1 of the present embodiment can also be formed with from first plate face 11 and be through to the more of the second plate face 12
A perforation 13, and the conductive material (not shown) for being connected to the conductive layer 10 is equipped in above-mentioned each perforation 13,
But the present invention is not limited.
Step S120：It refers to shown in Fig. 5 A and Fig. 5 B, a pattern layer 20 is provided on the conductive layer 10.Wherein,
The pattern layer 20 has a figure hole 201, with a predetermined block 31 ' of the exposed conductive layer 10.
It further says, the pattern layer 20 of the present embodiment is that dry film is first attached on conductive layer 10, then by above-mentioned dry film
The figure hole 201 with given shape is formed in a manner of exposure imaging, for figure hole 201 to be enable to expose needed for designer
The predetermined block 31 ' of given shape.Wherein, in the forming process of above-mentioned pattern layer 20, preferable environmental condition is 20 DEG C of temperature
~24 DEG C, humidity 50%~60%.Therefore, used by the present embodiment step S120 can according to the different demands of designer,
And realize variously-shaped predetermined block 31 ', it is limited for the strip of the existing golden finger of escape.
Step S130：Refer to shown in Fig. 5 A and Fig. 5 B, on the predetermined block 31 ' in the figure hole 201 sequentially into
Shape one is bonded 32 and one hard gold layer of layer (hard gold layer) 33, further says, in the predetermined block of the conductive layer 10
Above-mentioned bond layer 32 is formed with such as plating mode deposition on 31 ' and is arranged at the hard gold layer 33 of bond layer 32；Then remove
The pattern layer 20.
Wherein, the bond layer 32 and hard gold layer 33 are substantially to fill up above-mentioned figure hole 201 in this present embodiment, that is,
Above-mentioned 33 outer surface of hard gold layer is substantially flush in the outer surface of pattern layer 20, but the present invention is not only restricted to this.
Furthermore since the hard gold layer 33 and material are difficult to be fixedly combined between the conductive layer 10 of copper, so this reality
It is by being bonded layer 32 hard gold layer 33 to be enable to be firmly adhered on conductive layer 10 to apply example.In more detail, the present embodiment
Bond layer 32 for nickel layer 32, and the nickel layer 32 can generate by force with hard gold layer 33 and material for the conductive layer 10 of copper respectively
Degree preferably bond.
Step S140：It refers to shown in Fig. 6 A and Fig. 6 B, in the hard gold layer 33 and a scheduled circuit area of conductive layer 10
A shielding layer 30 is formed on block 2 '.That is, designer can cover the pre- of conductive layer 10 by the shielding layer 30 of specific pattern
Alignment road block 2 ', to shape required line pattern.Wherein, above-mentioned scheduled circuit block 2 ' is to lead with predetermined block 31 '
Two positions being separated from each other in electric layer 10, and the scheduled circuit block 2 ' of the present embodiment can be arranged at aforesaid substrate 1 and set
On the position for having perforation 13, but not limited to this.
It further says, the shielding layer 30 of the present embodiment is first to attach dry film in hard gold layer 33 and conductive layer 10, then
Dry film on conductive layer 10 is formed into the shielding layer 30 with given shape in a manner of exposure imaging, for enabling shielding layer 30
The scheduled circuit block 2 ' of given shape needed for covering design person.Wherein, in the forming process of above-mentioned shielding layer 30, preferably
Environmental condition is 20 DEG C~24 DEG C of temperature, humidity 50%~60%.Therefore, step S140 can foundation used by the present embodiment
The different demands of designer, and realize variously-shaped scheduled circuit block 2 '.
Step S150：It refers to shown in Fig. 7 A and Fig. 7 B, the conductive layer 10 covered by etching above-mentioned not shielded layer 30
Position, so that the conductive layer 10 is configured to (or leaving) layers of copper 31 (i.e. predetermined block 31 ') and at least a circuit 2 is (i.e. predetermined
Circuit block 2 '), then remove the shielding layer 30.That is, by the conductive layer 10 be etched into layers of copper 31 and with it is above-mentioned
At least circuit 2 that layers of copper 31 is separated from each other.Above-mentioned layers of copper 31 (i.e. predetermined block 31 '), bond layer 32 and hard gold layer 33 are in this
An independent metal pad 3 is collectively referred to as in embodiment.
Wherein, it is above-mentioned " etching " it is to be implemented in a manner of chemical etching in this present embodiment, and above-mentioned chemical etching is preferable
It is the etching solution that will not corrode hard gold layer 33 used, the hard gold layer 33 for being beneficial to independent metal pad 3 is able to maintain that designer
Predetermined external form, but the present invention is not only restricted to this.
Furthermore the hard gold layer 33 of the independent metal pad 3 is suitable for contact and connects in this present embodiment, is touched for passing through
It touches outer member and forms connection, and then apply in servomechanism or semiconductor test etc., but the present invention is not limited.
Step S160：It refers to shown in Fig. 8 A and Fig. 8 B, a soldermask layer 4 is formed in the first plate face 11 of the substrate 1, and
Make the soldermask layer 4 around 3 outside of the independent metal pad and at least part of the circuit 2 is embedding in the inner.Into one
Say that the soldermask layer 4 can be equipped at least perforate 41 for exposed portion circuit 2, so that above-mentioned reveal via perforate 41 in step ground
2 position of circuit gone out can connect (such as：Welding or grafting etc.) in an outer member.
Furthermore the soldermask layer 4 during shaping, preferably soldermask layer 4 not in contact in independent metal pad 3, and
The hard gold layer 33 is not less than height of the soldermask layer 4 compared to the first plate face 11 compared to the height H1 of the first plate face 11
H2, but the present invention is not only restricted to this.
Accordingly, after via implementation above-mentioned steps S110~S160, you can the board structure of circuit of the present embodiment is completed in manufacture
100, but above-mentioned each step S110~S160 can be replaced with reasonable manner, changed or substituted in practice, without
It is contained to be confined to the present embodiment.For example, the first plate face 11 of the substrate 1 and the second plate face 12 can all be formed with independence
One of 11 and second plate face 12 of metal gasket 3 or above-mentioned first plate face is formed with independent metal pad 3.
Furthermore the present embodiment will then illustrate the board structure of circuit completed via implementation steps S110~S160 in following
100 construction feature, but the board structure of circuit 100 of the present invention is not limited to be completed with step S110~S160.
Fig. 8 A to Fig. 8 C are referred to, the board structure of circuit 100 includes a substrate 1, is arranged at the substrate 1 and mutually divides
From a circuit 2 and an independent metal pad 3 and the soldermask layer 4 for being arranged at the substrate 1.Wherein, the substrate 1 includes
Positioned at one first plate face 11 of opposite side and one second plate face 12, and above-mentioned circuit 2, independent metal pad 3 and soldermask layer 4 are all
It is arranged at the first plate face 11 of substrate 1.
Furthermore the independent metal pad 3 is set in distance with circuit 2 and mutually electrically isolates, and the independent metal
Pad 3 includes the hard gold layer 33 for being arranged at a joint part 34 of above-mentioned first plate face 11 and being formed on joint part 34.
In more detail, the joint part 34 includes in this present embodiment is arranged at 1 first plate face 11 of substrate
One nickel layer 32 of one layers of copper 31 and the above-mentioned layers of copper 31 of connection and hard gold layer 33, and the layers of copper 31 in the present embodiment is with circuit 2
It is manufactured and with identical height by identical conductive layer 10.It should be noted that though the joint part 34 of the present embodiment be with
Exemplified by layers of copper 31 and nickel layer 32, but the joint part 34 of the present invention is not excluded for substituting above-mentioned layers of copper 31 and nickel with other constructions or material
Layer 32.
It further says, 31 side wall of layers of copper is uncoated in the hard gold layer 33 and nickel layer 32, and the width of layers of copper 31
Degree is directed away from the first plate face 11 (direction from bottom to top in such as Fig. 8 B) from neighbouring first plate face 11 and gradually reduces.It is described
Hard gold layer 33 and the width of nickel layer 32 are roughly equal, and the hard gold layer 33 and the outside left of nickel layer 32 protrude out above-mentioned copper
Layer 3, and the hard gold layer 33 is not less than (such as compared to the height H1 of the first plate face 11：More than) soldermask layer 4 is compared to
The height H2 of one plate face 11.
In addition, the soldermask layer 4 is around the outside of independent metal pad 3, and 2 at least part of the circuit be embedded in it is described anti-
In layer 4.Wherein, the independent metal pad 3 is preferably not in contact in soldermask layer 4.
In conclusion board structure of circuit disclosed in the embodiment of the present invention and its manufacturing method, can need not remove any hard gold
Layer 33 and form independent metal pad 3, and the independent metal pad 3 will not connect any invalid block, hardened to avoid circuit
Structure 100 generates unnecessary noble metal waste.
Furthermore since the board structure of circuit 100 of the present embodiment is during independent metal pad 3 is formed, without such as existing
As using non-gold-plated area as the guiding (such as Fig. 1) for treating gold-plated area, so the board structure of circuit 100 of the present embodiment can be in substrate 1
On any position be formed with independent metal pad 3, and then make the external form of the independent metal pad 3 on substrate 1, size, position and close
Degree, is less affected by limitation, for being effectively facilitated the development of board structure of circuit 100.
The foregoing is merely the preferred possible embodiments of the present invention, are not used for limiting to protection scope of the present invention, it is all according to
The equivalent changes and modifications that the claims in the present invention are done should all belong to the protection domain of claims of the present invention.
Claims (10)
1. a kind of board structure of circuit, including：
Substrate includes the first plate face and the second plate face positioned at opposite side；
Circuit is arranged at first plate face of the substrate；And
Independent metal pad, is arranged at first plate face of the substrate, and the independent metal pad is set with the circuit in interval
It puts and mutually electrically isolates；Wherein, the independent metal pad includes the joint part for being arranged at first plate face and formation
In the hard gold layer on the joint part.
2. board structure of circuit as described in claim 1, wherein, the joint part, which includes, is arranged at the one of first plate face
One nickel layer of layers of copper and the connection layers of copper and the hard gold layer, the layers of copper have identical height with the circuit.
3. board structure of circuit as claimed in claim 2, wherein, the layers of copper side wall is uncoated in the hard gold layer, and institute
It states the width of layers of copper and is directed away from first plate face from neighbouring first plate face and gradually reduce.
4. board structure of circuit as claimed in claim 3, wherein, the outside left of the hard gold layer protrudes out the layers of copper.
5. board structure of circuit according to any one of claims 1 to 4 further comprises being arranged at first plate face
A soldermask layer, the soldermask layer around on the outside of the independent metal pad, and the circuit be at least partly embedded in it is described
Soldermask layer, and the independent metal pad is not in contact in the soldermask layer.
6. board structure of circuit as claimed in claim 5, wherein, the hard gold layer is not small compared to the height of first plate face
In height of the soldermask layer compared to first plate face.
7. a kind of board structure of circuit manufacturing method, including：
One substrate and the conductive layer being arranged on the substrate are provided；Wherein, the substrate includes one positioned at opposite side
First plate face and one second plate face, the conductive layer are arranged at first plate face；
A bond layer is formed on a predetermined block of the conductive layer and is arranged at a hard gold layer of the bond layer；And
By the Conductive Layer Etch into the predetermined block and the circuit being separated from each other with the predetermined block；Wherein, it is described
Predetermined block, the bond layer and the hard gold layer are collectively referred to as an independent metal pad.
8. board structure of circuit manufacturing method as claimed in claim 7, wherein, a pattern layer is provided on the conductive layer；
Wherein, the pattern layer has a figure hole, with the predetermined block of the exposed conductive layer；Institute in the figure hole
It states and the bond layer and the hard gold layer is sequentially shaped on predetermined block, then remove the pattern layer.
9. board structure of circuit manufacturing method as claimed in claim 7, wherein, one in the hard gold layer and the conductive layer is pre-
A shielding layer is formed on the block of alignment road, and etches the conductive layer position not covered by the shielding layer, so that described
Conductive layer is configured to the predetermined block and the circuit, then removes the shielding layer.
10. the board structure of circuit manufacturing method as any one of claim 7 to 9, further comprises：Described first
Plate face forms a soldermask layer, and makes the soldermask layer around on the outside of the independent metal pad and by least part of the circuit
It is embedding in the inner.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611014475.1A CN108076585A (en) | 2016-11-18 | 2016-11-18 | Board structure of circuit and its manufacturing method |
| CN202110440870.0A CN113115513A (en) | 2016-11-18 | 2016-11-18 | Circuit board structure and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611014475.1A CN108076585A (en) | 2016-11-18 | 2016-11-18 | Board structure of circuit and its manufacturing method |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110440870.0A Division CN113115513A (en) | 2016-11-18 | 2016-11-18 | Circuit board structure and manufacturing method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN108076585A true CN108076585A (en) | 2018-05-25 |
Family
ID=62160060
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201611014475.1A Pending CN108076585A (en) | 2016-11-18 | 2016-11-18 | Board structure of circuit and its manufacturing method |
| CN202110440870.0A Pending CN113115513A (en) | 2016-11-18 | 2016-11-18 | Circuit board structure and manufacturing method thereof |
Family Applications After (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110440870.0A Pending CN113115513A (en) | 2016-11-18 | 2016-11-18 | Circuit board structure and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (2) | CN108076585A (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101699940A (en) * | 2009-11-10 | 2010-04-28 | 广州兴森快捷电路科技有限公司 | Manufacture method of golden finger printed board |
| CN102638945A (en) * | 2012-03-21 | 2012-08-15 | 深圳崇达多层线路板有限公司 | Method for producing goldfinger via twice electroplating |
| JP5163547B2 (en) * | 2009-03-09 | 2013-03-13 | 日本電気株式会社 | Card edge terminal manufacturing method for printed wiring board |
| CN103233250A (en) * | 2013-04-28 | 2013-08-07 | 胜宏科技（惠州）股份有限公司 | Method for electroplating goldfinger with thick gold layer |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4444435B2 (en) * | 2000-03-06 | 2010-03-31 | ソニーケミカル＆インフォメーションデバイス株式会社 | Printed wiring board and method for manufacturing printed wiring board |
| CN101145552A (en) * | 2006-09-12 | 2008-03-19 | 日月光半导体制造股份有限公司 | Integrated circuit package substrate and making method |
-
2016
- 2016-11-18 CN CN201611014475.1A patent/CN108076585A/en active Pending
- 2016-11-18 CN CN202110440870.0A patent/CN113115513A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5163547B2 (en) * | 2009-03-09 | 2013-03-13 | 日本電気株式会社 | Card edge terminal manufacturing method for printed wiring board |
| CN101699940A (en) * | 2009-11-10 | 2010-04-28 | 广州兴森快捷电路科技有限公司 | Manufacture method of golden finger printed board |
| CN102638945A (en) * | 2012-03-21 | 2012-08-15 | 深圳崇达多层线路板有限公司 | Method for producing goldfinger via twice electroplating |
| CN103233250A (en) * | 2013-04-28 | 2013-08-07 | 胜宏科技（惠州）股份有限公司 | Method for electroplating goldfinger with thick gold layer |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113115513A (en) | 2021-07-13 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105357892B (en) | Printed wiring board and preparation method thereof | |
| CN201267058Y (en) | Composite circuit board | |
| TW201038147A (en) | Printed wiring board and method for manufacturing same | |
| TW201023322A (en) | Wiring substrate and the method of manufacturing the same | |
| TW201533860A (en) | Wiring board and semiconductor device using the same | |
| US20090095508A1 (en) | Printed circuit board and method for manufacturing the same | |
| TWI278264B (en) | Wiring board manufacturing method | |
| CN103632979A (en) | Chip packaging substrate and structure, and manufacturing methods thereof | |
| TW201919453A (en) | Printed circuit board and method for manufacturing the same | |
| TWI474447B (en) | Semiconductor package structure and enveloping method thereof | |
| TWI395526B (en) | Printed circuit board strip and panel | |
| US20050101136A1 (en) | Etching method and method of manufacturing circuit device using the same | |
| CN106684050A (en) | Metal post conduction embedded chip circuit board structure and technological method thereof | |
| CN106684051A (en) | Metal post conducting chip-scale packaging structure and technique thereof | |
| TW200532811A (en) | Method for fabricating a packaging substrate | |
| CN108076585A (en) | Board structure of circuit and its manufacturing method | |
| JP2008124339A5 (en) | ||
| TW200816407A (en) | Window manufacture method of semiconductor package type printed circuit board | |
| US7919864B2 (en) | Forming of the last metallization level of an integrated circuit | |
| TWI594671B (en) | Flexible circuit board micro-aperture conductive through-hole structure and manufacturing method | |
| JP5058929B2 (en) | Wiring board and manufacturing method thereof | |
| TWI793935B (en) | Pad structure and test key structure and testing method for semiconductor device | |
| KR20170023310A (en) | Package substrate including embedded circuit pattern, manufacturing method of the same, and semiconductor package including the substrate | |
| CN104538322B (en) | A kind of single-side nickel-plating bonding method | |
| CN104185355B (en) | The preparation method and circuit board of a kind of circuit board |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20180525 |