CN108075782A - A kind of dual mode data restructuring network based on LDPC/Turbo codes - Google Patents
A kind of dual mode data restructuring network based on LDPC/Turbo codes Download PDFInfo
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- CN108075782A CN108075782A CN201810058248.1A CN201810058248A CN108075782A CN 108075782 A CN108075782 A CN 108075782A CN 201810058248 A CN201810058248 A CN 201810058248A CN 108075782 A CN108075782 A CN 108075782A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1105—Decoding
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
- H03M13/2957—Turbo codes and decoding
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Abstract
The present invention relates to a kind of data recombination networks of the dual-mode decoding device based on LDPC/Turbo, it is characterised in that replaces traditional interleaving address storage method and QPP interleaving address real-time calculations with the shift unit of memory and LDPC code.By prestoring one group of basic relocated address and corresponding shift value, relocated address in required piece of each clock cycle can be obtained.This method memory and the shift network of LDPC code make LDPC code/Turbo code data recombination network achieve the purpose that share instead of traditional QPP interleaving address generators.The advantages of this method is most directly perceived is so that the Turbo code separately to work /LDPC code data recombination network has the structure that can be shared, and has apparent advantage compared with conventional method in terms of resource consumption and storage occupancy.
Description
Technical field
The invention belongs to wireless communication system channel codec domains, are related to a kind of bimodulus based on LDPC/Turbo codes
Data recombination network.
Background technology
There are much calculating of the literature research data on LDPC code and Turbo codes on dual-mode decoding device in foreign countries at present
The shared problem of unit and storage organization.And for the data recombination unit outside decoding computing unit, LDPC code shift network
It separately works with the interleaving network of Turbo code, occupies respective logic unit.So far without documents by the displacement of LDPC code
The interleaving network of network and Turbo code realizes shared document and research.
The present invention passes through the parallel Turbo code interleaving address different to different code length under TD-LTE standards on MATLA platforms
It is emulated, summarizes and find that relocated address in the block of Turbo code can be sought with the shift unit in LDPC code shift network, realize
Two network portions share, and save the occupancy of bimodulus resource.
The content of the invention
Based on address shift rule is replaced in Turbo code block, it is proposed that with memory and the shift network generation of LDPC code
For traditional real-time interleaving address generators of QPP.For basic sequence and shift value that needs store, can be produced by MATLAB
Raw data generate it and initialization memory ROM are obtained after mif files, when FPGA is realized can to the IP kernel of Altera into
Row directly invokes.Shifting function is carried out by the way that pre-stored basic relocated address is sent into shift register, can be worked as
Relocated address in block needed for the preceding moment.Further according to relocated address in the block at current time, to be sent into the data in interleaver into
Intertexture between row sub-block.This method makes LDPC code shift network and Turbo code interleaving network have the structure that can be shared.
Present invention design is as follows：
Present invention design the general frame is as shown in Figure 1.The bimodulus shared data recombination structure is selected according to mode m ode
Input and output.In ldpc mode, LDPC code posterior information, the shift value of the reading in shift value memory 1 are inputted
To carry out cyclic shift, the LDPC code posterior information after output restructuring.Parameter P is degree of parallelism, at this time equal to the extension of LDPC code
The factor.In turbo mode, parameter P is the degree of parallelism of Turbo decodings, i.e. sub-block number.Different codes can be obtained by look-up table
According to the shift value that shift value memory 2 stores, displacement acquisition is carried out to basic relocated address for the basic sequence of long Turbo code
Relocated address in the block that current time needs.Relocated address in Turbo code posterior information and the block is inputted into interleaving/deinterleaving again
Turbo data after device is recombinated export.Read/write information after Turbo code interleaving/deinterleaving is also by prestoring
Mode in ROM obtains.P Turbo code after output finally reads/writes Turbo posterior informations according to address information
RAM。
In order to support the decoding of 6 kinds of code checks of LDPC code under WIMAX standards, there is one group of ROM to store in shift unit memory 1
The corresponding non-negative element value of basic matrix of all code checks, another group of ROM store the corresponding row number of each non-negative element of component code.Often
Group 6 pieces of ROM, each ROM store non-negative element or row number of 6 kinds of code checks with a line.Storage for Turbo code shift value, because
Degree of parallelism determines the bit wide of shift value, and the shift value under different degree of parallelisms is stored in different ROM groups.
The shifting function for the data that P bit wide is w is segmented into w group P bit datas and carries out identical displacement, Ran Houchong
It is new to be spliced into the data that P bit wide is w.It therefore, need to be in shift register and interleaving/deinterleaving device during each data recombination
Call the number sub-cells equal with bit wide.Assuming that Turbo code posterior information bit wide is 7, and degree of parallelism 8, data recombination network
Internal structure is as shown in Figure 2.
Cyclic shifter is made of bit separation unit, sub- shift unit and bit combination unit.For 8 that bit wide is 3
Relocated address d in block0~d7, the data that 3 bit wides are 8 bits are separated into according to the position of each bit, are sent into three son displacements
Device.The displacement numerical value sft of these three sub- shift units is consistent, and each data phase is taken by bit combination unit again after displacement
With the bit of position, 8 data D are reconsolidated into0~D7.This 8 data are relocated address in required piece.Interleaver
Equally it is made of bit separation unit, sub- interleaver and bit combination unit.It is 7 bits for 8 posterior information bit wides
Turbo code data i0~i7, 7 sub- interleavers are needed in interleaver.Every sub- interleaver is according to relocated address in the block of input
Instruction is interleaved 8 bit datas of separation restructuring.Finally, the bit of the 7 data same positions exported to sub- interleaver
It merges, the Turbo code posterior information I of data recombination is completed in output0~I7.In data recombination, the sub- shift unit of calling
Quantity is determined by the bit wide of parameter P, and the quantity of the sub- interleaver called is determined by the bit wide of posterior information.In setting for the present invention
It is 9 there is provided the maximum number of sub- shift unit and sub- interleaver in meter.So that the Turbo code separately to work /LDPC code data
Restructuring network has the structure that can be shared, and has saved resource consumption and storage occupancy.
This method has versatility when degree of parallelism is 4 to the realization of all code lengths.The basic displacement of storage needed for each code length
Address is divided into two kinds of " 0,1,2,3 " and " 0,3,2,1 ", is not enumerated herein due to code length is excessive.And it is 12 in degree of parallelism
In the case of, the code length that all code lengths can be divided exactly by 12 also all meets this rule.And degree of parallelism be 12 when, can only be divided exactly by 12
Code length could complete the parallel decoding of Lothrus apterus.It is understood that this method degree of parallelism be 12 when also have it is general
Property.Fig. 3 show the basic relocated address of storage needed for each code length when degree of parallelism is 12.It is special that the basic relocated addresses of Fig. 4 meet
The part Turbo code of situation.Basic relocated address meets the code length of such situation, can remove interleaver and deinterleaver, according to
The shift value of storage directly carries out Turbo code posterior information cyclic shift, and output is the Turbo code after data recombination.
Description of the drawings：1. Fig. 1 is design the general frame
2. Fig. 2 is data recombination network internal structure
The basic relocated address for storage needed for each code length that 3. Fig. 3 is degree of parallelism when being 12
4. Fig. 4 is the part Turbo code that basic relocated address meets special circumstances.
Claims (5)
1. a kind of data recombination network of the dual-mode decoding device based on LDPC/Turbo, feature includes shift value memory 1, moves
Place value memory 2, cyclic shifter, interleaving/deinterleaving device.The basic relocated address meets the part of special circumstances
Turbo code can save the tables of data of interleaving/deinterleaving, degree of parallelism be 12 when each code length needed for storage basic relocated address table,
Dual mode data recombination structure figure, data recombination inside configuration figure.
2. its characteristic procedure includes according to claim 1：The data generated by MATLAB, after mif files are generated to it
Initialization memory ROM is obtained, the IP kernel of Altera can be directly invoked when FPGA is realized.By will be pre-stored
Basic relocated address is sent into shift register and carries out shifting function, can obtain relocated address in the block needed for current time.Again
According to relocated address in the block at current time, the intertexture carrying out sub-block to the data being sent into interleaver.
3. in order to support the decoding of 6 kinds of code checks of LDPC code under WIMAX standards, there is one group of ROM to store institute in shift unit memory 1
There is the corresponding non-negative element value of basic matrix of code check, another group of ROM stores the corresponding row number of each non-negative element of component code.P
Bit wide is the shifting function of the data of w, is segmented into w group P bit datas and carries out identical displacement, is then spliced into P again
Bit wide is the data of w.
The basic relocated address of storage needed for each code length when 4. degree of parallelism is 12.
5. basic relocated address meets the part Turbo code of special circumstances.Basic relocated address meets the code length of such situation, can
Remove interleaver and deinterleaver, cyclic shift directly is carried out to Turbo code posterior information according to the shift value of storage, output is
For the Turbo code after data recombination.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113206674A (en) * | 2021-04-11 | 2021-08-03 | 南京理工大学 | Efficient interleaver for LDPC decoder and interleaving method |
| WO2022178790A1 (en) * | 2021-02-25 | 2022-09-01 | 华为技术有限公司 | Common mode decoding circuit, digital baseband, radio frequency transceiver, and decoding method |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106301390A (en) * | 2016-08-11 | 2017-01-04 | 中国计量大学 | LDPC/Turbo code dual-mode decoding device |
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- 2018-01-22 CN CN201810058248.1A patent/CN108075782A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106301390A (en) * | 2016-08-11 | 2017-01-04 | 中国计量大学 | LDPC/Turbo code dual-mode decoding device |
Non-Patent Citations (1)
| Title |
|---|
| 葛婷婷: "基于LDPC码和Turbo码的双模译码器设计", 《中国优秀硕士学位论文全文数据库 信息科技辑》 * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2022178790A1 (en) * | 2021-02-25 | 2022-09-01 | 华为技术有限公司 | Common mode decoding circuit, digital baseband, radio frequency transceiver, and decoding method |
| CN113206674A (en) * | 2021-04-11 | 2021-08-03 | 南京理工大学 | Efficient interleaver for LDPC decoder and interleaving method |
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Application publication date: 20180525 |