WO2022178790A1 - Common mode decoding circuit, digital baseband, radio frequency transceiver, and decoding method - Google Patents

Abstract

The present application relates to the field of communications. Disclosed are a common mode decoding circuit, a digital baseband, a radio frequency transceiver, and a decoding method, used for implementing multiplexing of an LDPC code and a Turbo code for decoding, so as to save resources. The common mode decoding circuit comprises: a cyclic shift network used for selectively receiving low density parity check (LDPC) code decoding information and performing cyclic shift calculation to output LDPC data, or, receiving Turbo decoding information and performing cyclic shift calculation to output a Turbo interleaving sequence, the LDPC decoding information comprising LDPC posteriori data and an LDPC cyclic shift value, and the Turbo decoding information comprising a basic sequence, a Turbo cyclic shift value, and a Turbo offset value respectively corresponding to odd columns and even columns of the Turbo interleaving sequence; an interleaving/de-interleaving circuit used for receiving Turbo posteriori data and the Turbo interleaving sequence, and performing interleaving and de-interleaving processing to obtain Turbo data; and a decoding circuit used for selectively decoding the LDPC data or the Turbo data.

Description

Common mode decoding circuit, digital baseband, radio frequency transceiver and decoding method technical field

The present application relates to the field of communications, and in particular, to a common mode decoding circuit, a digital baseband, a radio frequency transceiver and a decoding method.

Background technique

The data channel coding scheme of the fourth generation (4th generation, 4G) communication technology adopts the Turbo code, and the data channel coding scheme of the fifth generation (5th generation, 5G) communication technology adopts the low density parity check (low density parity). check, LDPC) code. For devices that support both 4G communication technology and 5G communication technology, it is necessary to support decoding both Turbo codes and LDPC codes.

The principle of decoding the Turbo code is to first calculate the Turbo interleaving sequence, and then interleave and de-interleave the data to be decoded according to the Turbo interleaving sequence to obtain the decoding result; the principle of decoding the LDPC code is to cyclically shift the data to be decoded through a cyclic shifter. bits to get the decoded result. Currently, the above two decoding processes are independent of each other in hardware implementation, which wastes resources.

SUMMARY OF THE INVENTION

Embodiments of the present application provide a common-mode decoding circuit, a digital baseband, a radio frequency transceiver, and a decoding method, which are used to implement multiplexing and decoding of LDPC codes and Turbo codes, so as to save resources.

To achieve the above object, the embodiments of the present application adopt the following technical solutions:

In a first aspect, a decoding circuit is provided, comprising: a cyclic shift network for selectively receiving LDPC decoding information and performing cyclic shift calculation to output LDPC data, or receiving Turbo decoding information and performing cyclic shifting Bit calculation to output the Turbo interleaved sequence; wherein, the LDPC decoding information includes: LDPC posterior data and LDPC cyclic shift value; Shift value and Turbo offset value, the base sequence is the result of taking the quotient of the value of an even column or an odd column in the Turbo interleaving sequence, and L is the length of one row of the Turbo interleaving sequence; interleaving/deinterleaving circuit, use After receiving the Turbo a posteriori data and the Turbo interleaving sequence, the interleaving and de-interleaving process is performed to obtain the Turbo data; the decoding circuit is used for selectively decoding the LDPC data or the Turbo data.

In the common-mode decoding circuit provided by the embodiments of the present application, the cyclic shift network can selectively receive LDPC decoding information and perform cyclic shift calculation to output LDPC data, or receive Turbo decoding information and perform cyclic shift calculation to output Turbo interleaved sequence. The interleaving/de-interleaving circuit receives the Turbo a posteriori data and the Turbo interleaving sequence, performs interleaving and de-interleaving processing, and obtains Turbo data. The decoding circuit selectively decodes the LDPC data or the Turbo data. Realize LDPC code and Turbo code multiplexing cyclic shift network for decoding, so resources are saved. In addition, in the process of obtaining the Turbo interleaved sequence by restoring the input base sequence, the turbo cyclic shift value and the turbo offset value, the input base sequence, the turbo cyclic shift value and the turbo offset value are respectively the odd numbers of the turbo interleaved sequence. The columns correspond to the even columns, because there is a cyclic shift relationship between the interleaving positions located in the odd columns, and there is also a cyclic shift relationship between the interleaving positions located in the even columns, so that the common mode decoding circuit can be applied to high parallelism. degree of turbo interleaving sequence.

In a possible implementation, the cyclic shift network includes a first cyclic shifter and a second cyclic shifter.

In a possible implementation manner, when the cyclic shift network receives the turbo decoding information: the first cyclic shifter is used to input a base sequence corresponding to one odd-numbered column of the turbo interleaving sequence and a plurality of odd-numbered columns of the turbo interleaving sequence. Turbo cyclic shift value and perform cyclic shift calculation to output the interleaving positions of multiple odd-numbered columns; the second cyclic shifter is used to input a base sequence corresponding to an even-numbered column of the turbo interleaving sequence and multiple even-numbered columns of the turbo interleaving sequence Turbo cyclic shift value and perform cyclic shift calculation to output the interleaving positions of multiple even columns. That is, the interleaving positions are calculated separately for odd-numbered columns and even-numbered columns.

In a possible implementation manner, the cyclic shift network further includes a first adder and a second adder, where the first adder is configured to input the interleaving positions of the plurality of odd-numbered columns and the turbo offset values of the plurality of odd-numbered columns, and output the The odd-numbered columns of the turbo interleaving sequence; the second adder is used to input the interleaving positions of the multiple even-numbered columns and the turbo offset values of the multiple even-numbered columns, and output the even-numbered columns of the Turbo interleaving sequence. That is, the odd and even columns of the turbo interleaved sequence are calculated separately.

In a possible implementation, the common mode decoding circuit further includes a parameter generator, a first locator and a second locator: the parameter generator is used to calculate a row, an even column and an odd column of the turbo interleaved sequence The value of the column; take the value of a row modulo L to obtain the turbo offset value corresponding to the odd column and the turbo offset value corresponding to the even column; take the value of an even column to L to obtain the base sequence corresponding to the even column, The value of an odd column is quotient to L to obtain the base sequence corresponding to the odd column; the value of a row is quotient to L to obtain the shift reference value corresponding to the odd column and the shift reference value corresponding to the even column; the first locator, It is used to input the shift reference value and base sequence corresponding to the odd-numbered columns, and output the Turbo cyclic shift value corresponding to the odd-numbered columns; the second locator is used to input the shift reference value and base sequence corresponding to the even-numbered columns, and output the even-numbered columns The corresponding turbo cyclic shift value. That is, the base sequence, the turbo offset value, and the turbo cyclic shift value are calculated separately for odd-numbered columns and even-numbered columns.

In a possible implementation, the interleaving/deinterleaving circuit includes a first interleaving/deinterleaving unit and a second interleaving/deinterleaving unit; the first interleaving/deinterleaving unit is configured to receive turbo a posteriori data and odd numbers of the turbo interleaving sequence The second interleaving/deinterleaving device is used to receive the turbo posterior data and the even columns of the Turbo interleaving sequence, and perform interleaving and deinterleaving to obtain the turbo data of the even columns. That is to say, the interleaving and deinterleaving processing is also performed separately for odd-numbered columns and even-numbered columns.

In a possible implementation manner, the decoding circuit is configured to combine the turbo data of the odd-numbered columns and the turbo data of the even-numbered columns, and decode the combined turbo data. That is, the turbo data of the odd-numbered columns and the turbo data of the even-numbered columns are combined first, and then decoded.

In a possible implementation manner, when the cyclic shift network receives LDPC decoding information, the first cyclic shifter is configured to input odd-numbered LDPC posterior data and corresponding LDPC cyclic shift values and perform cyclic shift calculation, to output odd-numbered LDPC data; the second cyclic shifter is used to input even-numbered LDPC posterior data and corresponding LDPC cyclic shift values and perform cyclic shift calculation to output even-numbered LDPC data. That is to say, LDPC data is also calculated separately for parity and even.

In a possible implementation, the decoding circuit is configured to combine odd-numbered LDPC data and even-numbered LDPC data, and decode the combined LDPC data. That is, the odd-numbered LDPC data and the even-numbered LDPC data are first combined, and then decoded.

In a second aspect, a digital baseband is provided, including a digital processing circuit and the common-mode decoding circuit according to the first aspect and any of the embodiments thereof, the digital processing circuit is used for digitally processing a digital signal of a receiving link to obtain a digital signal based on The data to be decoded of the Turbo code or the data to be decoded based on the LDPC code of the low density parity check code, and the common mode decoding circuit is used for decoding the data to be decoded to output a decoding result.

In a third aspect, a radio frequency transceiver is provided, including a receiving analog baseband and the digital baseband described in the second aspect; the receiving analog baseband is used to perform analog-to-digital conversion on a low-frequency modulated signal of a receiving link to obtain a digital receiving link. signal, the digital baseband is used to digitally process and decode the digital signal to obtain the decoded result.

A fourth aspect provides a decoding method, which is applied to the common-mode decoding circuit of the first aspect and any one of the embodiments thereof, the method comprising: selectively receiving low-density parity-check code LDPC decoding information and performing a cyclic shift Bit calculation to output LDPC data, or, receiving image dial Turbo decoding information and performing cyclic shift calculation to output Turbo interleaved sequence; wherein, LDPC decoding information includes: LDPC posterior data and LDPC cyclic shift value; Turbo decoding The information includes: the base sequence, the turbo cyclic shift value, and the turbo offset value corresponding to the odd and even columns of the turbo interleaving sequence, respectively, and the base sequence is the value of an even column or an odd column in the turbo interleaving sequence to take the quotient of L As a result, L is the length of one line of the Turbo interleaving sequence; receive the Turbo a posteriori data and the Turbo interleaving sequence, perform interleaving and deinterleaving processing, and obtain Turbo data; selectively decode the LDPC data or the Turbo data.

In a possible implementation manner, receiving image dial turbo decoding information and performing cyclic shift calculation to output a turbo interleaving sequence, including: inputting the interleaving positions of multiple odd-numbered columns and the turbo offset values of multiple odd-numbered columns, and outputting Odd-numbered columns of the turbo interleaving sequence; input the interleaving positions of multiple even-numbered columns and the turbo offset values of multiple even-numbered columns, and output the even-numbered columns of the turbo interleaving sequence.

In a possible implementation manner, the method further includes: calculating the values of a row, an even column and an odd column of the Turbo interleaving sequence; taking the value of a row modulo L to obtain the Turbo offset value corresponding to the odd column and the corresponding value of the even column The Turbo offset value of ; take the value of an even column to L to get the base sequence corresponding to the even column, take the value of an odd column to L to obtain the base sequence corresponding to the odd column; take the value of a row to L to take the quotient Obtain the shift reference value corresponding to the odd-numbered column and the shift reference value corresponding to the even-numbered column; input the shift reference value and base sequence corresponding to the odd-numbered column, and output the turbo cycle shift value corresponding to the odd-numbered column; input the shift corresponding to the even-numbered column Reference value and base sequence, output the turbo cyclic shift value corresponding to the even-numbered column.

In a possible implementation manner, receiving Turbo a posteriori data and a Turbo interleaving sequence, performing interleaving and deinterleaving processing to obtain Turbo data, including: receiving Turbo a posteriori data and an odd-numbered column of the Turbo interleaving sequence, performing interleaving and deinterleaving processing, Turbo data of odd-numbered columns is obtained; Turbo a posteriori data and even-numbered columns of the Turbo interleaving sequence are received, and interleaving and de-interleaving processing is performed to obtain Turbo data of even-numbered columns.

In a possible implementation manner, selectively decoding the LDPC data or the turbo data includes: combining the turbo data of the odd-numbered columns and the turbo data of the even-numbered columns, and decoding the combined turbo data.

In a possible implementation manner, when receiving LDPC decoding information, receiving low density parity check code LDPC decoding information and performing cyclic shift calculation to output LDPC data, including: inputting odd-numbered LDPC posterior data and corresponding The LDPC cyclic shift value and the cyclic shift calculation are performed to output the odd-numbered LDPC data; the even-numbered LDPC posterior data and the corresponding LDPC cyclic shift value are input and the cyclic shift calculation is performed to output the even-numbered LDPC data.

In a possible implementation manner, selectively decoding LDPC data or Turbo data includes: combining odd-numbered LDPC data and even-numbered LDPC data, and decoding the combined LDPC data.

In a fifth aspect, a computer-readable storage medium is provided, in which a computer program is stored, which, when executed on a computer, causes the computer to perform the method of the fourth aspect and any one of the embodiments thereof.

In a sixth aspect, there is provided a computer program product comprising instructions which, when run on a computer or processor, cause the computer or processor to perform the method of the fourth aspect and any one of the embodiments.

For the technical effects of the second to sixth aspects, refer to the technical effects of the first aspect and any of its embodiments.

Description of drawings

FIG. 1 is a schematic structural diagram of a radio frequency transceiver according to an embodiment of the present application;

2 is a schematic structural diagram of a DBB according to an embodiment of the present application;

3 is a schematic diagram of a base sequence, a Turbo cyclic shift value, and a Turbo offset value of a Turbo interleaved sequence inversely deduced by a Turbo interleaved sequence provided by an embodiment of the present application;

FIG. 4 is a schematic structural diagram 1 of a common-mode decoding circuit provided by an embodiment of the present application;

FIG. 5 is a second schematic structural diagram of a common-mode decoding circuit according to an embodiment of the present application;

6 is a schematic flowchart 1 of a decoding method provided by an embodiment of the present application;

FIG. 7 is a second schematic flowchart of a decoding method provided by an embodiment of the present application;

FIG. 8 is a third schematic flowchart of a decoding method provided by an embodiment of the present application;

FIG. 9 is a third schematic structural diagram of a common-mode decoding circuit according to an embodiment of the present application.

Detailed ways

As shown in FIG. 1, the figure shows the structure of a radio frequency transceiver, which can be applied to a communication device. The transceiver includes: a phase locked loop (PLL) 10, a local oscillator (local oscillator generator, LO) 11, digital base band (DBB) 12 and radio frequency circuit, the radio frequency circuit includes receive analog base band (receive analog base band, RX ABB) 13, transmit analog base band (transmit analog base band, TX ABB) 14, low A low noise amplifier (LNA) 15 , a power amplifier (PA) 16 , an antenna 17 , a first mixer 18 , a second mixer 19 and an antenna switch 20 .

First, the connection relationship of the above components is explained:

The output of PLL 10 is coupled to the input of LO 11 , the output of which may be coupled to the first input of first mixer 18 and the first input of second mixer 19 .

For the receiving chain of the radio frequency circuit, the antenna 17 is coupled to the input terminal of the LNA 15 through the first path of the antenna switch 20, and the output terminal of the LNA 15 is coupled to the second input terminal of the first mixer 18, and the first mixer The output of 18 is coupled to the input of RX ABB 13, and the output of RX ABB 13 is coupled to DBB 12.

For the transmit chain of the radio frequency circuit, DBB 12 is coupled to the input of TX ABB 14, the output of TX ABB 14 is coupled to the second input of second mixer 19, and the output of second mixer 19 is coupled to The input of the PA 16, the output of the PA 16 is coupled to the antenna 17 through the second path of the antenna switch 20.

The functions of the above devices are described below:

The PLL 10 is used to output a first oscillation signal of a fixed clock frequency for each channel to the LO 11.

LO 11 is used to process the first oscillating signal (optional frequency division, and optional output quadrature phase) and output transmit oscillating signals of multiple local oscillator frequencies, or process the first oscillating signal ( Optional frequency division, and optional output quadrature phase) and output receiving oscillating signals of multiple local oscillator frequencies, the transmitting oscillating signal and the receiving oscillating signal may be the same or different.

The LNA 15 is used to amplify the high frequency analog signal received through the antenna 17 with the low frequency modulated signal.

The first mixer 18 is used to mix the received oscillating signal and the signal output by the LNA 15, and output it to the RX ABB 13.

The RX ABB 14 is used for analog-to-digital conversion of the low frequency modulated signal of the receive chain to obtain a digital signal of the receive chain. For example, the RX ABB 14 filters, amplifies, and analog-to-digital converts the signal output from the first mixer 18 to obtain a digital signal.

The DBB 12 is used for digitally processing and decoding the digital signal corresponding to the low-frequency modulation signal received by the receiving link to obtain a decoding result, or sending the digital signal to the transmitting link.

The TX ABB 13 is used to filter and amplify the digital signal from the DBB 12.

The second mixer 19 is used to mix the transmit oscillating signal (optionally, and the signal output by the TX ABB 13 ) and output it to the PA 16 .

PA 16 is used to amplify the high frequency signal after mixing.

The communication apparatus involved in the embodiment of the present application may be a device including a wireless transceiver function. A communication apparatus may also be referred to as terminal equipment, user equipment (UE), access terminal, subscriber unit, subscriber station, mobile station, mobile station, remote station, remote terminal, mobile equipment, user terminal, terminal, wireless communication device, user agent, or user device. For example, the communication device may be a cell phone, smart speaker, smart watch, handheld device with wireless communication capabilities, computing device or other processing device connected to a wireless modem, robot, drone, smart driving vehicle, smart home, in-vehicle device, Medical equipment, smart logistics equipment, wearable equipment, Wi-Fi equipment, terminal equipment in a future 5G network or a network after 5G, etc., are not limited in this embodiment of the present application.

As shown in FIG. 2, a structure of the DBB 12 is shown. The DBB 12 includes a digital processing circuit 121 and a common-mode decoding circuit 122. The digital processing circuit 121 is used to digitally process the digital signal of the receiving chain to obtain a turbo-based digital signal. The common mode decoding circuit 122 is used for decoding the data to be decoded to output the decoding result.

In a possible implementation, the digital processing circuit 121 includes a coupled de-offset and de-cyclic prefix (cyclic prefix, CP) circuit 1211, a fast Fourier transform (fast Fourier transform, FFT) and a user separation circuit 1212, Channel estimation circuit 1213 , equalizer 1214 , inverse discrete Fourier transform (IDFT) circuit 1215 , channel compensation circuit 1216 , demodulator 1217 , descrambler 1218 . After the DBB 12 inputs the IO data from the TX ABB, the decoding result is output by the common mode decoding circuit 122 through the processing of each circuit.

The de-offset and de-CP circuit 1211 is used to mitigate inter-symbol interference caused by wireless transmission multipath fading.

The FFT and user separation circuit 1212 is used to perform time-frequency domain transformation, and obtain frequency domain information by separation.

The channel estimation circuit 1213 is used for estimating the time domain or frequency domain response of the channel to correct and recover the received data.

The equalizer 1214 is used to generate the opposite characteristic of the channel to cancel the intersymbol interference caused by the time-varying multipath propagation characteristic of the channel.

The IDFT circuit 1215 is configured to restore the uplink received orthogonal frequency division multiplexing (OFDM) carrier signal to a single carrier frequency division multiple access (SC-FDMA) carrier signal.

The channel compensation circuit 1216 is used for compensating errors introduced by operations such as receiver channel estimation.

The demodulator 1217 is used to restore the information in the modulation symbols into bit stream information.

The descrambler 1218 is used to remove the user scramble information contained in the bit stream to obtain the original user bit stream.

The common mode decoding circuit 122 is used for decoding LDPC codes or decoding Turbo codes.

As mentioned above, currently, the process of decoding the LDPC code by the common-mode decoding circuit 122 and the process of decoding the Turbo code are independent of each other in terms of hardware implementation, which wastes resources. Therefore, in order to perform resource multiplexing for these two processing procedures, in one embodiment, the cyclic shift of the interleaving address in the quadratic polynomial permutation (QPP) interleaving of the Turbo code under low parallelism can be performed. As a rule, the memory, the adder, and the cyclic shifter used in the LDPC code decoding process are used to replace the QPP interleaver used in the Turbo code decoding process. The base sequence, Turbo offset value and Turbo cyclic shift value of the Turbo interleaving sequence can be pre-stored in the memory. The cyclic shifter inputs the base sequence and Turbo cyclic shift value of the Turbo interleaving sequence and performs cyclic shifting to obtain each column of Turbo interleaving. For the interleaving position of the sequence, the adder inputs the interleaving position and Turbo offset value of each column of Turbo interleaving sequences, and outputs the Turbo interleaving sequence. In this way, resource utilization is improved by multiplexing resources with LDPC codes and Turbo codes.

Regarding, the base sequence, the turbo cyclic shift value and the turbo offset value of the turbo interleaved sequence will be described later.

The original formula for calculating the Turbo interleaved sequence through the QPP interleaver is as follows:

f(x)=(f ₂ x ² +f ₁ x)modK Equation 1

Among them, K represents the code length of the Turbo code, that is, the number of values in the Turbo interleaved sequence. x represents the position before interleaving, and the value range is K natural numbers (for example, 0, 1, 2, 3... K-1). f ₁ and f ₂ are coefficients, and their values correspond to K according to the protocol. f(x) represents the output turbo interleaved sequence.

In the following, in conjunction with Fig. 3, it is explained how to deduce the base sequence, Turbo cyclic shift value and Turbo offset value of the Turbo interleaved sequence through the Turbo interleaved sequence:

Exemplarily, assuming that the code length of the Turbo code is K=6144, a Turbo interleaving sequence f(x) with K values is obtained according to formula 1, and the Turbo interleaving sequence is divided into four segments according to the parallelism W=4, and each segment of Turbo interleaving is interleaved. The length of the sequence is L=K/W=1536, resulting in a 4*L matrix pattern as shown in Table 1. Among them, f ₂ =480 and f ₁ =343 in formula 1, the first section of turbo interleaving sequence corresponds to x value of 0-1535, the second section of turbo interleaving sequence corresponds to x value of 1536-3071, and the third section of turbo interleaving sequence corresponds to x value of 1536-3071 The sequence corresponds to x values of 3072-4607, and the fourth segment of the turbo interleaved sequence corresponds to x values of 4608-6143. Among them, the degree of parallelism refers to the amount of data that can be processed at the same time.

Table 1

	0	1	2	3	4	5	6	7	…	1534	1535
first paragraph	0	743	2446	5109	2588	1027	426	785	…	6002	4825
second paragraph	4608	5351	910	3573	1052	5635	5034	5393	…	4466	3289
third paragraph	3072	3815	5518	2037	5660	4099	3498	3857	…	2930	1753
fourth paragraph	1536	2279	3982	501	4124	2563	1962	2321	…	1394	217

All the values in Table 1 are modulo L to get the Turbo offset value (OFFSET) shown in Table 2. It can be seen from this that the Turbo offset values of the same column of Turbo interleaved sequences are the same, that is, the values at the same position in each segment of the Turbo interleaved sequence are still at the same relative position in this segment of the Turbo interleaved sequence after interleaving.

Table 2

	0	1	2	3	4	5	6	7	…	1534	1535
first paragraph	0	743	910	501	1052	1027	426	785	…	1394	217

second paragraph	0	743	910	501	1052	1027	426	785	…	1394	217
third paragraph	0	743	910	501	1052	1027	426	785	…	1394	217
fourth paragraph	0	743	910	501	1052	1027	426	785	…	1394	217

All values of the Turbo interleaving sequence in Table 1 are quotient to L to obtain the interleaving position (PHI value) shown in Table 3, where the interleaving position refers to the exchange sequence number of the same column value. It can be seen from this that there is a cyclic shift relationship between the interleaving positions of each column of Turbo interleaving sequences, that is, they can be derived by adding a certain Turbo cyclic shift value to the interleaving position of the first column of Turbo interleaving sequences. The columns are 0, 3, 2, 1, the second column is 0, 3, 2, 1 from the first column plus a turbo cyclic shift value of 0, and the third column is the first column plus a turbo cyclic shift value of 3 (rotate up by 3) to get 1, 0, 3, 2, and so on.

table 3

	0	1	2	3	4	5	6	7	…	1534	1535
first paragraph	0	0	1	3	1	0	0	0	…	3	3
second paragraph	3	3	0	2	0	3	3	3	…	2	2
third paragraph	2	2	3	1	3	2	2	2	…	1	1
fourth paragraph	1	1	2	0	2	1	1	1	…	0	0

Any value in the original Turbo interleaving sequence can be obtained by =PHI*L+OFFSET, that is, "interleaving position*length of each Turbo interleaving sequence L+Turbo offset value". Since there is a cyclic shift relationship between the interleaving positions of the turbo interleaving sequences in each column, only the interleaving positions of the turbo interleaving sequences in the first column and the interleaving positions of the turbo interleaving sequences in the other columns are stored relative to the turbo interleaving sequences in the first column. The Turbo cyclic shift value of the interleaving position of , the interleaving position of any column of Turbo interleaving sequences can be obtained. Combined with the Turbo offset value of the first Turbo interleaving sequence, any value of the Turbo interleaving sequence can be derived without storing all the interleaving sequences, thus reducing resource overhead. Therefore, the interleaving position of the first column of the turbo interleaving sequence can be called the base sequence of the turbo interleaving sequence.

Based on the above principles, the embodiments of the present application provide a common-mode decoding circuit as shown in FIG. 4 , which can implement the decoding of Turbo codes and the decoding of LDPC codes. The common mode decoding circuit includes a plurality of selectors 41 , a cyclic shifter 42 , an adder 43 , an interleaver/deinterleaver 44 , a memory (eg read-only memory (ROM)) 45 and a decoding circuit 46 .

Among them, the selector 41 is used to select one output from two inputs.

In LDPC mode (selector 41 is switched to state "1"), cyclic shifter 42 selectively inputs LDPC a posteriori data (also called LDPC a posteriori information or LDPC data to be decoded), and reads from memory 45 The LDPC cyclic shift value is cyclically shifted to output LDPC data (also called routing a posteriori information), and the decoding circuit 46 decodes the LDPC data to output a decoded result (also called decoded LDPC code).

In the turbo mode (the selector 41 is switched to the state "0"), the cyclic shifter 42 inputs the base sequence of the turbo interleaved sequence read from the memory 45, the turbo cyclic shift value for cyclic shifting, and sends them to the adder 43 outputs the interleaving position of the Turbo interleaving sequence, and the adder 43 also reads the Turbo offset value from the memory 45, according to the aforementioned formula "interleaving position * length L+Turbo offset value of each Turbo interleaving sequence" to the interleaving value. The interleaver/deinterleaver 44 outputs the Turbo interleaved sequence, and the interleaver/deinterleaver 44 additionally inputs Turbo a posteriori data (also referred to as Turbo data to be decoded), and outputs Turbo data (also referred to as Turbo data to be decoded) after interleaving and deinterleaving processing by the interleaver/deinterleaver 24 routing a posteriori information), the decoding circuit 46 decodes the turbo data to output a decoded result (also called a decoded turbo code).

The above common-mode decoding circuit is only suitable for Turbo codes with low parallelism (small number of segments). Due to the shift characteristics, the cyclic shifter used in the decoding process of the non-reusable LDPC code lacks universality.

Exemplarily, assuming that the code length of the Turbo code is K=6080, the Turbo interleaving sequence f(x) is obtained according to formula 1, and the Turbo interleaving sequence is divided into eight segments according to the degree of parallelism W=8, and the length of each segment of the Turbo interleaving sequence is L= K/W=760, an 8*L matrix pattern as shown in Table 4 is obtained. Among them, f ₂ =190, f ₁ =47 in formula 1, the first stage of Turbo interleaving sequence corresponds to x value of 0-759, the second stage of Turbo interleaving sequence corresponds to x value of 760-1519, the third stage of Turbo interleaving sequence The sequence corresponds to the x value of 1520-2279, the fourth segment of the Turbo interleaved sequence corresponds to the x value of 2280-3039, the fifth segment of the Turbo interleaved sequence corresponds to the x value of 3040-3799, and the sixth segment of the Turbo interleaved sequence corresponds to the x value of 3040-3799. The value is 3800-4559, the seventh segment of the turbo interleaved sequence corresponds to the x value of 4560-5319, and the eighth segment of the turbo interleaved sequence corresponds to the x value of 5320-6079.

Table 4

	0	1	2	3	4	5	6	7	…	758	759
first paragraph	0	237	854	1851	3228	4985	1042	3559	…	5986	2423
second paragraph	5320	2517	94	4131	2468	1185	282	5839	…	5226	4703
third paragraph	4560	4797	5414	331	1708	3465	5602	2039	…	4466	903
fourth paragraph	3800	997	4654	2611	648	5745	4842	4319	…	3706	3183
fifth paragraph	3040	3277	3894	4891	188	1945	4082	519	…	2946	5463
sixth paragraph	2280	5557	3134	1091	5508	4225	3322	2799	…	2186	1663
paragraph 7	1520	1757	2374	3371	4748	425	2562	5079	…	1426	3943
eighth paragraph	760	4037	1614	5651	3988	2705	1802	1279	…	666	143

All the values of the Turbo interleaving sequence in Table 4 are quotient to L to obtain the interleaving positions (PHI values) shown in Table 5. It can be seen from this that there is no cyclic shift relationship between the interleaving positions of each column of Turbo interleaving sequences, that is, it cannot be derived by adding the Turbo shift value to the interleaving positions of the first column of Turbo interleaving sequences.

table 5

	0	1	2	3	4	5	6	7	…	758	759
first paragraph	0	0	1	2	4	6	1	4	…	7	3
second paragraph	7	3	0	5	3	1	0	7	…	6	6
third paragraph	6	6	7	0	2	4	7	2	…	5	1
fourth paragraph	5	1	6	3	1	7	6	5	…	4	4
fifth paragraph	4	4	5	6	0	2	5	0	…	3	7
sixth paragraph	3	7	4	1	7	5	4	3	…	2	2
paragraph 7	2	2	3	4	6	0	3	6	…	1	5
eighth paragraph	1	5	2	7	5	3	2	1	…	0	0

And the Turbo interleaving sequence with higher parallelism, the more the number of code lengths whose interleaving positions do not satisfy the cyclic shift relationship, Table 6 shows the code lengths corresponding to the interleaving positions that satisfy the cyclic shift relationship when the parallelism is 12, and the remaining codes None of the long interleaving positions satisfy the cyclic shift relationship.

Table 6

In addition, the base sequences of the turbo interleaving sequences of different code lengths are also different, and the higher the degree of parallelism, the greater the number of base sequences of the turbo interleaving sequences. The base sequences of all Turbo interleaving sequences of the same code length are stored in advance through the memory, and the base sequence of one of the Turbo interleaving sequences is selected by the selector during use, which has a large resource overhead; and if the Turbo interleaving sequence is directly calculated by formula 1, the computational complexity high.

Although there is no cyclic shift relationship between the interleaving positions of the two adjacent columns of the turbo interleaving sequence in the example of Table 5 above, it can be seen that there is a cyclic shift relationship between the interleaving positions located in the odd-numbered columns, and the interleaving positions located in the even-numbered columns have a cyclic shift relationship. There is also a cyclic shift relationship between the interleaving positions. For example, the first column of Table 5 is 0, 7, 6, 5, 4, 3, 2, 1, and the third column is 1, which is obtained by adding the turbo cyclic shift value of 7 (upward cyclic shift by 7) to the first column. 0, 7, 6, 5, 4, 3, 2, and so on. Similarly, the second column of Table 5 is 0, 3, 6, 1, 4, 7, 2, 5, and the fourth column is the second column plus the turbo cyclic shift value of 6 (upward cyclic shift of 6) to get 2 , 5, 0, 3, 6, 1, 4, 7, and so on.

Therefore, in the common-mode decoding circuit of the embodiment of the present application, the Turbo interleaving sequence forming the matrix pattern is divided into odd-numbered columns and even-numbered columns, and the turbo offset value and interleaving position of the odd-numbered or even-numbered columns are calculated respectively, and the Turbo offset value and the interleaving position of the odd-numbered or even-numbered columns are calculated respectively. And the adder restores the original Turbo interleaved sequence for odd or even columns, respectively.

As shown in FIG. 5 , the common mode decoding circuit includes a cyclic shift network 51, an interleaving/deinterleaving circuit 52, a decoding circuit 53, a parameter generator 54, a first locator 55, a second locator 56 and multiple selector 57.

Among them, the selector 57 is optional and is used to select one output from the two inputs.

The cyclic shift network 51 includes a first cyclic shifter 511 , a second cyclic shifter 512 , a first adder 513 and a second adder 514 . The interleaving/deinterleaving circuit 52 includes a first interleaving/deinterleaving unit 521 and a second interleaving/deinterleaving unit 522 .

The common-mode decoding circuit is used to implement the decoding method shown in FIG. 6 , and the functions of the above modules will be described below with reference to FIG. 6 .

As shown in Figure 6, the decoding method includes steps S601-S603:

S601. The cyclic shift network 51 selectively receives LDPC decoding information and performs cyclic shift calculation to output LDPC data, or receives Turbo decoding information and performs cyclic shift calculation to output a Turbo interleaved sequence.

In LDPC mode (selector 57 switches to state "1"), cyclic shift network 51 selectively receives LDPC decoding information and performs cyclic shift calculations to output LDPC data. The LDPC decoding information includes: LDPC posterior data and LDPC cyclic shift value. The LDPC posterior data is the LDPC data to be decoded, and the LDPC cyclic shift value is determined by the protocol and can be stored in the memory.

Wherein, when the cyclic shift network 51 receives the LDPC decoding information, the first cyclic shifter 511 inputs odd LDPC posterior data and corresponding LDPC cyclic shift values and performs cyclic shift calculation to output odd LDPC data . The second cyclic shifter 512 inputs even-numbered LDPC posterior data and corresponding LDPC cyclic shift values and performs cyclic shift calculation to output even-numbered LDPC data.

In turbo mode (selector 57 switches to state "0"), cyclic shift network 51 selectively receives turbo decoded information and performs cyclic shift calculations to output a turbo interleaved sequence. The turbo decoding information includes: a base sequence, a turbo cyclic shift value and a turbo offset value corresponding to the odd-numbered columns and the even-numbered columns of the turbo interleaving sequence, respectively.

First, how to obtain the base sequence, the turbo cyclic shift value, and the turbo offset value will be described with reference to FIG. 7 .

S701. The parameter generator 54 calculates the values of one row, one even column and one odd column in the turbo interleaving sequence of W rows and L columns.

First, combine Table 7-Table 19 to illustrate how to obtain the Turbo interleaving sequence of W rows and L columns:

It is assumed that the code length K of the Turbo interleaving sequence is M*W*L*2^n, where L and W are positive integers, and L is a multiple of 2; M and n are positive integers. That is to say, when calculating the Turbo interleaving sequence by formula 1, the input parameter K=M*W*L*2^n.

When the Turbo interleaving sequence is represented in the form of a matrix pattern of W rows and M*L*2^n columns, the Turbo interleaving sequence of W rows and M*L*2^n columns can be split continuously by column by using the dichotomy method until W rows are obtained. Turbo interleaved sequence of L columns.

In a possible implementation manner, a turbo interleaving sequence of W rows and L columns may be obtained by splitting the Turbo interleaving sequence of W rows and M*L*2^n columns according to parity columns.

Exemplarily, assuming that the code length of the Turbo code is K=6080, the Turbo interleaving sequence f(x) is obtained according to formula 1, and the Turbo interleaving sequence is divided into four segments according to the degree of parallelism W=4, and the length of each segment of the Turbo interleaving sequence is K/ W=1520, a 4*1520 matrix pattern as shown in Table 7 is obtained. Assuming M=1 and n=2, there are L=380. Among them, f ₂ =190 and f ₁ =47 in formula 1, the first section of Turbo interleaving sequence corresponds to x value of 0-1519, the second section of Turbo interleaving sequence corresponds to x value of 1520-3039, and the third section of Turbo interleaving sequence The sequence corresponds to x values of 3040-4559, and the fourth segment of the Turbo interleaved sequence corresponds to x values of 4560-6079.

Table 7

	0	1	2	3	4	5	6	7	…	1518	1519
first paragraph	0	237	854	1851	3228	4985	1042	3559	…	5226	4703
second paragraph	4560	4797	5414	331	1708	3465	5602	2039	…	3706	3183
third paragraph	3040	3277	3894	4891	188	1945	4082	519	…	2186	1663
fourth paragraph	1520	1757	2374	3371	4748	425	2562	5079	…	666	143

The Turbo interleaved sequence of 4 rows and 1520 columns shown in Table 7 is split according to the odd and even columns to obtain two Turbo interleaved sequences of 4 rows and 760 columns, wherein the Turbo interleaved sequences of 4 rows and 760 columns corresponding to the odd columns are shown in Table 8 , the turbo interleaving sequence of 4 rows and 760 columns corresponding to the even columns is shown in Table 9.

Table 8

	0	2	4	6	…	1518
first paragraph	0	854	3228	1042	…	5226

second paragraph	4560	5414	1708	5602	…	3706
third paragraph	3040	3894	188	4082	…	2186
fourth paragraph	1520	2374	4748	2562	…	666

Table 9

	1	3	5	7	…	1519
first paragraph	237	1851	4985	3559	…	4703
second paragraph	4797	331	3465	2039	…	3183
third paragraph	3277	4891	1945	519	…	1663
fourth paragraph	1757	3371	425	5079	…	143

The Turbo interleaved sequence of 4 rows and 760 columns shown in Table 8 is split according to the odd and even columns to obtain two Turbo interleaved sequences of 4 rows and 380 columns, wherein the Turbo interleaved sequences of 4 rows and 380 columns corresponding to the odd columns are shown in Table 10 , the turbo interleaving sequence of 4 rows and 380 columns corresponding to the even columns is shown in Table 11.

Table 10

	0	4	…	1516
first paragraph	0	3228	…	1332
second paragraph	4560	1708	…	5892
third paragraph	3040	188	…	4372
fourth paragraph	1520	4748	…	2852

Table 11

	2	6	…	1518
first paragraph	854	1042	…	5226
second paragraph	5414	5602	…	3706
third paragraph	3894	4082	…	2186
fourth paragraph	2374	2562	…	666

The Turbo interleaved sequence of 4 rows and 760 columns shown in Table 9 is split according to the odd and even columns to obtain two Turbo interleaved sequences of 4 rows and 380 columns, wherein the Turbo interleaved sequences of 4 rows and 380 columns corresponding to the odd columns are shown in Table 12 , the turbo interleaving sequence of 4 rows and 380 columns corresponding to the even columns is shown in Table 13.

Table 12

	1	5	…	1517
first paragraph	237	4985	…	49
second paragraph	4797	3465	…	4609
third paragraph	3277	1945	…	3089
fourth paragraph	1757	425	…	1569

Table 13

	3	7	…	1519
first paragraph	1851	3559	…	4703
second paragraph	331	2039	…	3183
third paragraph	4891	519	…	1663

fourth paragraph

3371

5079

…

143

Then the Turbo interleaving sequence of W rows and L columns can be any of the Turbo interleaving sequences shown in Table 10-Table 13.

In another possible implementation manner, the Turbo interleaving sequence of W rows and M*L*2^n columns may be split in half by column to obtain the Turbo interleaving sequence of W rows and L columns.

Exemplarily, the Turbo interleaving sequence of 4 rows and 1520 columns shown in Table 7 is still used as an example for description. Split it in half by column to obtain two Turbo interleaving sequences of 4 rows and 760 columns. Among them, the Turbo interleaving sequence of the first half of 4 rows and 760 columns is shown in Table 14, and the Turbo interleaved sequence of the second half of 4 rows and 760 columns is shown in Table 1. 15 shown.

Table 14

	0	1	…	759
first paragraph	0	237	…	2423
second paragraph	4560	4797	…	903
third paragraph	3040	3277	…	5463
fourth paragraph	1520	1757	…	3943

Table 15

	760	761	…	1519
first paragraph	5320	2517	…	4703
second paragraph	3800	997	…	3183
third paragraph	2280	5557	…	1663
fourth paragraph	760	4037	…	143

The Turbo interleaved sequence of 4 rows and 760 columns shown in Table 14 is split in half by column to obtain two Turbo interleaved sequences of 4 rows and 380 columns, wherein the first half of the Turbo interleaved sequences of 4 rows and 380 columns are shown in Table 16, The Turbo interleaving sequence of the second half with 4 rows and 380 columns is shown in Table 17.

Table 16

	0	1	…	379
first paragraph	0	237	…	4323
second paragraph	4560	4797	…	2803
third paragraph	3040	3277	…	1283
fourth paragraph	1520	1757	…	5843

Table 17

	380	381	…	759
first paragraph	2660	1377	…	2423
second paragraph	1140	5937	…	903
third paragraph	5700	4417	…	5463
fourth paragraph	4180	2897	…	3943

The Turbo interleaved sequence of 4 rows and 760 columns shown in Table 15 is split in half to obtain two Turbo interleaved sequences of 4 rows and 380 columns, wherein the first half of the Turbo interleaved sequences of 4 rows and 380 columns are shown in Table 18, The Turbo interleaving sequence of 4 rows and 380 columns in the second half is shown in Table 19.

Table 18

	760	761	…	1139
first paragraph	5320	2517	…	523
second paragraph	3800	997	…	5083
third paragraph	2280	5557	…	3563
fourth paragraph	760	4037	…	2043

Table 19

	1140	1141	…	1519
first paragraph	1900	3657	…	4703
second paragraph	380	2137	…	3183
third paragraph	4940	617	…	1663
fourth paragraph	3420	5177	…	143

Then the Turbo interleaving sequence of W rows and L columns can be any of the Turbo interleaving sequences shown in Table 16-Table 19.

As described above for Table 5, although there is no cyclic shift relationship between the interleaving positions of the two adjacent columns of the turbo interleaving sequence, there is a cyclic shift relationship between the interleaving positions located in the odd-numbered columns. There is also a cyclic shift relationship between the interleaving positions.

Therefore, in the embodiment of the present application, the Turbo interleaving sequence of W rows and L columns is divided into odd and even columns, which includes L/2 even columns and L/2 odd columns, that is, the Turbo interleaving sequence of W rows and L columns is divided into odd columns and L/2 odd columns. Even columns are treated separately.

Exemplarily, still taking the Turbo interleaving sequence shown in Table 4 as an example, W=8, L=760, the odd-numbered columns of the Turbo interleaving sequence are shown in Table 20, and the even-numbered columns of the Turbo interleaving sequence are shown in Table 21.

Table 20

	0	2	4	6	…	758
first paragraph	0	854	3228	1042	…	5986
second paragraph	5320	94	2468	282	…	5226
third paragraph	4560	5414	1708	5602	…	4466
fourth paragraph	3800	4654	648	4842	…	3706
fifth paragraph	3040	3894	188	4082	…	2946
sixth paragraph	2280	3134	5508	3322	…	2186
paragraph 7	1520	2374	4748	2562	…	1426
eighth paragraph	760	1614	3988	1802	…	666

Table 21

	1	3	5	7	…	759
first paragraph	237	1851	4985	3559	…	2423
second paragraph	2517	4131	1185	5839	…	4703
third paragraph	4797	331	3465	2039	…	903
fourth paragraph	997	2611	5745	4319	…	3183
fifth paragraph	3277	4891	1945	519	…	5463

sixth paragraph	5557	1091	4225	2799	…	1663
paragraph 7	1757	3371	425	5079	…	3943
eighth paragraph	4037	5651	2705	1279	…	143

It should be noted that, in this embodiment of the present application, the parameter generator 54 does not need to store or calculate all the values in Table 20 and Table 21 according to Formula 1, but only needs to store or calculate according to Formula 1 in Table 20 and Table 21 The value of one column and the value of one row (for example, the bolded values in Table 20 and Table 21), then the value of one row in Table 20 and Table 21 is the value of one row in the turbo interleaving sequence of W row and L column, in Table 20 The value of one column is the value of an odd-numbered column of the turbo interleaving sequence of W rows and L columns, and the value of one column in Table 21 is the value of an even-numbered column of the turbo interleaved sequence of W rows and L columns. Other values in Table 20 and Table 21 can be derived by using a cyclic shifter and an adder, thus saving occupied storage resources or reducing computational complexity. Further, it is even only necessary to store or calculate the two values of one column (which can be two adjacent values or non-adjacent two values) and the value of one row according to formula 1, so as to further save the occupied storage resources or reduce the calculation the complexity.

S702, the parameter generator 54 modulates the value of one row of the Turbo interleaving sequence of the W row and L column to L to obtain the turbo offset value corresponding to the odd column and the turbo offset value corresponding to the even column; Take the quotient to get the base sequence corresponding to the even column, take the quotient of the value of an odd column to L to get the base sequence corresponding to the odd column; take the value of a row to L to get the shift reference value corresponding to the odd column and the corresponding to the even column. Shift reference value.

The Turbo offset value represents the relative position within a row of the values of a row in the Turbo interleaved sequence. Specifically, the parameter generator 54 may modulo L the values of a row of L/2 odd columns in the turbo interleaving sequence to obtain L/2 turbo offset values corresponding to the odd columns, and the parameter generator 54 may The value of one row of L/2 even-numbered columns is modulo L to obtain L/2 Turbo offset values corresponding to the even-numbered columns. At this time, the values of one row in the Turbo interleaving sequence of W rows and L columns can be stored or calculated according to formula 1, instead of storing or calculating all the values, which can save occupied storage resources or reduce computational complexity.

Exemplarily, for an odd-numbered column, the parameter generator 54 may modulo L(760) on the value of the first row in Table 20 to obtain L/2 turbo offsets corresponding to the odd-numbered column as shown in Table 22. value. For even-numbered columns, the parameter generator 54 may modulo L(760) on the values in the first row in Table 21 to obtain L/2 turbo offset values corresponding to the even-numbered columns as shown in Table 23.

Table 22

	0	2	4	6	…	758
Turbo offset value	0	94	188	282	…	666

Table 23

	1	3	5	7	…	759
Turbo offset value	237	331	425	519	…	143

The base sequence of the turbo interleaved sequence represents the relative position of the values of a column in the turbo interleaved sequence within a column.

Specifically, in a possible implementation manner, the parameter generator 54 may obtain a set of base sequences (with W values) by quoting the value of an odd-numbered column in the turbo interleaving sequence to L, and use an even-numbered sequence in the turbo interleaving sequence to obtain a set of base sequences (with W values). Quoting the values of the columns against L yields another set of basis sequences (with W values). At this time, the values of one even column and one odd column in the turbo interleaving sequence of W rows and L columns can be stored or calculated according to formula 1, instead of storing or calculating all the values, which can save occupied storage resources or reduce computational complexity .

Exemplarily, for an odd-numbered column, the parameter generator 54 may obtain a set of base sequences as shown in Table 24 by taking the quotient of the value of the first column in Table 20 against L(760). For even columns, parameter generator 54 may modulo L(760) the values of the first column in Table 20 to obtain another set of basis sequences as shown in Table 25.

Table 24

	0
first paragraph	0
second paragraph	7
third paragraph	6
fourth paragraph	5
fifth paragraph	4
sixth paragraph	3
paragraph 7	2
eighth paragraph	1

Table 25

	1
first paragraph	0
second paragraph	3
third paragraph	6
fourth paragraph	1
fifth paragraph	4
sixth paragraph	7
paragraph 7	2
eighth paragraph	5

In another possible implementation, the parameter generator 54 may obtain two base sequences by taking the quotient of two values in an odd-numbered column of the turbo interleaving sequence against L, and according to the two base sequences (which may be adjacent or not Adjacent) of the modulo (modulo W) difference to obtain the step value of the adjacent base sequences in the same column, and then obtain a set of base sequences according to the step value of the adjacent base sequences and one of the two base sequences base sequence (with W values). Similarly, the parameter generator 54 can obtain two base sequences by taking the quotient of two values in an even-numbered column of the Turbo interleaved sequence to L, and according to the modulo ( The modulo is W) difference value to obtain the step value of adjacent base sequences in the same column, and then another group of base sequences is obtained according to the step value of adjacent base sequences and one of the two base sequences (as a benchmark) (with W values). At this time, two values and step values in one column of the turbo interleaving sequence of W rows and L columns can be stored or calculated according to formula 1, instead of storing or calculating all the values, which can save occupied storage resources or reduce computational complexity .

The specific formula is (phi_ini+a*step) mod W, where phi_ini represents a base sequence as a benchmark, step is the step value of the adjacent base sequence, and a is the row where the base sequence to be calculated is located and the base sequence used as the benchmark The difference in the row.

It should be noted that the difference value of the modulo (modulo W) of two adjacent base sequences is equal to the step value of the adjacent base sequence; the difference value of the modulo (modulo W) of two non-adjacent base sequences , equal to b times the step value of adjacent base sequences, where b is the difference between the rows where the two base sequences are located.

Exemplarily, as shown in Table 24, the modulo is 8, the modulo difference between the second value and the first value is 7-0=7, and the modulo difference between the third value and the second value is The value is 6+8-7=7, the modulo difference between the fourth value and the third value is 5+8-6=7, and so on, the modulo difference between two adjacent values is 7, that is, the step value of the adjacent base sequence is 7. Therefore, it can be deduced that this group of base sequences is 0, 7, 6, 5, 4, 3, 2, and 1 through the step value 7 of the adjacent base sequence and the first base sequence 0, and Table 24 can also be obtained.

Exemplarily, as shown in Table 25, the modulo is 8, the modulo difference between the second value and the first value is 3-0=3, and the modulo difference between the third value and the second value is The value is 6-3=3, the modulo difference between the fourth value and the third value is 1+8-6=3, and so on, the modulo difference between two adjacent values is 3, That is, the step value of adjacent base sequences is 3. Therefore, it can be deduced that this group of base sequences is 0, 3, 6, 1, 4, 7, 2, and 5 through the step value 3 of the adjacent base sequence and the first base sequence 0, and Table 25 can also be obtained.

By storing the step value, the occupied storage resources can be saved or the computational complexity can be reduced. As shown in Table 26, the relationship between the parity step values of each code length when W=8 is listed. The odd step value refers to the step value of adjacent base sequences in the odd-numbered column, and the even-step value refers to the step value of the adjacent sequence in the even-numbered column.

Table 26

The shift reference value represents the relative position of a column of values in a row of the turbo interleaved sequence. Specifically, the parameter generator 54 can obtain L/2 shift reference values corresponding to the odd-numbered columns by taking the quotient of the value of a row of the odd-numbered columns in the turbo interleaving sequence to L; the parameter generator 54 can The value of a row is quotient to L to obtain L/2 shift reference values corresponding to the even columns. At this time, the values of one row in the Turbo interleaving sequence of W rows and L columns can be stored or calculated according to formula 1, instead of storing or calculating all the values, which can save occupied storage resources or reduce computational complexity.

Exemplarily, for an odd-numbered column, the parameter generator 54 can obtain L/2 shift references corresponding to the odd-numbered column as shown in Table 27 by taking the quotient of the value of the first row in Table 20 against L (760). value. For even-numbered columns, the parameter generator 54 may obtain L/2 shift reference values corresponding to the even-numbered columns as shown in Table 28 by taking the quotient of the values in the first row in Table 21 against L (760).

Table 27

	0	2	4	6	…	758
Shift reference value	0	1	4	1	…	7

Table 28

	1	3	5	7	…	759
Shift reference value	0	2	6	4	…	3

S703, the first locator 55 inputs the shift reference value and the base sequence corresponding to the odd-numbered columns, and outputs L/2 Turbo cyclic shift values corresponding to the odd-numbered columns; the second locator 56 inputs the shift reference value corresponding to the even-numbered columns value and base sequence, output the L/2 turbo cyclic shift values corresponding to the even columns.

Exemplarily, for an odd-numbered column, the first locator 55 compares the value in Table 27 with the value in Table 24, thereby determining the L/2 turbo cycle shifts corresponding to the odd-numbered column as shown in Table 29. bit value. For example, the value 1 in the column "2" in Table 27 is obtained by rotating the value 1 in Table 24 upward by 7 bits, so the corresponding turbo cyclic shift value is 7. And so on.

Exemplarily, for even-numbered columns, the second locator 56 compares the values in Table 28 with the values in Table 25 to determine the L/2 turbo cycle shifts corresponding to the even-numbered columns as shown in Table 30. bit value. For example, the 2 in the "3" column in Table 28 is obtained by rotating the value 2 in Table 25 upward by 6 bits, so the corresponding turbo cyclic shift value is 6. And so on.

Table 29

	0	2	4	6	…	758
Turbo cyclic shift value	0	7	4	7	…	1

Table 30

	1	3	5	7	…	759
Turbo cyclic shift value	0	6	2	4	…	1

Step S601 will be described below with reference to FIG. 8. As shown in FIG. 8, step S601 includes S6011-S6012.

S6011. When the cyclic shift network 51 receives the turbo decoding information, the first cyclic shifter 511 inputs the base sequence corresponding to one odd-numbered column of the turbo interleaved sequence and the turbo of multiple (L/2) odd-numbered columns of the turbo interleaved sequence The cyclic shift value and the cyclic shift calculation are performed to output the interleaving positions of more than (L/2) odd columns. The second cyclic shifter 512 inputs the base sequence corresponding to one even-numbered column of the turbo interleaved sequence and the turbo cyclic shift values of multiple (L/2) even-numbered columns of the turbo interleaved sequence, and performs cyclic shift calculation to output multiple (L/2) even-numbered columns of the turbo interleaved sequence. L/2) interleaving positions of even columns.

Because there is a cyclic shift relationship between the interleaving positions located in odd columns, and there is also a cyclic shift relationship between interleaving positions located in even columns, and both can be obtained by cyclic shift of the base sequence, so the base sequence is calculated according to Turbo The interleaving position of any column can be obtained by cyclically shifting the cyclic shift value.

Exemplarily, for an odd-numbered column, the first cyclic shifter 511 performs a cyclic shift on the base sequence in Table 24 according to the Turbo cyclic shift value in Table 29, so as to obtain the corresponding odd-numbered column as shown in Table 31. The L/2 column interleaving position. For example, for the base sequences 0, 7, 6, 5, 4, 3, 2, and 1 in Table 24, according to the Turbo cyclic shift value 7 located in the "2" column in Table 29, rotate up 7 bits to obtain the "2" column in Table 31. 2" column for interleaving positions 1, 0, 7, 6, 5, 4, 3, 2. And so on.

Exemplarily, for an even-numbered column, the second cyclic shifter 512 performs a cyclic shift on the base sequence in Table 25 according to the Turbo cyclic shift value in Table 30, so as to obtain the corresponding even-numbered column as shown in Table 32. The L/2 column interleaving position. For example, the base sequences 0, 3, 6, 1, 4, 7, 2, and 5 in Table 25 are rotated upward by 6 bits according to the Turbo cyclic shift value 6 located in the "3" column in Table 30 to obtain the "3" column in Table 32. Interleave positions 2, 5, 0, 3, 6, 1, 4, 7 for 3" columns. And so on.

Table 31

	0	2	4	6	…	758
Interleaving position (first segment)	0	1	4	1	…	7
Interleaving position (second paragraph	7	0	3	0		6
Interleaving position (third paragraph)	6	7	2	7		5
Interleaving position (fourth segment)	5	6	1	6		4
Interleaving position (fifth paragraph)	4	5	0	5		3
Interleaving position (sixth paragraph)	3	4	7	4		2
Interleaving position (seventh paragraph)	2	3	6	3		1
Interleaving position (section 8)	1	2	5	2		0

Table 32

	1	3	5	7	…	759
Interleaving position (first segment)	0	2	6	4	…	3
Interleaving Position (Second Section)	3	5	1	7		6
Interleaving position (third paragraph)	6	0	4	2		1
Interleaving position (fourth segment)	1	3	7	5		4
Interleaving position (fifth paragraph)	4	6	2	0		7
Interleaving position (sixth paragraph)	7	1	5	3		2
Interleaving position (seventh paragraph)	2	4	0	6		5
Interleaving position (section 8)	5	7	3	1		0

S6012, when the cyclic shift network 51 receives the turbo decoding information, the first adder 513 inputs the interleaving positions of the multiple (L/2) odd-numbered columns and the turbo offset values of the multiple (L/2) odd-numbered columns, and outputs the output Odd columns of the turbo interleaved sequence. The second adder 514 inputs the interleaving positions of the multiple (L/2) even-numbered columns and the turbo offset values of the multiple (L/2) even-numbered columns, and outputs the even-numbered columns of the turbo interleaved sequence.

Since it has been explained above that the turbo offset values of the same column of Turbo interleaving sequences are the same, any turbo offset value in the first row represents the turbo offset value of the same column.

Exemplarily, for odd-numbered columns, the first adder 513 multiplies the values of the interleaving positions in Table 32 by L(760) respectively to obtain the values shown in Table 33, and then divides the values shown in Table 33 by column. Adding the Turbo offset values shown in Table 22, the odd-numbered columns of the Turbo interleaved sequence shown in Table 20 are obtained.

Exemplarily, for an even-numbered column, the second adder 514 multiplies the values of the interleaving positions in Table 33 by L(760) respectively to obtain the values shown in Table 34, and then divides the values shown in Table 34 by column. Adding the Turbo offset values shown in Table 23, the even-numbered columns of the Turbo interleaving sequence shown in Table 21 are obtained.

Table 33

	0	2	4	6	…	758
first paragraph	0	760	3040	760	…	5320
second paragraph	5320	0	2280	0	…	4560
third paragraph	4560	5320	1520	5320	…	3800
fourth paragraph	3800	4560	760	4560	…	3040
fifth paragraph	3040	3800	0	3800	…	2280
sixth paragraph	2280	3040	5320	3040	…	1520
paragraph 7	1520	2280	4560	2280	…	760
eighth paragraph	760	1520	3800	1520	…	0

Table 34

	1	3	5	7	…	759
first paragraph	0	1520	4560	3040	…	2280
second paragraph	2280	3800	760	5320	…	4560
third paragraph	4560	0	3040	1520	…	760
fourth paragraph	760	2280	5320	3800	…	3040
fifth paragraph	3040	4560	1520	0	…	5320
sixth paragraph	5320	760	3800	2280	…	1520
paragraph 7	1520	3040	0	4560	…	3800
eighth paragraph	3800	5320	2280	760	…	0

S602. The interleaving/de-interleaving circuit 52 receives the Turbo a posteriori data and the Turbo interleaving sequence, performs interleaving and de-interleaving processing, and obtains Turbo data.

In the turbo mode (the selector 57 is switched to the state "0"), the interleaving/deinterleaving circuit 52 receives the turbo posterior data and the turbo interleaving sequence, performs interleaving and deinterleaving processing, and obtains turbo data.

The first interleaver/deinterleaver 521 receives the turbo posterior data and the odd columns of the turbo interleaving sequence, performs interleaving and deinterleaving processing, and obtains the turbo data of the odd columns. The second interleaver/deinterleaver 522 receives the turbo a posteriori data and the even columns of the turbo interleaving sequence, performs interleaving and deinterleaving processing, and obtains turbo data of the even columns.

S603. The decoding circuit 53 selectively decodes the LDPC data or the Turbo data.

In the LDPC mode (the selector 57 is switched to the state "1"), the decoding circuit 53 combines the odd-numbered LDPC data and the even-numbered LDPC data, and decodes the combined LDPC data.

In the turbo mode (the selector 57 is switched to the state "0"), the decoding circuit 53 combines the turbo data of the odd-numbered columns and the turbo data of the even-numbered columns, and decodes the combined turbo data.

The common mode decoding circuit shown in Figure 5 can decode the data to be decoded according to the even and odd columns of the turbo interleaving sequence. If the number of turbo interleaving sequences is large, the turbo interleaving sequence can also be divided into multiple sections, and a common mode decoding circuit can be added. The number of , each common-mode decoding circuit is used to process even and odd columns in a Turbo interleaved sequence.

Exemplarily, as shown in FIG. 9, M*2^(n+1) sub-circuits in the common-mode decoding circuit shown in The sub-circuits include a first cyclic shifter 511, a first adder 513, a first interleaver/de-interleaver 521, and a first locator 55. These sub-circuits are commonly coupled to the same decoding circuit 53 and belong to a common-mode decoding The two sub-circuits of the circuit are used to process a section of Turbo interleaving sequence of W rows and L columns in the Turbo interleaving sequence whose code length is M*W*L*2^n. One of the two sub-circuits is used to process a section of Turbo interleaving. The odd-numbered column of the sequence, and the other is used to process the even-numbered column of a Turbo interleaved sequence. The decoding circuit 53 decodes the data output by all the subcircuits after combining, so as to realize the code length of M*W*L*2^n The Turbo interleaved sequence is decoded.

In the common-mode decoding circuit, digital baseband, radio frequency transceiver, and decoding method provided by the embodiments of this application, the cyclic shift network can selectively receive LDPC decoding information and perform cyclic shift calculation to output LDPC data, or receive Turbo decoding code information and perform a cyclic shift calculation to output a turbo interleaved sequence. The interleaving/de-interleaving circuit receives the Turbo a posteriori data and the Turbo interleaving sequence, performs interleaving and de-interleaving processing, and obtains Turbo data. The decoding circuit selectively decodes the LDPC data or the Turbo data. Realize LDPC code and Turbo code multiplexing cyclic shift network for decoding, so resources are saved. In addition, in the process of obtaining the Turbo interleaved sequence by restoring the input base sequence, the turbo cyclic shift value and the turbo offset value, the input base sequence, the turbo cyclic shift value and the turbo offset value are respectively the odd numbers of the turbo interleaved sequence. The columns correspond to the even columns, because there is a cyclic shift relationship between the interleaving positions located in the odd columns, and there is also a cyclic shift relationship between the interleaving positions located in the even columns, so that the common mode decoding circuit can be applied to high parallelism. degree of turbo interleaving sequence.

Embodiments of the present application also provide a computer-readable storage medium, where a computer program is stored in the computer-readable storage medium, and when it runs on a computer or a processor, the computer or the processor causes the computer or the processor to execute the steps in FIGS. 6 to 8 . corresponding method.

Embodiments of the present application also provide a computer program product containing instructions, when the instructions are executed on a computer or a processor, the computer or the processor causes the computer or processor to execute the corresponding methods in FIGS. 6-8 .

It should be understood that, in various embodiments of the present application, the size of the sequence numbers of the above-mentioned processes does not mean the sequence of execution, and the execution sequence of each process should be determined by its functions and internal logic, and should not be dealt with in the embodiments of the present application. implementation constitutes any limitation.

Those of ordinary skill in the art can realize that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Skilled artisans may implement the described functionality using different methods for each particular application, but such implementations should not be considered beyond the scope of this application.

Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process of the above-described systems, devices and units may refer to the corresponding processes in the foregoing method embodiments, which will not be repeated here.

In the several embodiments provided in this application, it should be understood that the disclosed systems, devices and methods may be implemented in other manners. For example, the device embodiments described above are only illustrative. For example, the division of the units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components may be combined or Can be integrated into another system, or some features can be ignored, or not implemented. On the other hand, the shown or discussed mutual coupling or direct coupling or communication connection may be through some interfaces, indirect coupling or communication connection of devices or units, and may be in electrical, mechanical or other forms.

The units described as separate components may or may not be physically separated, and components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution in this embodiment.

In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically alone, or two or more units may be integrated into one unit.

In the above-mentioned embodiments, it may be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using a software program, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on the computer, all or part of the processes or functions described in the embodiments of the present application are generated. The computer may be a general purpose computer, special purpose computer, computer network, or other programmable device. The computer instructions may be stored in or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be downloaded from a website site, computer, server, or data center Transmission to another website site, computer, server or data center via wired (eg coaxial cable, optical fiber, Digital Subscriber Line, DSL) or wireless (eg infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that can be accessed by a computer or data storage devices including one or more servers, data centers, etc. that can be integrated with the medium. The usable medium may be a magnetic medium (eg, a floppy disk, a hard disk, a magnetic tape), an optical medium (eg, a DVD), or a semiconductor medium (eg, a Solid State Disk (SSD)), and the like.

The above are only specific embodiments of the present application, but the protection scope of the present application is not limited to this. should be covered within the scope of protection of this application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims (19)

1. A common-mode decoding circuit, characterized in that it includes:

   A cyclic shift network for selectively receiving low density parity check code LDPC decoding information and performing cyclic shift calculation to output LDPC data, or, receiving image dial Turbo decoding information and performing cyclic shift calculation to output Turbo Interleaving sequence; wherein, the LDPC decoding information includes: LDPC posterior data and LDPC cyclic shift value; the Turbo decoding information includes: the base sequence, Turbo A cyclic shift value and a Turbo offset value, the base sequence is the result of taking a quotient between the values of an even column or an odd column in the Turbo interleaving sequence, where L is the length of one row of the Turbo interleaving sequence;

   Interleaving/de-interleaving circuit for receiving Turbo a posteriori data and the Turbo interleaving sequence, performing interleaving and de-interleaving processing to obtain Turbo data;

   A decoding circuit for selectively decoding the LDPC data or the Turbo data.
2. The common mode decoding circuit according to claim 1, wherein the cyclic shift network comprises a first cyclic shifter and a second cyclic shifter.
3. The common-mode decoding circuit according to claim 2, wherein when the cyclic shift network receives the turbo decoding information:

   The first cyclic shifter is configured to input a base sequence corresponding to one odd-numbered column of the turbo interleaved sequence and turbo cyclic shift values of a plurality of odd-numbered columns of the turbo interleaved sequence, and perform a cyclic shift calculation to output the Describe the interleaving positions of a plurality of odd-numbered columns;

   The second cyclic shifter is configured to input a base sequence corresponding to one even-numbered column of the Turbo interleaved sequence and the turbo cyclic shift values of a plurality of even-numbered columns of the Turbo interleaved sequence, and perform cyclic shift calculation to output the The interleaving positions of the multiple even-numbered columns are described.
4. The common-mode decoding circuit according to claim 3, wherein the cyclic shift network further comprises a first adder and a second adder,

   The first adder is configured to input the interleaving positions of the plurality of odd-numbered columns and the Turbo offset values of the plurality of odd-numbered columns, and output the odd-numbered columns of the Turbo interleaving sequence;

   The second adder is configured to input the interleaving positions of the multiple even-numbered columns and the turbo offset values of the multiple even-numbered columns, and output the even-numbered columns of the turbo interleaving sequence.
5. The common-mode decoding circuit according to claim 3 or 4, wherein the common-mode decoding circuit further comprises a parameter generator, a first locator and a second locator:

   The parameter generator is used to calculate the values of a row, an even column and an odd column of the Turbo interleaving sequence; the value of the row is modulo L to obtain the Turbo offset value corresponding to the odd column and the corresponding Turbo offset of the even column. Turbo offset value; take the quotient of the value of the even column to L to obtain the basis sequence corresponding to the even column, and take the quotient of the value of the odd column to L to obtain the basis sequence corresponding to the odd column; The value of L takes the quotient to obtain the shift reference value corresponding to the odd column and the shift reference value corresponding to the even column;

   The first locator is used to input the shift reference value and the base sequence corresponding to the odd-numbered column, and output the Turbo cyclic shift value corresponding to the odd-numbered column;

   The second locator is used for inputting the shift reference value and base sequence corresponding to the even-numbered columns, and outputting the turbo cyclic shift value corresponding to the even-numbered columns.
6. The common-mode decoding circuit according to any one of claims 3-5, wherein the interleaving/deinterleaving circuit comprises a first interleaving/deinterleaving device and a second interleaving/deinterleaving device;

   The first interleaving/deinterleaving device is used for receiving Turbo a posteriori data and odd columns of the Turbo interleaving sequence, and performing interleaving and deinterleaving processing to obtain the Turbo data of the odd columns;

   The second interleaver/deinterleaver is configured to receive turbo a posteriori data and even columns of the turbo interleaving sequence, perform interleaving and deinterleaving processing, and obtain even columns of turbo data.
7. The common-mode decoding circuit according to claim 6, wherein the decoding circuit is configured to combine the turbo data of the odd-numbered columns and the turbo data of the even-numbered columns, and decode the combined turbo data .
8. The common-mode decoding circuit according to claim 2, wherein when the cyclic shift network receives the LDPC decoding information, the first cyclic shifter is configured to input odd-numbered LDPC posterior data and corresponding The LDPC cyclic shift value and the cyclic shift calculation are performed to output odd-numbered LDPC data; the second cyclic shifter is used to input the even-numbered LDPC posterior data and the corresponding LDPC cyclic shift value and perform cyclic shift calculation. , to output even-numbered LDPC data.
9. The common-mode decoding circuit according to claim 8, wherein the decoding circuit is configured to combine the odd-numbered LDPC data and the even-numbered LDPC data, and decode the combined LDPC data.
10. A digital baseband, characterized in that it includes a digital processing circuit and the common-mode decoding circuit according to any one of claims 1-9, wherein the digital processing circuit is used for digitally processing digital signals of a receiving link to obtain Based on the data to be decoded based on the Turbo code or the data to be decoded based on the low density parity check code (LDPC) code, the common mode decoding circuit is configured to decode the data to be decoded to output a decoding result.
11. A radio frequency transceiver, characterized in that it includes a receiving analog baseband and a digital baseband as claimed in claim 10 ; the receiving analog baseband is used to perform analog-to-digital conversion on a low-frequency modulated signal of a receiving link to obtain a signal of the receiving link. A digital signal, and the digital baseband is used to digitally process and decode the digital signal to obtain a decoding result.
12. A decoding method, characterized in that, applied to the common-mode decoding circuit according to any one of claims 1-9, the method comprising:

    Selectively receive low-density parity check code LDPC decoding information and perform cyclic shift calculation to output LDPC data, or receive image dial Turbo decoding information and perform cyclic shift calculation to output Turbo interleaved sequence; wherein, the The LDPC decoding information includes: LDPC posterior data and LDPC cyclic shift value; the Turbo decoding information includes: the base sequence, the Turbo cyclic shift value and the Turbo offset corresponding to the odd and even columns of the Turbo interleaved sequence, respectively. Shift value, the base sequence is the result of taking a quotient between the values of an even column or an odd column in the Turbo interleaving sequence, where L is the length of a row of the Turbo interleaving sequence;

    Receive Turbo a posteriori data and the Turbo interleaving sequence, perform interleaving and de-interleaving processing, and obtain Turbo data;

    The LDPC data or the Turbo data is selectively decoded.
13. The method according to claim 12, wherein when receiving the turbo decoding information, the method further comprises:

    Inputting a base sequence corresponding to an odd-numbered column of the Turbo interleaving sequence and the turbo cyclic shift values of a plurality of odd-numbered columns of the Turbo interleaving sequence and performing a cyclic shift calculation to output the interleaving positions of the plurality of odd-numbered columns;

    A base sequence corresponding to one even-numbered column of the turbo interleaving sequence and turbo cyclic shift values of multiple even-numbered columns of the turbo interleaving sequence are input, and a cyclic shift calculation is performed to output the interleaving positions of the multiple even-numbered columns.
14. The method according to claim 13, wherein the receiving the picture dialing turbo decoding information and performing a cyclic shift calculation to output a Turbo interleaved sequence, comprising:

    inputting the interleaving positions of the plurality of odd-numbered columns and the Turbo offset values of the plurality of odd-numbered columns, and outputting the odd-numbered columns of the Turbo interleaving sequence;

    The interleaving positions of the plurality of even-numbered columns and the turbo offset values of the plurality of even-numbered columns are input, and the even-numbered columns of the turbo interleaving sequence are output.
15. The method of claim 13 or 14, further comprising:

    Calculate the value of a row, an even column and an odd column of the Turbo interleaved sequence; take the value of the row to L modulo to obtain the Turbo offset value corresponding to the odd column and the Turbo offset value corresponding to the even column; Take the quotient of the value of an even column to L to obtain the basis sequence corresponding to the even column, take the quotient of the value of the odd column to L to obtain the basis sequence corresponding to the odd column; take the quotient of the value of the row to L to obtain the odd number The shift reference value corresponding to the column and the shift reference value corresponding to the even column;

    Input the shift reference value and base sequence corresponding to the odd-numbered column, and output the Turbo cyclic shift value corresponding to the odd-numbered column;

    Input the shift reference value and base sequence corresponding to the even-numbered column, and output the turbo cyclic shift value corresponding to the even-numbered column.
16. The method according to any one of claims 13-15, wherein the receiving Turbo a posteriori data and the Turbo interleaving sequence, performing interleaving and de-interleaving processing to obtain Turbo data, comprising:

    Receive Turbo posterior data and odd-numbered columns of the Turbo interleaving sequence, carry out interleaving and de-interleaving processing, and obtain the Turbo data of odd-numbered columns;

    Receive turbo posterior data and even columns of the turbo interleaving sequence, perform interleaving and deinterleaving processing, and obtain even columns of turbo data.
17. The method according to claim 16, wherein the selectively decoding the LDPC data or the Turbo data comprises:

    The turbo data of the odd-numbered columns and the turbo data of the even-numbered columns are combined, and the combined turbo data is decoded.
18. The method according to claim 12, wherein, when receiving the LDPC decoding information, the receiving the low density parity check code LDPC decoding information and performing a cyclic shift calculation to output the LDPC data, comprising:

    Input odd-numbered LDPC posterior data and corresponding LDPC cyclic shift value and perform cyclic shift calculation to output odd-numbered LDPC data; input even-numbered LDPC posterior data and corresponding LDPC cyclic shift value and perform cyclic shift calculation , to output even-numbered LDPC data.
19. The method according to claim 18, wherein the selectively decoding the LDPC data or the Turbo data comprises:

    The odd-numbered LDPC data and the even-numbered LDPC data are combined, and the combined LDPC data is decoded.

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