CN103888224B - Parallel realization method and device for LTE system Turbo code-inner interleaving - Google Patents
Parallel realization method and device for LTE system Turbo code-inner interleaving Download PDFInfo
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Abstract
The invention provides and discloses a method and device through which via table look-up and simple shifting and arithmetic operation, Turbo code-inner interleaving is achieved in a parallel mode. Data are stored into an input buffering zone in a column-preferential mode, a row of data are read according to row address indexing from the input buffering zone each time, then interleaving operation is carried out according to column address indexing, and Turbo code-inner interleaving is achieved. By analyzing 188 kinds of different code block lengths stated in the LTE physical layer protocol 36.212, the following law is summarized, namely equal-difference features exist in the front and the back of row address indexing under the situation of different code block lengths, and meanwhile when column address indexing is computed, the offset delta and the difference value N exist between the column address indexing of each row of data and the first row. According to the method and device, the computing time of a Turbo code-inner interleaving machine can be obviously shortened, quick Turbo coding and decoding can be achieved, the data throughput rate of a wireless communication system is improved, and the method and device can be widely used in a 4G base station and mobile equipment.
Description
Technical field
It is the present invention relates to communication technical field, more particularly to a kind of for interweaving simultaneously in LTE system Turbo coding and decoding
Row implementation method and device.
Background technology
With science and technology it is growing, wireless communication technology is widely applied.But user data is through aerial
When interface is transmitted, can be disturbed by various noises and signal, cause signal error or lose.In order to improve signal transmission
Quality, increases the reliability of wireless communication system, it usually needs communication system has the ability of certain error-detection error-correction.
In Long Term Evolution (Long Term Evolution, LTE) system, a kind of widely used error correcting code is exactly
Turbo code.Turbo code is born in 1993, is proposed on the basis of convolutional code and concatenated code first by Berrou et al., and which is special
It is that encoding and decoding complexity is high to levy, and time delay is big, but error performance is excellent, be suitable for big data quantity long code block and to delay requirement not
High data transfer.It can meet the randomness condition in Shannon Channel coding theory well, and employ iterative decoding
Mode obtaining coding gain, therefore, it is possible to obtain the limiting performance for approaching shannon limit.
Meanwhile, in order to improve the transmission characteristic of mobile communication, the impact that signal fadeout brings is reduced, can be compiled using interweaving
Code technology.Interweaving encoding technology is exactly to cause the bursty errors of digital data transmission, using interweaving encoding technology carry out from
Dispersion is processed and corrects the mistake.The knot of the Turbo encoder of the regulation of 3GPPLTE PHYs 36.212 is shown in Fig. 1
Composition, is made up of two component coders and an interleaver, and wherein interleaver plays crucial work in Turbo code
With directly affecting the decoding performance of Turbo code.The interleaver that LTE is adopted, is twice replaced polynomial (Quadratic
Polynomial Permutation, QPP) interleaver, with " maximum contention-free " characteristic, its expression formula is
∏(i)=(f1·i+f2·i2)modK
Wherein, i=0,1 ..., K-1.K is code block length, f1、f2Value it is relevant with code block size K value, design parameter is by LTE
In PHY 36.212,5.1.3.2.3 tables 5.1.3-3 is defined.
The implementation of interleaver is varied, and most straightforward approach is exactly to be calculated according to formula successively, due to including taking advantage of
Method is operated and modulo operation, and this calculation efficiency is very low.The existing mode for realizing Turbo code interleaver is generally
Can classify as and be calculated according to recurrence formula, save multiplication operation, improve processing speed.As Application No. 201210177005.2,
In the Chinese invention patent prospectus of entitled " a kind of realization of the parallel Turbo code interleaving device for LTE "
Propose one kind and iterative relations of the ∏ (i+8) and ∏ (i) between is obtained by recurrence formula, after being obtained by 8 kinds of current states
Continue 8 kinds of states, realize that a clock cycle completes the output of 8 interleaving address, its 8 interleaving address read 8 pieces of contents respectively
Identical RAM simultaneously obtains the output of 8 bit datas by main control module process.And for example Application No. 201010293964.1, invention name
One kind is proposed in the Chinese invention patent prospectus of " Turbo code parallel interleaver and parallel deinterleaving method " referred to as by row
Parallel read data and data are gone intersection Parallel Implementation Turbo code in the method that interweaves, by positive and reverse
Basic interleaving address ∏ (i) of recursion, and the L modulus set to which and ask business to obtain the row address of column address and first trip respectively, then
According to the recurrence relation of row address between before leaving, the row address of all rows is obtained respectively by forward and backward recursion, its described control
Device processed enters every trade by the row address of each row for concurrently reading a column data and the data of reading being produced according to cross unit
Intersect, realize interweaving in the row of data and in the ranks interweaving, complete whole interleaving process.
In real work, it is corresponding that inventor has found that the implementation of existing Turbo code interleaver be present：
Such as " a kind of realization of the parallel Turbo code interleaving device for LTE ", although its efficiency can improve 8 times, for
188 kinds of interleavers of the regulation of LTE PHYs 36.212 are realized using 8 parallel-by-bits, it is clear that had its limitation, and generated friendship
The process for knitting address is still serial execution；And such as " Turbo code parallel interleaver and the parallel deinterleaving method ", which is proposed
Twice replaced thought be worth affirmative, but its rank addresses every time needed for displacement is to be calculated successively to get by recurrence formula,
Its improved efficiency still has limitation.
The content of the invention
(1) technical problem to be solved
In order to effectively reduce the time of realizing of Turbo code interleaver in LTE system, improve Turbo code encoder and translate
The efficiency of code device, lifts the data throughput of existing 4G base stations and user terminal.
(2) technical scheme
To solve above-mentioned technical problem, the present invention proposes a kind of method interweaved in Parallel Implementation Turbo code, data is pressed
The preferential mode of row is stored in an input block, then carries out multiple replacement operator, and each replacement operator is from this
Row address index is pressed in input block and reads in data line, operation is interleaved further according to column address index, realizes Turbo code
Interior intertexture.
A kind of specific embodiment of the invention, line number R and columns C of the input block is according to following rule
Calculated：
C=K/R
A kind of specific embodiment of the invention, by row ground required during different code block lengths K corresponding column permutation
Location index is stored in a form, when first time replacement operator is carried out, column address index be according to code block length K simultaneously
Obtained by tabling look-up.
A kind of specific embodiment of the invention, the column address index are according to partially by the column address index of first trip
Shifting amount △ and difference N are calculated.
A kind of specific embodiment of the invention, obtains the column address index T0 of the first row and often goes relative to the
After side-play amount △ and difference N of a line, shifting function is circulated according to side-play amount △ to T0, and addition is completed according to difference N
Operation, obtains the column address index of corresponding line.
A kind of specific embodiment of the invention, column address index are obtained according to different code block lengths K statistics.
A kind of specific embodiment of the invention, statistics obtain for from the side-play amount of different code block lengths K and
Difference.
A kind of specific embodiment of the invention, the degree of parallelism of the implementation interweaved in the Turbo code is by counting
Determine according to bit wide L of the columns C and interleave unit for being stored in input block, the computing formula of its degree of parallelism P is P=C/ceil (C/
L), ceil () is represented carries out the operation that rounds up to data.
The present invention also proposes the device interweaved in a kind of Parallel Implementation Turbo code, including rank addresses signal generating unit, full friendship
Unit, input block are knitted, the input block storage needs to do the input stream of intertexture computing；The rank addresses life
Two parts work is completed into unit：First, column address index required during different code block lengths K corresponding column permutation is stored in
In one form, when first time replacement operator is carried out, the column address index is according to code block length K and by tabling look-up
Arrive；Second, the column address index of data to be decoded in calculating often row input block, completes the intertexture needed for second displacement
Index；The full interleave unit is indexed according to the column address that the rank addresses signal generating unit is transmitted, and every data line is carried out
Full intertexture computing.
A kind of specific embodiment of the invention, also including output buffer, which is used to store the full list that interweaves
Output data.
(3) beneficial effect
The present invention is not required to computation index address direct by the simple algorithm calculations such as table lookup operation and displacement, addition
The function of Turbo interleavers, with following usefulness：
1) table lookup operation realization is simple, and list item storage is taken up space less, it is easy to accomplish.
2) index from input block by row address and read in data, be not required to extra computation and complete displacement behaviour for the first time
Make.
3) only just can complete the intertexture of multiple data by displacement, addition and the operation that interweaves parallel, improve in Turbo
The degree of parallelism that interleaver is realized, reduces the execution time.
Description of the drawings
Fig. 1 is the Turbo encoder structure chart applied in LTE technologies；
Fig. 2 is a kind of specific embodiment structure chart of Turbo code interleaver of the invention；
Fig. 3 is the flowchart interweaved in a kind of Turbo code of the invention；
Fig. 4 is that a kind of specific embodiment of the invention interweaves operation chart entirely；
Input data relief area schematic diagram when Fig. 5 is K=216 in a kind of specific embodiment of the invention；
Moment data output buffer area schematic diagram when Fig. 6 is K=216 in a kind of specific embodiment of the invention.
Specific embodiment
The present invention proposes a kind of Parallel Implementation method for rapidly and efficiently completing to interweave in Turbo code and calculating, and the method is only
Including table look-up and shift, the simple arithmetical operation such as addition and intertexture, realize beneficial to Embedded Mobile processor, shorten when performing
Between, improve the data throughput of 4G base stations and terminal unit.
To make the object, technical solutions and advantages of the present invention become more apparent, below in conjunction with specific embodiment, and reference
Accompanying drawing, the present invention is described in further detail.
Fig. 1 is the structural representation for being applied to Turbo encoder in LTE PHYs.Its encoder bit rate is 1/3, right
In the message bit stream c of inputk, respectively obtain system information bit streams xk, the check bit that obtains after component coder 1
Stream zkWith the check bit stream z obtained after component coder 2k.It can be seen that the input bit of component coder 2
Stream is not original input information, but the bit stream c ' that input stream is obtained after interleaverk.As it was previously stated, interweaving
For the transmission characteristic for improving mobile communication, the impact that reduction channel fading brings is extremely necessary for the addition of device.
Fig. 2 is a kind of structural representation of specific embodiment of Turbo code interleaver of the invention, is mainly included
4 modules：Rank addresses signal generating unit 10, full interleave unit 20, input block 30 and output buffer 40.Wherein export slow
It is optional to rush area, and when actually realizing, the full output data for interweaving list 20 can be directly output to follow-up computing unit, so
The consumption of memory source can be saved.
The storage of input block 20 needs to do the input stream of intertexture computing.In order to coordinate implementing for the present invention,
Input information bits stream is deposited in input block according to preferential mode is arranged.Meanwhile, specify according in LTE PHYs
Code block length K statistical property, line number R and columns C of input block are dynamic changes, and its value is according to following rule
Calculated：
C=K/R
That is the size of input block changes according to the size of concrete input block.The situation of such as K=40
Under, line number R=8, columns C=5；And during K=3136, line number R=64, line number C=49.
Rank addresses signal generating unit 10 mainly completes two parts work.First, according to the value of code block length K, by tabling look-up
Obtain the row address index needed for the code block carries out replacing for the first time.It is apparent that the length of the allocation index and input block
Line number R it is identical.The present inventor is in specific construction practice, different to 188 kinds specified in LTE PHYs 36.212
Row address index corresponding to code block length is counted.In order to reduce the length of patent specification, only citing does one here
Explanation.As code block length K=528, the line number and columns of its input block are respectively 16 and 33, corresponding row address index is
{ 0,3,10,5,4,7,14,9,8,11,2,13,12,15,6,1 }；
And for example during code block length K=1056, the line number and columns of its input block are 32 and 33 respectively, corresponding row ground
Location indexes
0,19,10,5,4,7,14,25,8,27,18,13,12,15,22,1,16,3,26,21,20,23,30,9,24,
11,2,29,28,31,6,17 }；
And for example during code block length K=5760, the line number and columns of its input block are 64 and 90 respectively, corresponding row ground
Location indexes
0,25,34,27,4,29,38,31,8,33,42,35,12,37,46,39,16,41,50,43,20,45,54,
47,24,49,58,51,28,53,62,55,32,57,2,59,36,61,6,63,40,1,10,3,44,5,14,7,48,9,18,
11,52,13,22,15,56,17,26,19,60,21,30,23 }.
Meanwhile, the present inventor is in specific construction practice, it was also found that for defined in LTE PHYs 36.212
Code block length in 188, under different code block lengths, its row address index also has certain rule, is differed at once before and after allocation index
For definite value.As described above, during code block length K=528, its cycle is 4, difference is also 4；During code block length K=1056, its cycle is
8, difference is also 8；When code block length is 5760, its cycle is 4/8/16/32, and its difference also correspondingly takes 4/8/16/32.This
A person of good sense had found in specific construction practice, for 188 kinds of 36.212 defined of LTE PHYs different code block lengths, all
There is similar rule.So, the index value of a part on the one hand can be only stored in storage line allocation index, internal memory is saved and is opened
Pin；Meanwhile, accessing operation rather than indirect addressing can also be carried out according to this rule when memorizer is accessed, improve memory access efficiency.
Another work of rank addresses signal generating unit 10 is exactly the column address index for calculating each row of data, that is, complete the
Interleaving index needed for twice replaced.Experience according to the present inventor in specific construction practice, for LTE PHYs
188 kinds of code block lengths of defined in 36.212, it can be deduced that following rule：Often capable column address index is relative is come with the first row
Say, only exist the 2 points of differences of side-play amount △ and difference N.It is exactly particularly, after the column address index T0 of known the first row, can
Then additive operation is done further according to difference N with according to side-play amount △ to T0 institutes circulative shift operation, you can obtain the row ground of the row
Location indexes.Similarly, in order to reduce the length of patent specification, only an explanation is done in citing here.Such as code block length K=400, its
The line number and columns of input block is 8 and 50 respectively, and which completes the column address index of second displacement first trip
T0=0,21,32,33,24,5,26,37,38,29,10,31,42,43,34,15,36,47,48,39,20,41,
2,3,44,25,46,7,8,49,30,1,12,13,4,35,6,17,18,9,40,11,22,23,14,45,16,27,28,19 }.
Often capable side-play amount △ and difference N are respectively { 2,4,6,8,10,12,14 } and { 41,33,25,17,9, Isosorbide-5-Nitrae 3 }.
In order to calculate the second row column address index, then by ring shift left 2 is done to T0 after, obtain
T1(=T0<<2 }=32,33,24,5,26,37,38,29,10,31,42,43,34,15,36,47,48,39,20,
41,2,3,44,25,46,7,8,49,30,1,12,13,4,35,6,17,18,9,40,11,22,23,14,45,16,27,28,
19,0,21 }；
Then add operation (index value more than columns C need to do modular arithmetic) is being done to T1, is obtaining the final row ground of the row
Location indexes
T2=23,24,15,46,17,28,29,20,1,22,33,34,25,6,27,38,39,30,11,32,43,44,
35,16,37,48,49,40,21,42,3,4,45,26,47,8,9,0,31,2,13,14,5,36,7,18,19,10,41,12 }.
In the same manner, thus the column address index of other each rows can also get.It should be noted that herein for narration side
Just, if three variables T0, T1 and T2, when actually realizing, variable T0, each calculated column address are only needed
Index can be directly delivered to interleave unit 20.
The main column address index according to the transmission of rank addresses signal generating unit 10 of full interleave unit 20, enters to every data line
The full intertexture computing of row, the result for obtaining are sent to output buffer 40.Its principle is as shown in Figure 4.Column address index 101 is ranks
The column address index of certain data line of the transmission of scalar/vector 10, full interleave unit 20 indexes 101 according to column address, to defeated
Enter data register 201 and do the full operation that interweaves, the data after being interweaved are stored in result register 202.
Fig. 3 is a kind of flow chart for realizing interweaving in Turbo code of the invention, and its calculating process is divided into several
Step：Step 50 indexes according to row address and the input number that data line sends into full interleave unit 20 is read from input block 30
According in depositor 201.Certainly, as it was previously stated, how much relevant with specific implementation the data read in every time are, one can be read in
OK, it is also possible to according to rule, once carry multirow data.Step 60 rank addresses signal generating unit 10 is according to deviant △ and difference
N, on the basis of first trip column address index, calculates the column address index 101 of current line, sends in full interleave unit 20.Step
70 full interleave units 20 do the full operation that interweaves, single fisherman's knot according to the column address index 101 for obtaining to input data depositor 201
Fruit is stored in output data depositor 202, or is directly stored in output buffer 40.Whether step 80 then judges all data
Intertexture computing is fully completed, circulation has been jumped out if intertexture computing is fully completed, otherwise returned to step 50 and continue above-mentioned
Operation.
In order that the thought of the present invention is further elaborated, illustrate by taking code block length K=216 as an example below.
It is the schematic diagram after 216 data of input are stored in input block in the way of row are preferential shown in Fig. 5.It is such as front
Described, its line number and columns are respectively 8 and 27.Method as described above, indexes according to row address, from input block 30
Middle reading each row of data completes displacement for the first time, completes to put for the second time by full interleave unit 20 according still further to the column address index of the row
Change.Three row data are read in as shown in Fig. 6 and be interleaved the storage state of rear output buffer 40.It should be noted that defeated
The presence or absence for going out relief area 40 is determined by specific implementation.
The process of calculating column address that the present embodiment is introduced index, be relative to first trip column address index do displacement and
The arithmetical operations such as add operation, other equivalents such as column address relative to previous row index done operation also in the present invention
Protection domain within.
Particular embodiments described above, has been carried out to the purpose of the present invention, technical scheme and beneficial effect further in detail
Describe in detail bright, it should be understood that the foregoing is only the specific embodiment of the present invention, be not limited to the present invention, it is all
Within the spirit and principles in the present invention, any modification, equivalent substitution and improvements done etc. should be included in the protection of the present invention
Within the scope of.
Claims (10)
1. a kind of method for interweaving in Parallel Implementation Turbo code, it is characterised in that data are stored in in the way of row are preferential
In input block, multiple replacement operator is then carried out, each replacement operator is by row address from the input block
Index reads in data line, is interleaved operation further according to column address index, realizes interweaving in Turbo code.
2. the method for interweaving in Parallel Implementation Turbo code according to claim 1, it is characterised in that the input buffering
Line number R and columns C in area is calculated according to following rule：
C=K/R, wherein K are code block length.
3. the method for interweaving in Parallel Implementation Turbo code according to claim 1, it is characterised in that will be different code blocks long
Column address index required during the degree corresponding column permutations of K is stored in a form, when first time replacement operator is carried out, described
Column address index is obtained according to code block length K and by tabling look-up.
4. the method for interweaving in Parallel Implementation Turbo code according to claim 3, it is characterised in that in addition to first trip
Capable column address index is calculated according to offset Δ and difference N by the column address index of first trip.
5. the method for interweaving in Parallel Implementation Turbo code according to claim 3, it is characterised in that obtain the first row
After column address indexes T0 and often goes relative to the offset Δ and difference N of the first row, T0 is circulated according to offset Δ
Shifting function, and add operation is completed according to difference N, obtain the column address index of the row in addition to first trip.
6. the method for interweaving in Parallel Implementation Turbo code according to claim 4, it is characterised in that in addition to first trip
Capable column address index is obtained according to different code block lengths K statistics.
7. the method for interweaving in the Parallel Implementation Turbo code according to claim 4 or 5, it is characterised in that what statistics was obtained
For side-play amount and difference from different code block lengths K.
8. the method for interweaving in Parallel Implementation Turbo code according to claim 1, it is characterised in that in the Turbo code
The degree of parallelism of the implementation of intertexture is stored in bit wide L of the columns C and interleave unit of input block and determines which is parallel by data
The computing formula of degree P is P=C/ceil (C/L), and ceil () is represented carries out the operation that rounds up to data.
9. the device for interweaving in a kind of Parallel Implementation Turbo code, it is characterised in that including rank addresses signal generating unit, full intertexture
Unit, input block,
The input block storage needs to do the input stream of intertexture computing；
The rank addresses signal generating unit completes two parts work：First, will be required during different code block lengths K corresponding column permutation
Column address index be stored in a form, when first time replacement operator is carried out, column address index is according to code block
Length K is simultaneously obtained by tabling look-up；Second, calculate the column address index of data often to be decoded in row input block, the is completed
Interleaving index needed for twice replaced；
The full interleave unit is indexed according to the column address that the rank addresses signal generating unit is transmitted, and every data line is carried out entirely
Intertexture computing.
10. the device for interweaving in Parallel Implementation Turbo code as claimed in claim 9, it is characterised in that also including output buffering
Area, which is used for the output data for storing the full interleave unit.
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| CN116318552B (en) * | 2023-03-15 | 2023-09-22 | 归芯科技(深圳)有限公司 | Interleaving or de-interleaving method for Turbo code, device, communication chip and device thereof |
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| CN102412850A (en) * | 2010-09-25 | 2012-04-11 | 中兴通讯股份有限公司 | Turbo code parallel interleaver and parallel interleaving method thereof |
| CN102577205A (en) * | 2009-10-29 | 2012-07-11 | 高通股份有限公司 | App (a priori probability) storage design for ITE TURBO decoder with quadratic permutation polynomial interleaver |
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| CN102577205A (en) * | 2009-10-29 | 2012-07-11 | 高通股份有限公司 | App (a priori probability) storage design for ITE TURBO decoder with quadratic permutation polynomial interleaver |
| CN102412850A (en) * | 2010-09-25 | 2012-04-11 | 中兴通讯股份有限公司 | Turbo code parallel interleaver and parallel interleaving method thereof |
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