CN106301390A - LDPC/Turbo code dual-mode decoding device - Google Patents

Abstract

The invention discloses a kind of LDPC/Turbo code dual-mode decoding device, including input-buffer, solve Multi-connection unit, posterior information memory element, data recombination interleaving network, SISO array, external information memory element, iteration unit next time, hard decision output unit and control unit.SISO array is made up of 12 SISO decoding units, and SISO decoding unit is the main computing unit of dual-mode decoding device, and it is designed based on configurable bimodulus computing unit.The code length gap of LDPC code and Turbo code is relatively big, is designed inherently causing the wasting of resources if simply maximizing according to code length, so the mode that posterior information memory element and external information memory element use memory element splicing solves this problem.The present invention is capable of the dual-mode decoding of LDPC and Turbo code, and achieves resource-sharing of both computing unit and memory element.

Description

LDPC/Turbo code dual-mode decoding device

Technical field

The present invention relates to Modern Communication System field, particularly relate to channel decoding technical field, be both specifically related to one The LDPC/Turbo code dual-mode decoding device that LDPC code can be decoded and Turbo code can be decoded.

Background technology

In Modern Communication System, information waiting for transmission is encoded, modulation, transmission, solution be in harmonious proportion decoding the most permissible Correct by the information that mistake occurs in transmitting procedure.Decoder acts in above-mentioned decoding process just.LDPC code and The excellent properties of Turbo code make many communication standards select both code words as channel coding schemes or alternative, In following communication system, LDPC and Turbo code are also must obligato scheme.Multimodal error correcting deocder is at different communication Communication for information between network plays an important role.But LDPC code is different with the decoding algorithm of Turbo code, and this will cause The difference of single mode decoder hardware structure, if simply simply single mode decoder being combined into dual-mode decoding device, is bound to cause The waste of resource.The research of multi-mode decoder relates generally to two aspects: the design of computing unit and the design of memory element, its Main thought is exactly the resource-sharing of different mode decoder, reaches to reduce to greatest extent the consumption of resource.Set up different code word The bridge of different decoding algorithms is the emphasis that computing unit shares design.In prior art, one can be used for LDPC code and Turbo The unified Message Passing Algorithm of code, for different code words, calculating process all includes forward metrics, backward tolerance, outer (interior) Information and the calculating of posterior information, and devise a kind of unified computing unit (Flexible Function based on this algorithm Unit, FFU), use 8 structures parallel for FFU to devise soft-output coding (SISO) decoding unit.The deficiency of FFU structure Part is: this structure have invoked two has Symbol LU T-S to table look-up form, is separately employed in LDPC decoding mode and Turbo decoding Pattern, the two have Symbol LU T-S table look-up form realize function be identical, it follows that this structure can also continue to change Enter, reduce form number of tabling look-up further, reduce resource consumption.

Summary of the invention

The technical problem to be solved is to provide a kind of LDPC/Turbo code dual-mode decoding device, thus realizes one Kind of the dual-mode decoding device that not only LDPC code can be decoded but also Turbo code can be decoded.

The present invention solves its technical problem and is adopted the technical scheme that: its LDPC/Turbo code dual-mode decoding device, including Input-buffer, solution Multi-connection unit, posterior information (Lall) memory element, data recombination interleaving network, SISO array, external information (Lmd) memory element, iteration (NII) unit next time, hard decision output unit and control unit, described LDPC/Turbo code bimodulus The Lall memory element of decoder and Lmd memory element use the mode of memory element splicing.SISO array is by 12 SISO decoding unit is constituted, and SISO decoding unit is designed based on CFU unit.

Further, Lall memory element of the present invention is for storing the channel letter of the channel information of Turbo, LDPC code Breath and posterior information.When carrying out LDPC decoding, channel information is written in column Lall memory element.When carrying out Turbo decoding, Channel information first passes around solution multiple connection output system information position, verification 1 and check bit 2 information, Lall memory element of restoring.By Maximum code length in LDPC code and Turbo code differs relatively big, and the quantization bit wide of the channel information of LDPC code and posterior information Difference, when memory element designs, example ram:18*24,14*104 and 7*128 of three kinds of sizes, wherein first digit Representing bit wide, second digit represents the degree of depth, is expressed as ram18_24, ram14_104, ram7_128.These three stores Module is twoport ram, belongs to memory element gama_ram, have invoked 48 gama_ram altogether.Lmd memory element is used for depositing The internal information of all non-negative element positions of storage LDPC code and the component code external information of Turbo code, maximize according to code length and carry out Design, the same form using ram splicing makes up the problem that different code word code length difference is bigger, 6 ram98_88 of example With two kinds of single port memory modules of 1 ram84_88, bit wide is respectively 98,84, and the degree of depth is 88.

Further, SISO unit of the present invention can complete the parallel decoding of 8 SPC codes and the Turbo of LDPC code The parallel processing of 8 states of code.Bimodulus SISO unit mainly by branch metric calculation unit, front and back to recursive unit (BFM), ACS1 and ACS2 unit is constituted, and wherein BMF unit, ACS1 and ACS2 unit design based on CFU unit.Mould is decoded at LDPC Under formula, in addition to ASC2 unit and lach storehouse are not used by, remaining formant both participates in LDPC decoded operation.SISO unit Receive the internal information from restructuring network and the posterior information of renewal, calculate prior information (in order to be collectively referred to as with Turbo code Branch metric), while storage, branch metric is input to FBM unit, first forward recursive calculating forward metrics, then after calculating To tolerance, backward tolerance direct serial is input to ASC1, ASC1 and receives backward tolerance, from the forward metrics cached and degree of branching Amount carries out the renewal of internal information, and the calculating of backward tolerance and internal information is operate on pipeline mode, when the kth clock cycle When completing the backward tolerance of kth bit, ACS1 unit completes the internal information of-1 bit of kth, the data output difference of the two Two clock cycle.Under Turbo decoding mode, all unit are all in duty, and decoding process is similar with LDPC code. SISO unit receives system information, check information and external information and carries out branch metric, front and back to the calculating of tolerance.ACS1 and ACS2 Unit completes the calculating of Turbo code posterior information jointly.One SISO unit can complete 8 SPC codes of LDPC code also The parallel processing of 8 states of row decoding and Turbo code.Bimodulus SISO unit mainly by branch metric calculation unit, front and back Constituting to recursive unit (BFM), ACS1 and ACS2 unit, wherein BMF unit, ACS1 and ACS2 unit are to set based on CFU unit Meter.Under LDPC decoding mode, in addition to ASC2 unit and lach storehouse are not used by, remaining formant both participates in LDPC Decoded operation.SISO unit receives from the restructuring internal information of network and the posterior information of renewal, calculate prior information (in order to It is collectively referred to as branch metric with Turbo code), while storage, branch metric is input to FBM unit, first forward recursive and calculates Forward metrics, then calculate backward tolerance, backward tolerance direct serial is input to ASC1, ASC1 and receives backward tolerance, from caching Forward metrics and branch metric carry out the renewal of internal information, the calculating of backward tolerance and internal information is operate on pipeline mode , when the kth clock cycle completes the backward tolerance of kth bit, ACS1 unit completes the internal information of-1 bit of kth, Data output two clock cycle of difference of the two.Under Turbo decoding mode, all unit are all in duty, decoding Process is similar with LDPC code.SISO unit receives system information, check information and external information and carries out branch metric, front and back to tolerance Calculating.ACS1 and ACS2 unit completes the calculating of Turbo code posterior information jointly.

Further, CFU unit of the present invention by two form LUT-S and LUT-U that table look-up, take minima maximum mould Block, alternative data selector, adder and subtractor are constituted.The two kinds of decoding algorithms that can realize bimodulus carry out research send out Existing, the TDMP algorithm of LDPC code and the Log-MAP algorithm of Turbo code are directed to the meter of same type of nonlinear function Calculate, i.e. correlation function calculates, and uses the approximate way tabled look-up of Look-up by pair correlation function log, can by two kinds of code words, two Plant the core calculations unit of different decoding algorithms in a CFU unit.The Log-MAP algorithm of Turbo code is directed to as Max* function shown in formula (1), and in TDMP algorithm forward metrics, after be directed to f to tolerance and the calculating of internal information (x, calculating y), as shown in formula (2).Formula (1) is substituted into formula (2), formula (3) can be obtained.Realize for the ease of hardware, Formula (3) can be analyzed to the computing of symbolic operation and absolute value, as shown in formula (4).Finally according to formula (4), TDMP algorithm Core calculations function in comprise the calculating of two correlation functions, be unsigned variant | x |+| y | respectively and have symbolic variable | x |-|y|；According to formula (1), the core calculations function of Log-MAP algorithm only comprises the calculating of a correlation function, be without symbol Number variable | x-y |.

$\begin{array}{c}max*(x,y)=ln(e^x+e^y)\\ =\max (x,y)+f_c\left(\right|x-y\left|\right)\end{array}---\left(1\right)$

$f(x,y)=ln\left(\frac{1+e^{x+y}}{e^x+e^y}\right)---\left(2\right)$

$\begin{array}{c}f(x,y)=\ln (1+e^{x+y})-\ln (e^x+e^y)\\ =\max (0,x+y)+f_x\left(\right|x+y\left|\right)-\left(\max \right(x,y)+f_c(\left|x-y\right|\left)\right)\\ =\min (x,y)+f_c\left(\right|x+y\left|\right)-f_c\left(\right|x-y\left|\right)\end{array}---\left(3\right)$

$\begin{array}{c}sign\left(f\right(x,y\left)\right)=sign\left(x\right)sign\left(y\right)\\ \left|f(x,y)\right|=\min \left(\right|x|,|y\left|\right)+f_c\left(\right|x|+|y\left|\right)-f_c\left(\right|x|-|y\left|\right)\end{array}---\left(4\right)$

f_c(a)=ln (1+e^-a) (5)

It is directed to identical calculating by the decoding core calculations formula of above-mentioned analysis, LDPC code and Turbo code Function, it is simply that the correlation function shown in formula (5).The present invention is by setting up two forms of tabling look-up: have Symbol LU T-S and without symbol LUT-U, in LDPC pattern, form LTU-U and LUT-S, all in the state of use, only has form LTU-U to be adjusted in Turbo pattern With, therefore the most called without symbol form LTU-U in two kinds of decoding modes, thus reached the purpose of resource-sharing.Above Formula (1)-(5) are all existing, and listing here is for convenience of explanation.

Compared with prior art, the invention has the beneficial effects as follows: the present invention proposes a kind of novel memory element and shares side Formula: Lall memory element and Lmd memory element use the mode of memory element splicing, realize resource-sharing with this, reduce resource Consume；Meanwhile, the SISO unit that the present invention proposes designs based on CFU unit, and described CFU unit is by two forms of tabling look-up LUT-S and LUT-U, take minima maximum module, alternative data selector, adder and subtractor are constituted.With existing The FFU unit realizing identical function is compared, and CFU unit is fewer than FFU unit calls a form of tabling look-up, it is achieved resource-sharing, subtracts Few resource consumption, can better adapt to the Modern Communication System requirement to signal processing

Accompanying drawing explanation

Fig. 1 is the configurable bimodulus computing unit (CFU) realizing LDPC/Turbo code bimodulus core algorithm of the present invention Structure chart；

Fig. 2 is that in emulation testing, LDPC code code length is 2304, the decoding overall waveform of code check r=1/2；

Fig. 3 is that in emulation testing, LDPC code code length is 2304, the decoding waveform partial enlargement of code check r=1/2；

Fig. 4 is Turbo code K=192 in emulation testing, the decoding overall waveform of code check r=1/2；

Fig. 5 is Turbo code K=192 in emulation testing, the decoding waveform partial enlargement of code check r=1/2；

Detailed description of the invention

LDPC/Turbo code dual-mode decoding device of the present invention, including input-buffer, solves Multi-connection unit, posterior information (Lall) memory element, data recombination interleaving network, SISO array, external information (Lmd) memory element, list iteration next time (NII) Unit, hard decision output unit and control unit, the Lall memory element of described LDPC/Turbo code dual-mode decoding device and Lmd storage Unit use memory element splicing mode and SISO decoding unit be designed based on CFU unit.

The Lall memory element of the present invention is for storing the channel information of Turbo, the channel information of LDPC code and posteriority letter Breath.When carrying out LDPC decoding, channel information is written in column Lall memory element.When carrying out Turbo decoding, channel information is first First pass through solution multiple connection output system information position, verification 1 and check bit 2 information, Lall memory element of restoring.Due to LDPC code and The maximum code length difference of Turbo code is relatively big, and the channel information of LDPC code is different with the quantization bit wide of posterior information, in storage During unit design, example ram:18*24,14*104 and 7*128 of three kinds of sizes, wherein first digit represents bit wide, the Two-digit represents the degree of depth, is expressed as ram18_24, ram14_104, ram7_128.These three memory module is twoport Ram, belongs to memory element gama_ram, have invoked 48 gama_ram altogether.

Under LDPC decoding mode, in 48 pieces of gama_ram, only ram18_24 is used, and stores two in an address Variable node posterior information or channel information, maximum can store the information of 2*24*48 variable node, when code length is 2304 to the maximum Time, employ ram18_24 modules whole in 48 pieces of gama_ram；Under Turbo decoding mode, owing to Turbo code length is maximum Be 6144, use the degree of parallelism of 12, then block length is 512 to the maximum, differs relatively big with LDPC code, and the present invention uses ram to splice Form store.It is divided into the internal splicing of gama_ram and external splice.Inside gama_ram, ram18_24 and ram14_ 104 splicings for storing information bit and the information of check bit 1, ram7_128 for storing the information of check bit 2, then one Gama_ram module can store the information of 128 nodes.When external splice, every four pieces of gama_ram module spliced are connected together shape Becoming 12 groups of new memory element, the most maximum supported sub-block length is 128*4=512.Produced by control unit during decoding Reading and writing enable accordingly, the ram making participation decode is in running order, uses ram splicing can save the consumption of storage resource.

Lmd memory element is for storing internal information and the component code of Turbo code of all non-negative element positions of LDPC code External information, maximizes according to code length and is designed, and it is bigger that the same form using ram splicing makes up different code word code length difference Problem, example 6 ram98_88 and two kinds of single port memory modules of 1 ram84_88, bit wide is respectively 98,84, and the degree of depth is 88。

In ldpc mode, in base check matrix, non-negative element is up to 88, need to deposit when spreading factor is 96 to the maximum The internal information of storage is 96*88.One ram98_88 module can store 14*88 node, and ram84_88 can store 12 The internal information of node, then 7 ram can store the internal information of (14*6+12) * 88 nodes；Under Turbo decoding mode, only There are 6 ram98_88 in running order.One ram98_88 can store 12 external informations, when sub-block length is 512, front 5 ram are all used, and the 6th ram module only employs 72 addresses therein, then coexist storage 12* (88+72)=6144 Individual external information.

Referring to Fig. 1, the CFU unit of the present invention by two form LUT-S and LUT-U that table look-up, take minima maximum module, Alternative data selector, adder and subtractor are constituted.The decoding residing for CFU unit is activated according to mode select signal mode Corresponding computing module in pattern and CFU unit,.As mode=0, CFU work and LDPC pattern, en_able1 and en_ Able2 signal is all activated, and in unit, all modules are output as f all in duty, data selector₂.Work as mode=1 Time, CFU unit is in Turbo pattern, and now en_able1 signal is not activated, therefore LUT-S module is not activated, and data select Device is output as f₁.In CFU unit, form LUT-S and LUT-U that table look-up in hardware realizes is expressed as follows shown in table 1, and CFU is mono- Unit inputs in different modes with to export information relationship as shown in table 2 below.

LUT in table 1CFU unit

Table 2CFU unit inputs in different modes and exports information relationship

The present invention is further illustrated below with concrete emulation testing.Emulation platform be Matlab, Quartus II and The union simulation platform of Modesim software sharing.First in Matlab software, randomly generate the information ratio of one group of regular length Spy, encoded device, 2BPSK modulation, awgn channel transmission add make an uproar, LLR calculate and data-measuring after, by result read.Will Matlab output result imports and produces test file in Quartuas II.The last Modesim that calls in Quartus II produces Decoding waveform.Decoding result compares with the result of calculation of Matlab.In the checking of LDPC decoding mode, the present embodiment is adopted With code check be 1/2,2/3A, 3/4B, the LDPC code of 5/6 carried out functional test.Fig. 2 and Fig. 3 be code length be 2304, code check is 1/ The test result of 2, other code lengths are similar with the test result of code check.At Turbo code decoding mode, use K=192 and 6144, Code check is respectively 1/2, has carried out functional test as a example by the Turbo code of 1/3, Fig. 4 and Fig. 5 be code length be 192, code check is 1/2 Test result, other code lengths are similar with the test result of code check.Wherein mode is used for representing current decoding mode, and mode=0 is LDPC decoding mode, is otherwise Turbo pattern.Rate represents code check, and code_len is the marking signal of code length, and din is input Signal, dout0～dout11 is the output port of LDPC code, and dout_t is that Turbo code decodes result output port, dec_ Success is and matlab simulation result comparing result, and niter is the iterations of current decoding, and hdd_en is hard decision letter Number.

Cyclone IV Series FPGA EP4CE115F29C7 is used to show as target devices, synthesis result, the present embodiment Dual-mode decoding device consume logical block 6.08k altogether, take memory element 243k, maximum operation frequency is 62MHz.The present invention is real Existing bimodulus SISO unit consumes logical block 3631 altogether, and the SISO unit of single mode ldpc code decoder consumes logical block 2590, and the SISO unit of single mode Turbo code decoder consumes logical block 2831, compares and understands, passes through computing unit The logical block that the bimodulus SISO unit of shared design is consumed consumes logical block sums, logic much smaller than two kinds of single mode SISO Unit has saved more than 33%.

The LDPC/Turbo code dual-mode decoding device of the present invention can be applicable to Modern Communication System channel decoding technical field, Not only LDPC code can be decoded but also Turbo code can be decoded, and under equal conditions, the bimodulus of the present invention The logical block that SISO unit is consumed consumes logical block sum much smaller than two kinds of single mode SISO, and logical block has saved 33% Above.

The embodiment of present invention described above, is not intended that limiting the scope of the present invention, any in the present invention On the basis of the equivalent made and improvement, should be included within the scope of the present invention.

Claims (4)

1.LDPC/Turbo code dual-mode decoding device, including input-buffer, solves Multi-connection unit, posterior information memory element, data weight Group interleaving network, SISO array, external information memory element, iteration unit next time, hard decision output unit and control unit, it is special Levy and be: described posterior information memory element and external information memory element use the mode of memory element splicing；Described SISO array comprises 12 SISO unit, and SISO unit is designed based on CFU unit.

LDPC/Turbo code dual-mode decoding device the most according to claim 1, it is characterised in that: the storage of described posterior information is single Unit is for storing the channel information of Turbo, the channel information of LDPC code and posterior information；When carrying out LDPC decoding, channel is believed Breath is written in column posterior information memory element；When carrying out Turbo decoding, channel information first passes around solution multiple connection output system letter Breath position, verification 1 and check bit 2 information, posterior information of restoring memory element；When memory element designs, example three kinds is big Little ram:18*24,14*104 and 7*128, wherein first digit represents bit wide, and second digit represents the degree of depth, respectively table It is shown as ram18_24, ram14_104, ram7_128.These three memory module is twoport ram, belongs to memory element gama_ Ram, have invoked 48 gama_ram altogether；External information memory element is for storing the interior letter of all non-negative element positions of LDPC code Breath and the component code external information of Turbo code, maximize according to code length and be designed, the same form using ram splicing, example Six ram98_88 and two kinds of single port memory modules of a ram84_88, bit wide is respectively 98,84, and the degree of depth is 88.

LDPC/Turbo code dual-mode decoding device the most according to claim 1, it is characterised in that: described SISO unit can complete The parallel decoding of 8 SPC codes of LDPC code and the parallel processing of 8 states of Turbo code；This SISO unit is mainly by branch Metric calculation unit, front and back to recursive unit, ACS1 and ACS2 unit constitute, wherein before and after to recursive unit, ACS1 and ACS2 Unit designs based on CFU unit；Under LDPC decoding mode, in addition to ASC2 unit and lach storehouse are not used by, its Remaining formant both participates in LDPC decoded operation；SISO unit receives the posteriority letter of the internal information from restructuring network and renewal Breath, calculates prior information, to recursive unit before and after being input to by branch metric while storage, before first forward recursive calculates To tolerance, then calculating backward tolerance, backward tolerance direct serial is input to ASC1, ASC1 and receives backward tolerance, from caching Forward metrics and branch metric carry out the renewal of internal information, and the calculating of backward tolerance and internal information is operate on pipeline mode , when the kth clock cycle completes the backward tolerance of kth bit, ACS1 unit completes the internal information of-1 bit of kth, Data output two clock cycle of difference of the two；Under Turbo decoding mode, all unit are all in duty, decoding Process is similar with LDPC code；SISO unit receives system information, check information and external information and carries out branch metric, front and back to tolerance Calculating；ACS1 and ACS2 unit completes the calculating of Turbo code posterior information jointly.

LDPC/Turbo code dual-mode decoding device the most according to claim 3, it is characterised in that: described CFU unit is by two Table look-up form LUT-S and LUT-U, take minima maximum module, alternative data selector, adder and subtractor are constituted； The approximate way tabled look-up by pair correlation function log employing Look-up, by two kinds of code words, the core of two kinds of different decoding algorithms Computing unit is in a CFU unit；The Log-MAP algorithm of Turbo code is directed to the max* letter as shown in formula (1) Number, and in TDMP algorithm forward metrics, after be directed to f to tolerance and the calculating of internal information (x, calculating y), such as formula (2) shown in；Formula (1) is substituted into formula (2), formula (3) can be obtained；Realizing for the ease of hardware, formula (3) can be analyzed to symbol Computing and the computing of absolute value, as shown in formula (4)；Finally according to formula (4), the core calculations function of TDMP algorithm comprises The calculating of two correlation functions is unsigned variant | x |+| y | respectively and has symbolic variable | x |-| y |；According to formula (1), The core calculations function of Log-MAP algorithm only comprises the calculating of a correlation function, is unsigned variant | x-y |；

$\begin{array}{c}max*(x,y)=ln(e^x+e^y)\\ =\max (x,y)+f_c\left(\right|x-y\left|\right)\end{array}---\left(1\right)$

$f(x,y)=ln\left(\frac{1+e^{x+y}}{e^x+e^y}\right)---\left(2\right)$

$\begin{array}{c}f(x,y)=ln(1+e^{x+y})-ln(e^x+e^y)\\ =\max (0,x+y)+f_c\left(\right|x+y\left|\right)-\left(\max \right(x+y)+f_c\left(\right|x+y\left|\right))\\ =max(x,y)+f_c\left(\right|x-y\left|\right)-f_c\left(\right|x-y\left|\right)\end{array}---\left(3\right)$

$\begin{array}{c}sign\left(f\right(x,y))=sign\left(x\right)sign\left(y\right)\\ \left|f(x,y)\right|=\min \left(\right|x|,|y\left|\right)+f_c\left(\right|x|+|y\left|\right)-f_c\left(\right|x|-|y\left|\right)\end{array}---\left(4\right)$

f_c(a)=ln (1+e^-|a|) (5)

It is directed to identical calculating function by the decoding core calculations formula of above-mentioned analysis, LDPC code and Turbo code, It is exactly the correlation function f shown in formula (5)_c(a)；Symbol LU T-S is had and without Symbol LU T-U by setting up two forms of tabling look-up； In LDPC pattern, form LTU-U and LUT-S, all in the state of use, only has form LTU-U to be called, therefore in Turbo pattern In two kinds of decoding modes the most called without symbol form LTU-U, reached the purpose of resource-sharing.