CN108074929A

CN108074929A - Semiconductor structure and its manufacturing method

Info

Publication number: CN108074929A
Application number: CN201611001696.5A
Authority: CN
Inventors: 李勇
Original assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Priority date: 2016-11-11
Filing date: 2016-11-11
Publication date: 2018-05-25
Anticipated expiration: 2036-11-11
Also published as: CN108074929B

Abstract

A kind of semiconductor structure and its manufacturing method, method include：Substrate is provided, including N-type and p-type logic area, pull up transistor area and transmission gate transistor area, N-type logic area includes the first N-type threshold voltage area for forming the first N-type device, the second N-type threshold voltage area for forming the second N-type device, and the first N-type device is less than the second N-type device threshold voltage；P-type logic area includes the first p-type threshold voltage area for forming the first P-type device, the second p-type threshold voltage area for forming the second P-type device, and the first P-type device is more than the second P-type device threshold voltage；Form gate dielectric layer；The first work-function layer is formed on gate dielectric layer；Remove the first p-type threshold voltage area and the first work-function layer of area that pulls up transistor；The second work-function layer is formed in the first work-function layer and gate dielectric layer；Remove first, second work-function layer of the first N-type threshold voltage area and transmission gate transistor area.The present invention improves SRAM write and enters redundancy.

Description

Semiconductor structure and its manufacturing method

Technical field

The present invention relates to semiconductor applications more particularly to a kind of semiconductor structure and its manufacturing methods.

Background technology

In current semiconductor industry, IC products can be divided mainly into three categories type：Logic, memory and simulation Circuit, wherein memory device account for sizable ratio in IC products.As semiconductor technology develops, to memory Part is more widely applied, it is necessary to the memory device and other device regions are formed simultaneously on a single die, with shape Into embedded semiconductor storing equipment.Such as central processing unit will be embedded in the memory device, then it is required that described deposit Memory device carries out compatible with embedded central processing unit platform, and keeps the specification of original memory device and corresponding electricity Performance.

Usually, it is necessary to the memory device be carried out with embedded standard logical devices compatible.It is partly led for embedded For body device, logic area and memory block are generally divided into, logic area generally includes logical device, and memory block then includes memory Part.With the development of memory technology, there is various types of semiconductor memories, such as static random random access memory (SRAM, Static Random Access Memory), dynamic RAM (DRAM, Dynamic Random Access Memory), Erasable Programmable Read Only Memory EPROM (EPROM, Erasable Programmable Read-Only Memory), Electrically erasable programmable read-only memory (EEPROM, Electrically Erasable Programmable Read-Only) With flash memory (Flash).Since Static RAM has many advantages, such as low-power consumption and very fast operating rate so that static random is deposited Reservoir and forming method thereof receives more and more attention.

However, the performance that the prior art forms Static RAM in semiconductor devices needs to be further improved, make The overall performance for obtaining semiconductor devices is poor.

The content of the invention

It is of the invention to solve the problems, such as to be to provide a kind of semiconductor structure and its manufacturing method, improve the write-in redundancy of memory Degree, so as to improve the overall performance of formed semiconductor devices.

To solve the above problems, the present invention provides a kind of manufacturing method of semiconductor structure, including：Substrate is provided, it is described Substrate includes N-type logic area, p-type logic area, pull up transistor area and transmission gate transistor area, wherein, the N-type logic area Including：The second N-type for the first N-type threshold voltage area for forming the first N-type device and for forming the second N-type device Threshold voltage area, the threshold voltage of the first N-type device are less than the threshold voltage of the second N-type device；The p-type logic Area includes：The 2nd P for the first p-type threshold voltage area for forming the first P-type device and for forming the second P-type device Type threshold voltage area, the threshold voltage of first P-type device are more than the threshold voltage of second P-type device；In the N-type Logic area, p-type logic area, pull up transistor area and transmission gate transistor area part of substrate on form gate dielectric layer；Institute It states and the first work-function layer is formed on gate dielectric layer；Remove first work(in the first p-type threshold voltage area and the area that pulls up transistor Function layer；In remaining first work-function layer, shape on the gate dielectric layer in the first p-type threshold voltage area and the area that pulls up transistor Into the second work-function layer；Remove the second work-function layer and first of the first N-type threshold voltage area and transmission gate transistor area Work-function layer；In remaining second work-function layer, the gate dielectric layer of the first N-type threshold voltage area and transmission gate transistor area The 3rd work-function layer of upper formation；The 4th work-function layer is formed in the 3rd work-function layer.

Correspondingly, the present invention also provides a kind of semiconductor structure, including：Substrate, the substrate include N-type logic area, p-type Logic area, pull up transistor area and transmission gate transistor area, wherein, the N-type logic area includes：With the first N-type device The first N-type threshold voltage area and with the second N-type device the second N-type threshold voltage area, the first N-type device Threshold voltage is less than the threshold voltage of the second N-type device；The p-type logic area includes：First with the first P-type device P-type threshold voltage area and the second p-type threshold voltage area with the second P-type device, the threshold value electricity of first P-type device Pressure is more than the threshold voltage of second P-type device；Gate dielectric layer, positioned at the N-type logic area, p-type logic area, upper crystal pulling On the part of substrate of area under control and transmission gate transistor area；First work-function layer, the grid positioned at the second p-type threshold voltage area On dielectric layer；Second work-function layer, positioned at the first p-type threshold voltage area and pull up transistor area gate dielectric layer on, with And in first work-function layer；3rd work-function layer, positioned at the first N-type threshold voltage area and transmission gate transistor area On gate dielectric layer and in second work-function layer.

Compared with prior art, technical scheme has the following advantages：

The manufacturing method of semiconductor structure of the present invention includes：The first work-function layer is formed on gate dielectric layer；Removal The first p-type threshold voltage area and first work-function layer in the area that pulls up transistor；In remaining first work-function layer, the The second work-function layer is formed on the gate dielectric layer in one p-type threshold voltage area and the area that pulls up transistor；Remove the first N-type threshold value Voltage zone and the second work-function layer and the first work-function layer of transmission gate transistor area；In remaining second work-function layer, The 3rd work-function layer is formed on the gate dielectric layer of first N-type threshold voltage area and transmission gate transistor area；In the 3rd work content Several layers of the 4th work-function layer of upper formation.That is, transmission gate transistor area of the present invention and the first N-type threshold voltage area Work-function layer formation process is identical, the work-function layer formation process phase in the pull up transistor area and the first p-type threshold voltage area Together, since the first N-type threshold voltage area is for forming the first N-type device, the second N-type threshold voltage area is used to be formed Second N-type device, and the threshold voltage of the first N-type device be less than the second N-type device threshold voltage, described first For forming the first P-type device, the second p-type threshold voltage area is used to form the second P-type device in p-type threshold voltage area, and The threshold voltage of first P-type device is more than the threshold voltage of second P-type device, therefore compared to making transmission gate transistor Area is identical with the work-function layer formation process in the second N-type threshold voltage area, makes pull up transistor area and the first p-type threshold voltage area The identical scheme of work-function layer formation process, the present invention is in the equivalent of work-function layer corresponding to area that pull up transistor described in maintenance While work function value, the equivalent work function value of work-function layer corresponding to the transmission gate transistor area is reduced, so that institute State the saturation current of transistor corresponding to transmission gate transistor area and ON state current increase；Therefore the present invention forms semiconductor device The gamma ratio of memory can be improved in part, so that the write-in redundancy of memory is improved, and then improve institute The performance of memory is formed, improves the overall performance for forming semiconductor devices.

The present invention provides a kind of semiconductor structure, and the semiconductor structure includes：It is situated between positioned at the second p-type threshold voltage area grid The first work-function layer on matter layer；It is on the gate dielectric layer in the first p-type threshold voltage area and the area that pulls up transistor and described The second work-function layer in first work-function layer；In the first N-type threshold voltage area and transmission gate transistor area gate dielectric layer, And the 3rd work-function layer in second work-function layer.That is, transmission gate transistor area of the present invention and the first N Work-function layer corresponding to type threshold voltage area is identical, described to pull up transistor corresponding to area and the first p-type threshold voltage area Work-function layer is identical；Since the first N-type threshold voltage area has the first N-type device, the second N-type threshold voltage area tool There is the second N-type device, and the threshold voltage of the first N-type device is less than the threshold voltage of the second N-type device, described the One p-type threshold voltage area has the first P-type device, and the second p-type threshold voltage area has the second P-type device, and described the The threshold voltage of one P-type device is more than the threshold voltage of second P-type device, therefore compared to transmission gate transistor area and second Work-function layer corresponding to N-type threshold voltage area is identical, pull up transistor area and the work content corresponding to the first p-type threshold voltage area A kind of several layers of identical semiconductor structure in semiconductor structure of the present invention, are pulling up transistor described in maintenance corresponding to area While the equivalent work function value of work-function layer, the equivalent work content of work-function layer corresponding to the transmission gate transistor area is reduced Numerical value, so that the transmission gate transistor area has the saturation current of transistor and ON state current increase；Therefore the present invention The gamma ratio of memory can be improved in the semiconductor structure, so that the write-in redundancy of memory is changed It is kind, and then the performance of the memory is improved, improve the overall performance of semiconductor devices.

Description of the drawings

Fig. 1 to Figure 13 be semiconductor structure of the present invention one embodiment of manufacturing method in each step counter structure schematic diagram.

Specific embodiment

From background technology, Static RAM (SRAM, Static Random Access in semiconductor devices Memory performance) has much room for improvement.Its reason is analyzed to be：

Static RAM mainly includes pull-up (PU, Pull Up) transistor, drop-down (PD, Pull Down) transistor And transmission gate (PG, Pass Gate) transistor, and the write-in redundancy (write margin) of memory is to memory performance It plays a key effect, if can improve the write-in redundancy performance of memory, the yield of memory can be improved, partly lead The overall performance of body device is accordingly improved.Wherein, the write-in redundancy of memory and gamma ratio (gamma ratio) are into just Proportionate relationship, gamma is than the ratio between the ON state current for transmission gate transistor and the ON state current to pull up transistor.

Equivalent work function value of the ON state current of transmission gate transistor corresponding to transmission gate work-function layer is related, transmission gate The equivalent work function value of work-function layer is smaller, then the ON state current of transmission gate transistor is bigger；The ON state current to pull up transistor Related with the equivalent work function value corresponding to pull-up work-function layer, it is smaller to pull up the equivalent work function value of work-function layer, then pulls up The ON state current of transistor is smaller.Therefore, reduce the equivalent work function value of transmission gate work-function layer or reduce pull-up work function The equivalent work function value of layer enables to the gamma of memory than increasing, and then improves the write-in redundancy of memory, and improvement is deposited The yield of reservoir.

In order to solve the technical problem, the present invention provides a kind of manufacturing method of semiconductor structure, the method bags It includes：The first work-function layer is formed on gate dielectric layer；It removes the first p-type threshold voltage area and pulls up transistor the first of area Work-function layer；In remaining first work-function layer, on the gate dielectric layer in the first p-type threshold voltage area and the area that pulls up transistor Form the second work-function layer；Remove second work-function layer and in the first N-type threshold voltage area and transmission gate transistor area One work-function layer；In remaining second work-function layer, the gate medium of the first N-type threshold voltage area and transmission gate transistor area The 3rd work-function layer is formed on layer；The 4th work-function layer is formed in the 3rd work-function layer.It is that is, of the present invention Transmission gate transistor area is identical with the work-function layer formation process in the first N-type threshold voltage area, the Qu Yu that pulls up transistor The work-function layer formation process in one p-type threshold voltage area is identical, since the first N-type threshold voltage area is used to form the first N Type device, the second N-type threshold voltage area is for forming the second N-type device, and the threshold voltage of the first N-type device is small In the threshold voltage of the second N-type device, the first p-type threshold voltage area is for forming the first P-type device, and described second P-type threshold voltage area is for forming the second P-type device, and the threshold voltage of first P-type device is more than the second p-type device The threshold voltage of part, therefore compared to the work-function layer formation process phase for making transmission gate transistor area and the second N-type threshold voltage area With, make the area's scheme identical with the work-function layer formation process in the first p-type threshold voltage area that pull up transistor, the present invention is maintaining While the equivalent work function value of the work-function layer corresponding to area that pulls up transistor, the transmission gate transistor area institute is reduced The equivalent work function value of corresponding work-function layer, so that the saturation current of transistor corresponding to the transmission gate transistor area and opening State electric current increases；Therefore the gamma ratio of the invention for forming memory in semiconductor devices can be improved, so that depositing The write-in redundancy of reservoir is improved, and then improves the performance of institute's formation memory, and raising forms the whole of semiconductor devices Body performance.

It is understandable for the above objects, features and advantages of the present invention is enable to become apparent, below in conjunction with the accompanying drawings to the present invention Specific embodiment be described in detail.

With reference to figure 1, substrate (not indicating) is provided, the substrate includes N-type logic area (not indicating), p-type logic area (is not marked Show), pull up transistor area I and transmission gate transistor area 70, wherein, the N-type logic area includes：For forming the first N-type First N-type threshold voltage area 61 of device and the second N-type threshold voltage area 21 for forming the second N-type device, described the The threshold voltage of one N-type device is less than the threshold voltage of the second N-type device；The p-type logic area includes：For forming the First p-type threshold voltage area 11 of one P-type device and the second p-type threshold voltage area 52 for forming the second P-type device, The threshold voltage of first P-type device is more than the threshold voltage of second P-type device.

The semiconductor devices that the present embodiment is formed includes logical device and SRAM device.Therefore, the N-type logic area Technique platform is provided to be subsequently formed N-type logical device；The p-type logic area provides technique to be subsequently formed p-type logical device Platform；The area I that pulls up transistor is to be subsequently formed to pull up transistor to provide technique platform；The transmission gate transistor area 70 is It is subsequently formed transmission gate transistor and technique platform is provided.The area I that pulls up transistor is PMOS area, the transmission gate transistor Area 70 is NMOS area.

It should be noted that the substrate further includes pull-down transistor area (not shown), after the pull-down transistor area is The continuous pull-down transistor that formed provides technique platform, and the pull-down transistor area is NMOS area.Wherein, the area that pulls up transistor I, transmission gate transistor area 70 and pull-down transistor area are memory block, are provided to be subsequently formed Static RAM (SRAM) Technique platform.

It should also be noted that, in order to improve the device current in sram cell area, the transmission gate transistor area 70 includes Adjacent the first transmission gate transistor area II and the second transmission gate transistor area III.The first transmission gate transistor area II is It is subsequently formed the first transmission gate transistor and technique platform is provided, the second transmission gate transistor area III is to be subsequently formed second Transmission gate transistor provides technique platform, and the first transmission gate transistor and the second transmission gate transistor form biography in parallel Send a transistor.The first transmission gate transistor area II and the second transmission gate transistor area III is NMOS area.

The p-type logic area includes several p-type threshold voltage areas.Specifically, the first p-type threshold voltage area 11 is P-type standard threshold voltage area (SVT, Standard VT) 11；The second p-type threshold voltage area 52 includes：P-type ultralow threshold value Voltage zone (ULVT, Ultra-low VT) 13 and p-type low-threshold power pressure area (LVT, Low VT) 12.

The threshold voltage for the p-type logical device that each region is formed being ordered as from low to high in the p-type logic area：P Type ultralow threshold value voltage zone 13, p-type low-threshold power pressure area 12, p-type standard threshold voltage area 11.The p-type logic area can also Including p-type high threshold voltage area (High VT) (not shown) and p-type input and output device area (IO, Input Output), (figure is not Show).

The N-type logic area includes several N-type threshold voltage areas.Specifically, the first N-type threshold voltage area 61 is wrapped It includes：N-type ultralow threshold value voltage zone 23 and N-type low-threshold power pressure area 22；The second N-type threshold voltage area 21 is N-type standard threshold Threshold voltage area 21.

The threshold voltage for the N-type logical device that each region is formed being ordered as from low to high in the N-type logic area：N Type ultralow threshold value voltage zone 23, N-type low-threshold power pressure area 22, N-type standard threshold voltage area 21.The N-type logic area can also Including N-type high threshold voltage area's (not shown) and N-type input and output device area (not shown).

The present embodiment by the semiconductor structure that is formed for exemplified by fin field effect pipe, therefore the step of substrate is provided in, The substrate includes substrate 100 and discrete fin 110 on the substrate 100.

In another embodiment, the semiconductor structure is planar transistor, correspondingly, the substrate is planar substrates, The planar substrates are silicon substrate, germanium substrate, silicon-Germanium substrate or silicon carbide substrates, silicon-on-insulator substrate or germanium on insulator serve as a contrast Bottom, glass substrate or III-V compound substrate (such as gallium nitride substrate or gallium arsenide substrate etc.).

In the present embodiment, the substrate 100 is silicon substrate.In other embodiments, the material of the substrate can also be Germanium, SiGe, carborundum, GaAs or gallium indium, the substrate can also be the silicon substrate on insulator, the germanium on insulator Substrate, substrate of glass or III-V compound substrate (such as gallium nitride substrates or gallium arsenide substrate etc.).

The material identical of the material of the fin 110 and the substrate 100.In the present embodiment, the material of the fin 110 For silicon.In other embodiments, the material of the fin can also be germanium, SiGe, carborundum, GaAs or gallium indium.

Specifically, forming the processing step of the substrate 100 and fin 110 includes：Initial substrate is provided；Described initial Substrate surface forms patterned hard mask layer (not shown)；Using the hard mask layer as initial substrate described in mask etching, shape Into substrate 100 and protrude from the fin 110 on 100 surface of substrate.

In the present embodiment, after forming the substrate 100 and fin 110, retain the hard mask for being located at 110 top of fin Layer.The material of the hard mask layer is silicon nitride, subsequently when carrying out planarization process technique, the hard mask layer top surface For defining the stop position of planarization process technique, and play the role of protecting 110 top of fin.

With continued reference to Fig. 1, it is necessary to which explanation, after forming the substrate 100 and fin 110, the manufacturing method is also wrapped It includes：Isolation structure 101 is formed on the substrate 100 exposed in the fin 110, the isolation structure 101 covers the fin 110 partial sidewall, and the top of the isolation structure 101 is less than the top of the fin 110.

Isolation structure of the isolation structure 101 as semiconductor structure, for playing buffer action to adjacent devices.This In embodiment, the material of the isolation structure 101 is silica.In other embodiments, the material of the isolation structure may be used also Think silicon nitride or silicon oxynitride.

Specifically, the step of forming isolation structure 101 includes：Filling is full on the substrate 100 exposed in the fin Isolated material, the isolated material top is higher than at the top of the hard mask layer (not shown)；Grinding removal is higher than the hard mask The isolated material at layer top, forms isolation film；The isolation film of segment thickness is etched back to, exposes the top of the fin 110 Portion and partial sidewall form the isolation structure 101；Remove the hard mask layer.

It should also be noted that, further include step：N is carried out to the substrate of the p-type logic area and the area I that pulls up transistor Type well region doping treatment forms N-type well region in the substrate of the p-type logic area and the area I that pulls up transistor；To the N-type The substrate of logic area, transmission gate transistor area 70 and pull-down transistor area (not shown) carries out P type trap zone doping treatment, in institute It states and P type trap zone is formed in the substrate of N-type logic area, transmission gate transistor area 70 and pull-down transistor area.

Further, since the N-type ultralow threshold value voltage zone 23 and N-type low-threshold power pressure area are subsequently formed in same step Work-function layer corresponding to 22, and the device threshold voltage of the N-type ultralow threshold value voltage zone 23 is less than the N-type low-threshold power The device threshold voltage of pressure area 22, therefore after the formation isolation film, be etched back to before the isolation film of segment thickness, it is described Manufacturing method further includes：First N-type threshold value is carried out to the substrate corresponding to the N-type ultralow threshold value voltage zone 23 and adjusts doping (VT Implant) processing carries out the second N-type threshold value to the substrate corresponding to the N-type low-threshold power pressure area 22 and adjusts doping (VT Implant) processing.Specifically, the first N-type threshold value adjusts doping treatment and the second N-type threshold value adjusts doping treatment Doped ions for N-type ion, N-type ion includes P, As or Sb, and the first N-type threshold value adjusts the doping concentration of doping treatment Less than the doping concentration that the second N-type threshold value adjusts doping treatment.

By subsequently forming 12 institute of the p-type ultralow threshold value voltage zone 13 and p-type low-threshold power pressure area in same step Corresponding work-function layer, and the device threshold voltage of the p-type ultralow threshold value voltage zone 13 is less than the p-type low-threshold power pressure area 12 device threshold voltage, therefore after the formation isolation film, be etched back to before the isolation film of segment thickness, the manufacture Method further includes：First p-type threshold value is carried out to the substrate corresponding to the p-type ultralow threshold value voltage zone 13 and adjusts doping treatment, Second p-type threshold value is carried out to the substrate corresponding to the p-type low-threshold power pressure area 12 and adjusts doping treatment.Specifically, described One p-type threshold value adjusts doping treatment and the second p-type threshold value adjusts the Doped ions of doping treatment as p-type ion, and p-type ion includes B, Ga or In, the doping concentration that the first p-type threshold value adjusts doping treatment are less than the second p-type threshold value adjusting doping treatment Doping concentration.

With reference to reference to figure 2, in the present embodiment, gate electrode layer (high k are formed after high-k gate dielectric layer is formed after Last metal gate last) technique, form the gate structure of semiconductor structure.Therefore, the manufacturing method further includes： The N-type logic area (not indicating), p-type logic area (not indicating), the area I that pulls up transistor, transmission gate transistor area 70 and under Pseudo- grid structure 120 is formed in the substrate of crystal pulling area under control (not shown).

Dummy gate structure 120 is to be subsequently formed the gate structure of semiconductor structure to take up space position.Specifically, formed Across the pseudo- grid structure 120 of the fin 110, and dummy gate structure 120 cover the fin 110 atop part surface and Partial sidewall surface.

Dummy gate structure 120 is single layer structure or laminated construction.Dummy gate structure 120 includes pseudo- grid layer；Or institute Stating pseudo- grid structure 120 includes pseudo- oxide layer and the pseudo- grid layer in the pseudo- oxide layer.Wherein, the material of the pseudo- grid layer For polysilicon, silica, silicon nitride, silicon oxynitride, carborundum, carbonitride of silicium, carbon silicon oxynitride or amorphous carbon, the pseudo- oxidation The material of layer is silica or silicon oxynitride.

It should be noted that in the present embodiment, dummy gate structure 120 across the N-type logic area, p-type logic area, on Crystal pulling area under control I, transmission gate transistor area 70 and pull-down transistor area.In other embodiments, the pseudo- grid structure in each region is also Can be mutually discrete.

It should also be noted that, after forming dummy gate structure 120, the manufacturing method further includes：In the pseudo- grid knot Source and drain doping area (not shown) is formed in the fin 110 of 120 both sides of structure.Specifically, in the fin of each 120 both sides of region puppet grid structure The source and drain doping area of each transistor is formed in portion 110.

With reference to reference to figure 3, after forming the source and drain doping area, dummy gate structure 120 (as shown in Figure 3) is removed.

In the present embodiment, dry etch process, wet-etching technology or SiCoNi etching systems may be employed, described in removal Pseudo- grid structure 120.

It should be noted that before dummy gate structure 120 is removed, the manufacturing method further includes：In the pseudo- grid Interlayer dielectric layer (not shown) is formed in the substrate that structure 120 exposes, the interlayer dielectric layer exposes dummy gate structure 120 Top.

With reference to figure 4, in the N-type logic area (not indicating), p-type logic area (not indicating), pull up transistor area I and biography Send formation gate dielectric layer 102 on the part of substrate of a transistor area 70.

The substrate further includes pull-down transistor area (not shown), therefore in the step of formation gate dielectric layer 102, the grid Dielectric layer 102 is also formed on the part of substrate in the pull-down transistor area.

In the present embodiment, the gate dielectric layer 102 include boundary layer (IL, Interfacial Layer) (not indicating) with And the high-k gate dielectric layer (not indicating) positioned at the interface layer surfaces.Specifically, it is described in the step of forming gate dielectric layer 102 Gate dielectric layer 102 covers atop part surface and the sidewall surfaces of the fin 110 across the fin 110.

The boundary layer provides good interface basis to form the high-k gate dielectric layer, is situated between so as to improve the high k grid The quality of matter layer reduces the interface state density between the high-k gate dielectric layer and fin 110, and avoids the high-k gate dielectric layer Harmful effect caused by being contacted directly with fin 110.The material of the boundary layer is silica or silicon oxynitride.

In the present embodiment, the boundary layer is formed using oxidation technology, the boundary layer formed is only formed at what is exposed 102 top surface of fin and sidewall surfaces.In other embodiments, can also the boundary layer, example be formed using depositing operation Such as chemical vapor deposition method, physical gas-phase deposition or atom layer deposition process, the boundary layer formed is also located at described On isolation structure.

The material of the high-k gate dielectric layer is more than the gate medium material of silica relative dielectric constant for relative dielectric constant Material.In the present embodiment, the material of the high-k gate dielectric layer is HfO₂.In other embodiments, the material of the high-k gate dielectric layer Material can also be HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO₂Or Al₂O₃.Chemical vapor deposition, physics may be employed Vapor deposition or atom layer deposition process form the high-k gate dielectric layer.In the present embodiment, formed using atom layer deposition process The high-k gate dielectric layer.

Subsequent step also includes forming work-function layer on the gate dielectric layer 102.In order in subsequent technique, to described Gate dielectric layer 102 plays a protective role, and is formed before work function, the manufacturing method further includes：On the gate dielectric layer 102 Form cap layer (not shown)；Etching stop layer (not shown) is formed in the cap layer.

The cap layer can play the role of the protection gate dielectric layer 102, prevent subsequent etching technics to described Gate dielectric layer 102 causes unnecessary etching loss, and the cap layer also helps stop and subsequently formed in gate electrode layer Easy diffused metal ions are spread into the gate dielectric layer 102.In the present embodiment, the material of the cap layer is TiN, using original Sublayer depositing operation forms the cap layer, and the cap layer is made to have good step coverage.In other embodiments, institute The material for stating cap layer can also be TiSiN, and formation process can also be chemical vapor deposition method or physical vapour deposition (PVD) work Skill.

The etching stop layer is different from the follow-up material for forming work-function layer, so that work content described in subsequent etching Several layers of etching technics is smaller to the etch rate of the etching stop layer, therefore the etching stop layer is described in subsequent etching Play the role of etching stopping in the etching technics of work-function layer, etching injury can be caused to avoid to the gate dielectric layer 102. In the present embodiment, the material of the etching stop layer is TaN, forms the etching stop layer using atom layer deposition process, makes The etching stop layer has good step coverage.In other embodiments, the material of the etching stop layer can be with For TaSiN, formation process can also be chemical vapor deposition method or physical gas-phase deposition.

Subsequent step is included in the work-function layer formed on the gate dielectric layer 102 in each region corresponding to each region devices；It is right For N-type device, the equivalent work function value of work-function layer is smaller, and device threshold voltage is smaller, and the thickness of work-function layer is got over It is small；For P-type device, the equivalent work function value of work-function layer is smaller, and device threshold voltage is bigger, and the thickness of work-function layer It spends smaller.Wherein, device threshold voltage is smaller, and the ON state current (Ion) of the device is corresponding bigger.

In the present embodiment, since the first N-type threshold voltage area 61 is for the first N-type device of formation, second N-type Threshold voltage area 21 is for forming the second N-type device, and the threshold voltage of the first N-type device is less than the second N-type device The threshold voltage of part, 11st area of the first p-type threshold voltage are used to form the first P-type device, the second p-type threshold voltage area 52 for forming the second P-type device, and the threshold voltage of first P-type device is more than the threshold value electricity of second P-type device Pressure, therefore in follow-up step, make work-function layer corresponding to the 70 and first N-type threshold voltage area 61 of transmission gate transistor area Formation process it is identical, make the formation work of the work-function layer corresponding to area I and the first p-type threshold voltage area 11 that pulls up transistor Skill is identical；Compared to making, transmission gate transistor area 70 is identical with the formation process of 21 work-function layer of the second N-type threshold voltage area, makes Scheme identical with the formation process of 11 work-function layer of the first p-type threshold voltage area crystal pulling area under control I, the present embodiment are maintaining institute It states while pull up transistor the equivalent work function value of work-function layer corresponding to area I, reduces the transmission gate transistor area 70 The equivalent work function value of corresponding work-function layer, so that the follow-up ON state current increase for forming transmission gate transistor, and then The gamma ratio (gamma ratio) of institute's formation memory can be improved, improves the write-in redundancy of memory.

It should be noted that the first transmission gate transistor area II is for forming the first transmission gate transistor, described the Two transmission gate transistor area III are for forming the second transmission gate transistor, and the first transmission gate transistor and second transmits Door transistor forms transmission gate transistor in parallel；In order to avoid there is transmission gate transistor saturation current (Idsat) and ON state The phenomenon that electric current is excessive, to prevent leak-stopping electric current it is excessive the problem of, so as to be prevented while memory gamma ratio is improved pair The overall performance of formed semiconductor devices generates harmful effect, in the present embodiment, to the second transmission gate transistor area III The processing step carried out is identical with the processing step carried out to the first N-type threshold voltage area 61；Correspondingly, to described The processing step that first transmission gate transistor area II is carried out is walked with the technique carried out to the second N-type threshold voltage area 21 It is rapid identical.

In another embodiment, the processing step carried out to the first transmission gate transistor area with to the first N The processing step that type threshold voltage area is carried out is identical；Correspondingly, the technique carried out to the second transmission gate transistor area Step is identical with the processing step carried out to the second N-type threshold voltage area.In other embodiments, can also be：It is right The technique step that the first transmission gate transistor area, the second transmission gate transistor area and the first N-type threshold voltage area are carried out It is rapid identical.

It should also be noted that, in the present embodiment, it is described according to the actual performance demand of follow-up formed pull-down transistor Pull-down transistor area (not shown) is identical with the formation process of work-function layer corresponding to the second N-type threshold voltage area 21, correspondingly, The processing step carried out to the pull-down transistor area and the processing step carried out to the second N-type threshold voltage area 21 It is identical.

It elaborates below with reference to attached drawing to the forming step for forming work-function layer corresponding to each region.

With reference to figure 5, the first work-function layer 310 is formed on the gate dielectric layer 102.

Specifically, in the N-type logic area (not indicating), p-type logic area (not indicating), pull up transistor area I and transmission First work-function layer 310 is formed on the gate dielectric layer 102 of door transistor area 70.The substrate further includes pull-down transistor area (not shown), therefore in the step of formation the first work-function layer 310, first work-function layer 310 is also formed into described On the gate dielectric layer 102 in pull-down transistor area.

A part of first work-function layer 310 as work-function layer corresponding to follow-up second p-type threshold voltage area 52, For adjusting the threshold voltage of transistor corresponding to follow-up p-type ultralow threshold value voltage zone 13 and p-type low-threshold power pressure area 12.Therefore Follow-up the first work-function layer 310 for only retaining the second p-type threshold voltage area 52.

First work-function layer 310 be p-type work function material, p-type work function material workfunction range for 5.1eV extremely 5.5eV, for example, 5.2eV, 5.3eV or 5.4eV.The material of first work-function layer 310 for Ta, TiN, TaN, TaSiN or Chemical vapor deposition method, physical gas-phase deposition or atom layer deposition process may be employed in one or more of TiSiN Form first work-function layer 310.

In the present embodiment, the material of first work-function layer 310 is TiN；It is formed by atom layer deposition process described First work-function layer 310, so that first work-function layer 310 has good step coverage.

The thickness of first work-function layer 310 is according to the p-type ultralow threshold value voltage zone 13 and p-type low-threshold power pressure area Depending on the threshold voltage of transistor corresponding to 12.In the present embodiment, the thickness of first work-function layer 310 isExtremely

With reference to figure 6, the first p-type threshold voltage area 11 and the first work-function layer 310 for the area I that pulls up transistor are removed.

The threshold voltage for forming the first P-type device is more than the threshold voltage for forming the second P-type device, therefore this implementation It is subsequently in the first p-type threshold value by removing first work-function layer 310 in the first p-type threshold voltage area 11 in example Relatively thin work-function layer is formed on voltage zone 11, Process ba- sis is provided.

In the present embodiment, the formation of the work-function layer corresponding to area I and the first p-type threshold voltage area 11 that pulls up transistor Technique is identical, therefore, in the step of removing first work-function layer 310 in the first p-type threshold voltage area 11, also described in removal Pull up transistor the first work-function layer 310 of area I.

Specifically, in the second p-type threshold voltage area 52, N-type logic area (not indicating), 70 and of transmission gate transistor area The first graph layer 210 is formed in first work-function layer 310 of pull-down transistor area (not shown)；With first graph layer 210 For mask, using the first etching technics, the first p-type threshold voltage area 11 and the first work content for the area I that pulls up transistor are removed Several layers 310, until exposing the etching stop layer (not shown)；Remove first graph layer 210.

In the present embodiment, the material of first graph layer 210 is photoresist, after completing first etching technics, First graph layer 210 is removed using wet etching or cineration technics.In other embodiments, the material of first graph layer Material can also be silicon nitride or boron nitride.

In the present embodiment, first etching technics can be that dry etch process, wet-etching technology or SiCoNi are carved Erosion system.

With reference to reference to figure 7 to Fig. 9, in remaining first work-function layer 310, the first p-type threshold voltage area 11 and on The second work-function layer 350 (as shown in Figure 9) is formed on the gate dielectric layer 102 of crystal pulling area under control I.

Second work-function layer 350 is used as follow-up p-type logic area (not indicating) and the work content corresponding to area I that pulls up transistor The part of several layers subsequently forms the first P-type device, the second P-type device and the threshold voltage to pull up transistor for adjusting. Therefore the second work-function layer 350 of the p-type logic area and the area I that pulls up transistor subsequently are retained.

In the present embodiment, second work-function layer 350 is laminated construction, below with reference to attached drawing to forming described second The step of work-function layer 350, elaborates.

As shown in fig. 7, it in remaining first work-function layer 310, the first p-type threshold voltage area 11 and pulls up transistor The first workfunction material 320 is formed on the gate dielectric layer 102 of area I.

In order to preferably provide processing compatibility, in the present embodiment, first workfunction material 320 and described first The material identical of work-function layer 310.Therefore in the present embodiment, the material of first workfunction material 320 is TiN；Pass through Atom layer deposition process forms first workfunction material 320, so that first workfunction material 320 is with good Good step coverage.The corresponding of foregoing first work-function layer 310 refer to the description of first workfunction material 320 Description, details are not described herein.

The thickness of first workfunction material 320 depending on the thickness of first work-function layer 310, also according to It is follow-up to be formed depending on the first P-type device, the second P-type device and the threshold voltage that pulls up transistor.In the present embodiment, described The thickness of one workfunction material 320 isExtremely

It should be noted that in the present embodiment, first workfunction material 320 is also formed into the pull-down transistor In first work-function layer 310 of area's (not shown).

As shown in figure 8, it should also be noted that, according to the follow-up actual performance demand for forming the second N-type device, this reality It applies in example, first workfunction material is formed in first work-function layer 310 in the second N-type threshold voltage area 21 After 320, the manufacturing method further includes：Remove first workfunction material 320 and in the second N-type threshold voltage area 21 One work-function layer 310.

In the present embodiment, to the first transmission gate transistor area II processing steps carried out and to second N-type The processing step that threshold voltage area 21 is carried out is identical, the processing step carried out to pull-down transistor area (not shown) with The processing step carried out to the second N-type threshold voltage area 21 is identical, therefore removes the second N-type threshold voltage area 21 The first workfunction material 320 and the step of the first work-function layer 310 in, also remove the first transmission gate transistor area II With first workfunction material 320 and the first work-function layer 310 in pull-down transistor area.

Specifically, the p-type logic area (not indicating), the area I that pulls up transistor, the first N-type threshold voltage area 61 and Second graph layer 220 is formed in the first workfunction material 320 of second transmission gate transistor area III；With the second graph Layer 220 is mask, and using the second etching technics, removal is positioned at the second N-type threshold voltage area 21, the first transmission gate transistor The first workfunction material 320 and the first work-function layer 310 on area II and pull-down transistor area, until exposing the etch-stop Only layer (not shown)；Remove the second graph layer 220.

The correlation that can refer to foregoing first graph layer 210 (as shown in Figure 6) for the description of the second graph layer 220 is retouched It states, may be referred to the associated description of foregoing first etching technics for the description of second etching technics, details are not described herein.

As shown in figure 9, the second workfunction material 330 is formed in first workfunction material 320, described second 330 and first workfunction material 320 of workfunction material is used to form second work-function layer 350.

Specifically, in remaining first workfunction material 320, the second N-type threshold voltage area 21, first biography It send and forms second workfunction material on a transistor area II and the gate dielectric layer 102 of pull-down transistor area (not shown) 330。

Since removal is located at the second N-type threshold voltage area 21, the first transmission gate transistor area II and pull-down transistor After the first workfunction material 320 and the first work-function layer 310 in area's (not shown), exposing the etching stop layer, (figure is not Show), therefore second workfunction material 330 is formed at the second N-type threshold voltage area 21, the first transmission gate transistor On area II and the etching stop layer of pull-down transistor area (not shown).

Second workfunction material 330 is as follow-up p-type logic area (not indicating), the area I that pulls up transistor, the 2nd N The part in type threshold voltage area 21, the first transmission gate transistor area II and work-function layer corresponding to pull-down transistor area, is used for Adjusting subsequently forms the first P-type device, the second P-type device, pulls up transistor, the second N-type device, the first transmission gate transistor With the threshold voltage of pull-down transistor.Therefore the p-type logic area, the area I that pulls up transistor, the second N-type threshold value electricity are subsequently retained Pressure area 21, the first transmission gate transistor area II and second workfunction material 330 in pull-down transistor area.

In order to preferably improve processing compatibility, in the present embodiment, second workfunction material 330 and described first The material identical of work-function layer 310.Therefore in the present embodiment, the material of second workfunction material 330 is TiN；Pass through Atom layer deposition process forms second workfunction material 330, so that second workfunction material 330 is with good Good step coverage.The corresponding of foregoing first work-function layer 310 refer to the description of second workfunction material 330 Description, details are not described herein.

Thickness of the thickness of second workfunction material 330 according to first work-function layer 310, the first work function Depending on the thickness of material layer 320, form the first P-type device, the second P-type device also according to follow-up, pull up transistor, the 2nd N Depending on the threshold voltage of type device, the first transmission gate transistor and pull-down transistor.In the present embodiment, the second work function material The thickness of the bed of material 330 isExtremely

With reference to figure 10, the second work-function layer of removal the first N-type threshold voltage area 61 and transmission gate transistor area 70 350 and first work-function layer 310.

For NMOS device, it is related to the thickness of work-function layer to form the threshold voltage of transistor, and work function The thickness of layer is bigger, and threshold voltage is also corresponding bigger；Since the first N-type threshold voltage area 61 is for the first N-type device of formation Part, the second N-type threshold voltage area 21 is for forming the second N-type device, and the threshold voltage of the first N-type device is less than The threshold voltage of the second N-type device, therefore by removing the N-type low-threshold power pressure area 22 and N-type ultralow threshold value voltage Second work-function layer 350 and the first work-function layer 310 in area 23 are subsequently ultralow in the N-type low-threshold power pressure area 22 and N-type Relatively thin work-function layer is formed in threshold voltage area 23, Process ba- sis is provided.

In addition, in the present embodiment, to the processing step that the second transmission gate transistor area III is carried out with to described the The processing step that one N-type threshold voltage area 61 is carried out is identical, therefore the removal N-type low-threshold power pressure area 22 and N-type are ultralow In the step of second work-function layer 350 in threshold voltage area 23 and the first work-function layer 310, it is brilliant also to remove second transmission gate The second work-function layer 350 and the first work-function layer 310 of body area under control III.

Specifically, in the p-type logic area, the area I that pulls up transistor, the second N-type threshold voltage area 21, pull-down transistor area The 3rd graph layer 230 is formed in (not shown) and the second workfunction material 330 of the first transmission gate transistor area II；With institute The 3rd graph layer 230 is stated as mask, using the 3rd etching technics, removal is ultralow positioned at the N-type low-threshold power pressure area 22, N-type The second workfunction material 330, the first workfunction material 320 of 23 and second transmission gate transistor area III of threshold voltage area With the first work-function layer 310, until exposing the etching stop layer (not shown)；Remove the 3rd graph layer 230.

The correlation that can refer to foregoing first graph layer 210 (as shown in Figure 6) for the description of the 3rd graph layer 230 is retouched It states, the associated description of foregoing first etching technics is may be referred to for the description of the 3rd etching technics, details are not described herein.

It should be noted that in the present embodiment, the material of the cap layer (not shown) is TiN, the etching stop layer Material for TaN, the material of the cap layer and etching stop layer is p-type work function material, therefore in order to further reduce institute The equivalent work function value of work-function layer corresponding to the second transmission gate transistor area III is stated, it is described after the 3rd etching technics Manufacturing method further includes：Remove the cap layer and etching stopping on the second transmission gate transistor area III gate dielectric layers 102 Layer.

In the present embodiment, dry etch process, wet-etching technology or SiCoNi etching systems may be employed, described in removal Cap layer and etching stop layer on second transmission gate transistor area III gate dielectric layers 102.

With reference to figure 11, in remaining second work-function layer 350, the first N-type threshold voltage area 61 and transmission gate crystal The 3rd work-function layer 340 is formed on the gate dielectric layer 102 in area under control 70.

Specifically, in remaining second work-function layer 350, the second N-type threshold voltage area 21, the first transmission gate crystal In second workfunction material 330 of area under control II and pull-down transistor area (not shown), the first N-type threshold voltage area 61 The 3rd work-function layer is formed on etching stop layer and on the gate dielectric layer 102 of the second transmission gate transistor area III 340。

3rd work-function layer 340 is as the p-type logic area (not indicating), N-type logic area (not indicating), transmission gate Transistor area 70, a part for the work-function layer corresponding to area I and pull-down transistor area (not shown) that pulls up transistor, for adjusting It is follow-up formed the first P-type device, the second P-type device, the first N-type device, the second N-type device, pull up transistor, first transmits The threshold voltage of door transistor, the second transmission gate transistor and pull-down transistor.

In order to preferably improve processing compatibility, in the present embodiment, the 3rd work-function layer 340 and first work content Several layers 310 of material identical.Therefore in the present embodiment, the material of the 3rd work-function layer 340 is TiN；Pass through atomic layer deposition Product technique forms the 3rd work-function layer 340, so that the 3rd work-function layer 340 has good step coverage. It refer to the corresponding description of foregoing first work-function layer 310 to the description of the 3rd work-function layer 340, details are not described herein.

Thickness of the thickness of 3rd work-function layer 340 according to first work-function layer 310, the first work function material Depending on 320 thickness of layer and the thickness of the second workfunction material 330, the first P-type device, the 2nd P are formed also according to follow-up Type device, the first N-type device, the second N-type device, pull up transistor, the first transmission gate transistor, the second transmission gate transistor and Depending on the threshold voltage of pull-down transistor.In the present embodiment, the thickness of the 3rd work-function layer 340 isExtremely

With reference to figure 12, the 4th work-function layer 400 is formed in the 3rd work-function layer 340.

4th work-function layer 400 is as N-type logic area (not indicating), transmission gate transistor area 70 and lower crystal pulling A part for work-function layer corresponding to the (not shown) of area under control, for adjust it is follow-up formed the first N-type device, the second N-type device, The threshold voltage of first transmission gate transistor, the second transmission gate transistor and pull-down transistor.

It should be noted that in order to reduce processing step, save light shield, in the present embodiment, the 4th work function is formed After layer 400, retain positioned at the p-type logic area (not indicating) and the 4th work(to pull up transistor in the 3rd work-function layers 340 of area I Function layer 400.

4th work-function layer 400 be N-type work function material, N-type work function material workfunction range for 3.9eV extremely 4.5eV is, for example, 4eV, 4.1eV or 4.3eV.The material of 4th work-function layer 400 for TiAl, TiAlC, TaAlN, Chemical vapor deposition method, physical gas-phase deposition or atom may be employed in one or more in TiAlN, TaCN and AlN Layer depositing operation forms the 4th work-function layer 400.In the present embodiment, the material of the 4th work-function layer 400 is TiAl.

The thickness of 4th work-function layer 400 is according to the thickness and the second work function of the 3rd work-function layer 340 Depending on the thickness of material layer 330, also according to it is follow-up formed the first N-type device, the second N-type device, the first transmission gate transistor, Depending on the threshold voltage of second transmission gate transistor and pull-down transistor.In the present embodiment, the thickness of the 4th work-function layer 400 It spends and isExtremely

Therefore, in the present embodiment, the second workfunction material 330, the 3rd work content in the second N-type threshold voltage area 21 Several layers 340 and the 4th work-function layer 400 are for forming the work-function layer of the second N-type device；(figure is not in the pull-down transistor area Show) the second workfunction material 330, the 3rd work-function layer 340 and the 4th work-function layer 400 for forming pull-down transistor Work-function layer；The second workfunction material 330, the 3rd work-function layer 340 and the 4th of the first transmission gate transistor area II Work-function layer 400 is used to be formed the work-function layer of the first transmission gate transistor；3rd work(in the first N-type threshold voltage area 61 340 and the 4th work-function layer 400 of function layer is used to be formed the work-function layer of the first N-type device；The second transmission gate transistor The 3rd work-function layer 340 of area III and the 4th work-function layer 400 are used to be formed the work-function layer of the second transmission gate transistor.

In the present embodiment, second work-function layer 350 in the first p-type threshold voltage area 11,340 and of the 3rd work-function layer 4th work-function layer 400 is used to be formed the work-function layer of the first P-type device；First work(in the second p-type threshold voltage area 52 Function layer 310, the second work-function layer 350, the 3rd work-function layer 340 and the 4th work-function layer 400 are for the second P-type device of formation Work-function layer；The second work-function layer 350, the 3rd work-function layer 340 and the 4th work-function layer of the area I that pulls up transistor 400 work-function layers to pull up transistor for formation.

With reference to figure 13, after forming the 4th work-function layer 400, the manufacturing method further includes：In the 4th work content Gate electrode layer 500 is formed on several layers 400.

In the present embodiment, the gate electrode layer 500 is across the first p-type threshold voltage area 11, the second p-type threshold voltage Area 52, the area I that pulls up transistor, the second N-type threshold voltage area 21, the first N-type threshold voltage area 61,70 and of transmission gate transistor area Pull-down transistor area (not shown).In other embodiments, the gate electrode layer in each region can also be mutually discrete.

In the present embodiment, the material of the gate electrode layer 500 include one kind in Al, Cu, Ag, Au, Pt, Ni, Ti or W or It is a variety of.

Specifically, forming the processing step of the gate electrode layer 500 includes：It is formed in the 4th work-function layer 400 Gate electrode film, the gate electrode film top is higher than at the top of the interlayer dielectric layer (not shown)；Grinding removal is higher than the interlayer Gate electrode film at the top of dielectric layer forms the gate electrode layer 500.

In the present embodiment, the first work-function layer is formed on gate dielectric layer；Remove the first p-type threshold voltage area and upper First work-function layer in crystal pulling area under control；In remaining first work-function layer, the first p-type threshold voltage area and upper crystal pulling The second work-function layer is formed on the gate dielectric layer in area under control；Remove the first N-type threshold voltage area and transmission gate transistor area Second work-function layer and the first work-function layer；In remaining second work-function layer, the first N-type threshold voltage area and transmission gate The 3rd work-function layer is formed on the gate dielectric layer of transistor area；The 4th work-function layer is formed in the 3rd work-function layer. That is transmission gate transistor area of the present invention is identical with the work-function layer formation process in the first N-type threshold voltage area, it is described The area that pulls up transistor is identical with the work-function layer formation process in the first p-type threshold voltage area, due to the first N-type threshold voltage For forming the first N-type device, the second N-type threshold voltage area is used to form the second N-type device, and first N-type in area The threshold voltage of device is less than the threshold voltage of the second N-type device, and the first p-type threshold voltage area is used to form first P-type device, the second p-type threshold voltage area are used to form the second P-type device, and the threshold voltage of first P-type device More than the threshold voltage of second P-type device, therefore compared to the work(for making transmission gate transistor area and the second N-type threshold voltage area Function floor formation process is identical, the area that makes to pull up transistor is identical with the work-function layer formation process in the first p-type threshold voltage area Scheme, the present invention reduce institute while the equivalent work function value for the work-function layer corresponding to area that pulls up transistor described in maintenance The equivalent work function value of work-function layer corresponding to transmission gate transistor area is stated, so that brilliant corresponding to the transmission gate transistor area Saturation current and the ON state current increase of body pipe；Therefore the gamma ratio of the invention for forming memory in semiconductor devices can obtain To raising, so that the write-in redundancy of memory is improved, and then improves the performance of institute's formation memory, institute's shape is improved Into the overall performance of semiconductor devices.

Correspondingly, the present invention also provides a kind of semiconductor structures.With continued reference to Figure 13, semiconductor structure of the present invention is shown The structure diagram of one embodiment.The semiconductor structure includes：

Substrate, the substrate include N-type logic area (not indicating), p-type logic area (not indicating), pull up transistor area I with And transmission gate transistor area 70, wherein, the N-type logic area includes：The first N-type threshold voltage area with the first N-type device 61 and the second N-type threshold voltage area 21 with the second N-type device, the threshold voltage of the first N-type device be less than described The threshold voltage of second N-type device；The p-type logic area includes：The first p-type threshold voltage area 11 with the first P-type device, And the second p-type threshold voltage area 52 with the second P-type device, the threshold voltage of first P-type device are more than described the The threshold voltage of two P-type devices；Gate dielectric layer 102, positioned at the N-type logic area, p-type logic area, pull up transistor area I and On the part of substrate of transmission gate transistor area 70；First work-function layer 310, the grid positioned at the second p-type threshold voltage area 52 On dielectric layer 102；Second work-function layer 350 is situated between positioned at the grid of the first p-type threshold voltage area 11 and the area I that pulls up transistor On matter layer 102 and in first work-function layer 310；3rd work-function layer 340, positioned at the first N-type threshold voltage area 61 and transmission gate transistor area 70 gate dielectric layer 102 on and second work-function layer 350 on.

Semiconductor structure described in the present embodiment includes logical device and SRAM device.Wherein, positioned at the N-type logic area On device for N-type logical device, the device on the p-type logic area is p-type logical device, positioned at the upper crystal pulling For device on the I of area under control to pull up transistor, the device on the transmission gate transistor area 70 is transmission gate transistor.Specifically , for the area I that pulls up transistor for PMOS area, the transmission gate transistor area 70 is NMOS area.

It should be noted that the substrate further includes pull-down transistor area (not shown), the pull-down transistor area is NMOS area, the pull-down transistor area have pull-down transistor.Specifically, it is described pull up transistor, transmission gate transistor and Pull-down transistor forms SRAM device.

It should also be noted that, in order to improve the device current in sram cell area, the transmission gate transistor area 70 includes Adjacent the first transmission gate transistor area II and the second transmission gate transistor area III.The first transmission gate transistor area II tools There is the first transmission gate transistor, the second transmission gate transistor area III has the second transmission gate transistor, and described first passes A transistor and the second transmission gate transistor is sent to form transmission gate transistor in parallel.The first transmission gate transistor area II and Second transmission gate transistor area III is NMOS area.

The threshold voltage of the p-type logical device in each region being ordered as from low to high in the p-type logic area：P-type Ultralow threshold value voltage zone 13, p-type low-threshold power pressure area 12, p-type standard threshold voltage area 11.The p-type logic area can also wrap (figure is not for KuoPXing high threshold voltages area (High VT) (not shown) and p-type input and output device area (IO, Input Output) Show).

The threshold voltage of the N-type logical device in each region being ordered as from low to high in the N-type logic area：N-type Ultralow threshold value voltage zone 23, N-type low-threshold power pressure area 22, N-type standard threshold voltage area 21.The N-type logic area can also wrap KuoNXing high threshold voltages area's (not shown) and N-type input and output device area (not shown).

The present embodiment by the semiconductor junction component for exemplified by fin field effect pipe, therefore the substrate include substrate 100, And the discrete fin 110 on the substrate 100.

It should be noted that the semiconductor structure further includes：Between the adjacent fin 110 on substrate 100 Isolation structure 101, the top of the isolation structure 101 are less than the top of the fin 110.

The semiconductor structure further includes：Positioned at the p-type logic area and the intrabasement N-type traps of area I that pull up transistor Area；Positioned at the N-type logic area, the intrabasement P type trap zone in transmission gate transistor area 70 and pull-down transistor area；It further includes： Source and drain doping area in each region part fin 110.

In the present embodiment, the gate dielectric layer 102 include boundary layer (IL, Interfacial Layer) (not indicating) with And the high-k gate dielectric layer (not indicating) positioned at the interface layer surfaces, the gate dielectric layer 102 are also located at the pull-down transistor On the part of substrate in area.Specifically, the gate dielectric layer 102 is across the fin 110, and covers the part of the fin 110 Top surface and sidewall surfaces.

The material of the high-k gate dielectric layer is more than the gate medium material of silica relative dielectric constant for relative dielectric constant Material.In the present embodiment, the material of the high-k gate dielectric layer is HfO₂.In other embodiments, the material of the high-k gate dielectric layer Material can also be HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO₂Or Al₂O₃。

In the present embodiment, second work-function layer 350 is laminated construction.Second work-function layer 350 includes：It is located at The first p-type threshold voltage area 11 and pull up transistor area I gate dielectric layer 102 on and first work-function layer 310 On the first workfunction material 320；The second workfunction material 330 in first workfunction material 320.

Specifically, second workfunction material 330 is also located at the gate dielectric layer in the second N-type threshold voltage area 21 On 102；Correspondingly, the 3rd work-function layer 340 is also located at second work function material in the second N-type threshold voltage area 21 On layer 330.

Second workfunction material 330, the 3rd work-function layer 340 and the 4th work(in the second N-type threshold voltage area 21 Function layer 400 constitutes the work-function layer of the second N-type device；Second work function material of pull-down transistor area (not shown) The 330, the 3rd work-function layer 340 of layer and the 4th work-function layer 400 constitute the work-function layer of pull-down transistor；First transmission The second workfunction material 330, the 3rd work-function layer 340 and the 4th work-function layer 400 of door transistor area II constitutes first The work-function layer of transmission gate transistor；3rd work-function layer 340 and the 4th work-function layer in the first N-type threshold voltage area 61 400 constitute the work-function layer of the first N-type device；The 3rd work-function layer 340 of the second transmission gate transistor area III and Four work-function layers 400 constitute the work-function layer of the second transmission gate transistor.

Second work-function layer 350, the 3rd work-function layer 340 and the 4th work function in the first p-type threshold voltage area 11 Layer 400 constitutes the work-function layer of the first P-type device；First work-function layer 310 in the second p-type threshold voltage area 52, Two work-function layers 350, the 3rd work-function layer 340 and the 4th work-function layer 400 constitute the work-function layer of the second P-type device；Institute The second work-function layer 350, the 3rd work-function layer 340 and the 4th work-function layer 400 for stating the area I that pulls up transistor constitute crystal pulling The work-function layer of body pipe.

For N-type device, the equivalent work function value of work-function layer is smaller, and device threshold voltage is smaller, and work function The thickness of layer is smaller；For P-type device, the equivalent work function value of work-function layer is smaller, and device threshold voltage is bigger, and work( The thickness of function layer is smaller.Wherein, device threshold voltage is smaller, and the ON state current (Ion) of the device is corresponding bigger.

Since the first N-type threshold voltage area 61 has the first N-type device, the second N-type threshold voltage area 21 has There is the second N-type device, and the threshold voltage of the first N-type device is less than the threshold voltage of the second N-type device, described the One p-type threshold voltage, 11st area has the first P-type device, and the second p-type threshold voltage area 52 has the second P-type device, and institute The threshold voltage for stating the first P-type device is more than the threshold voltage of second P-type device, therefore in the present embodiment, the transmission Door transistor area 70 is identical with the work-function layer corresponding to the first N-type threshold voltage area 61, the area I and first that pulls up transistor Work-function layer corresponding to p-type threshold voltage area 11 is identical；Compared to 70 and second N-type threshold voltage area 21 of transmission gate transistor area Corresponding work-function layer is identical, and the area I that pulls up transistor is identical with the work-function layer corresponding to the first p-type threshold voltage area 11 A kind of semiconductor structure, the present embodiment reduce while the equivalent work function value for the work-function layer that pulls up transistor described in maintenance The equivalent work function value of the transmission gate transistor work function layer, so that the saturation current of the transmission gate transistor (Idsat) increase with ON state current, and then improve the gamma ratio (gamma ratio) of memory, improve writing for memory Enter redundancy.

It should be noted that the first transmission gate transistor area II has the first transmission gate transistor, described second passes Send a transistor area III that there is the second transmission gate transistor, and the first transmission gate transistor and the second transmission gate transistor Form transmission gate transistor in parallel；In order to avoid there is the phenomenon that transmission gate transistor saturation current and excessive ON state current, To prevent leak-stopping electric current it is excessive the problem of, so as to while memory gamma ratio is improved, prevent to the whole of semiconductor devices Body performance generates harmful effect, therefore in the present embodiment, the second transmission gate transistor area III and the first N-type threshold value Work-function layer corresponding to voltage zone 61 is identical；Correspondingly, the first transmission gate transistor area II and the second N-type threshold value Work-function layer corresponding to voltage zone 21 is identical.

In another embodiment, corresponding to the first transmission gate transistor area and the first N-type threshold voltage area Work-function layer is identical；Correspondingly, the second transmission gate transistor area and the work content corresponding to the second N-type threshold voltage area Several layers identical.In other embodiments, can also be：The first transmission gate transistor area, the second transmission gate transistor area with And the first work-function layer corresponding to N-type threshold voltage area is identical.

It should also be noted that, in the present embodiment, according to the actual performance demand of the pull-down transistor, the lower crystal pulling Body area under control (not shown) is identical with the work-function layer corresponding to the second N-type threshold voltage area 21.

First work-function layer 310 is used to adjust the threshold voltage of the second P-type device.

First work-function layer 310 be p-type work function material, p-type work function material workfunction range for 5.1eV extremely 5.5eV, for example, 5.2eV, 5.3eV or 5.4eV.The material of first work-function layer 310 for Ta, TiN, TaN, TaSiN or One or more of TiSiN.In the present embodiment, the material of first work-function layer 310 is TiN.

The thickness of first work-function layer 310 is depending on the threshold voltage of second P-type device.The present embodiment In, the thickness of first work-function layer 310 isExtremely

Second workfunction material, 330 and first workfunction material 320 constitutes second work-function layer 350.Second work-function layer 350 is used to adjust first P-type device, the second P-type device and the threshold value to pull up transistor Voltage, and second workfunction material 330 be additionally operable to adjust the second N-type device, the first transmission gate transistor and under The threshold voltage of pull transistor.

The material of first workfunction material 320 can be Ta, TiN, TaN, TaSiN or TiSiN in one kind or Several, the material of second workfunction material 330 can be one kind or several in Ta, TiN, TaN, TaSiN or TiSiN Kind.In order to preferably improve processing compatibility, in the present embodiment, the 320 and second work function material of the first workfunction material The material of the bed of material 330 and the material identical of first work-function layer 310.Therefore in the present embodiment, the first work function material The material of 320 and second workfunction material 330 of the bed of material is all TiN.

The thickness of first workfunction material 320 depending on the thickness of first work-function layer 310, also according to Depending on first P-type device, the second P-type device and the threshold voltage that pulls up transistor；Second workfunction material 330 Thickness depending on the thickness of first work-function layer 310, the thickness of the first workfunction material 320, also according to described First P-type device, the second P-type device pull up transistor, the second N-type device, the first transmission gate transistor and pull-down transistor Depending on threshold voltage.In the present embodiment, the thickness of first workfunction material 320 isExtremelySecond work( The thickness of function material layer 330 isExtremely

3rd work-function layer 340 is for the first P-type device of adjusting, the second P-type device, the first N-type device, the 2nd N Type device pulls up transistor, the threshold voltage of the first transmission gate transistor, the second transmission gate transistor and pull-down transistor.

The material of 3rd work-function layer 340 can be one or more of Ta, TiN, TaN, TaSiN or TiSiN. In order to preferably improve processing compatibility, in the present embodiment, material and first work function of the 3rd work-function layer 340 The material identical of layer 310.Therefore in the present embodiment, the material of the 3rd work-function layer 340 is TiN.

Thickness of the thickness of 3rd work-function layer 340 according to first work-function layer 310, the first work function material Depending on 320 thickness of layer and the thickness of second workfunction material 330, also according to first P-type device, the 2nd P Type device, the first N-type device, the second N-type device, pull up transistor, the first transmission gate transistor, the second transmission gate transistor and Depending on the threshold voltage of pull-down transistor.In the present embodiment, the thickness of the 3rd work-function layer 340 isExtremely

4th work-function layer 400 for adjust the first N-type device, the second N-type device, the first transmission gate transistor, The threshold voltage of second transmission gate transistor and pull-down transistor.In the present embodiment, the 4th work-function layer 400 is also located at institute In the 3rd work-function layer 340 for stating p-type logic area (not indicating) and the area I that pulls up transistor.

4th work-function layer 400 be N-type work function material, N-type work function material workfunction range for 3.9eV extremely 4.5eV is, for example, 4eV, 4.1eV or 4.3eV.The material of 4th work-function layer 400 for TiAl, TiAlC, TaAlN, One or more in TiAlN, TaCN and AlN.In the present embodiment, the material of the 4th work-function layer 400 is TiAl.

The thickness of 4th work-function layer 400 is according to the thickness and the second work function of the 3rd work-function layer 340 Depending on the thickness of material layer 330, passed also according to the first N-type device, the second N-type device, the first transmission gate transistor, second Depending on the threshold voltage for sending a transistor and pull-down transistor.In the present embodiment, the thickness of the 4th work-function layer 400 isExtremely

In the present embodiment, the semiconductor structure includes：The first work(on the second p-type threshold voltage area gate dielectric layer Function layer；On the gate dielectric layer in the first p-type threshold voltage area and the area that pulls up transistor and in first work-function layer The second work-function layer；In the first N-type threshold voltage area and transmission gate transistor area gate dielectric layer and second work( The 3rd work-function layer on function layer.That is, transmission gate transistor area of the present invention and the first institute of N-type threshold voltage area Corresponding work-function layer is identical, and the area that pulls up transistor is identical with the work-function layer corresponding to the first p-type threshold voltage area；By There is the first N-type device in the first N-type threshold voltage area, the second N-type threshold voltage area has the second N-type device, And the threshold voltage of the first N-type device is less than the threshold voltage of the second N-type device, the first p-type threshold voltage Area has the first P-type device, and the second p-type threshold voltage area has the second P-type device, and the threshold of first P-type device Threshold voltage is more than the threshold voltage of second P-type device, therefore compared to transmission gate transistor area and the second N-type threshold voltage area Corresponding work-function layer is identical, the area that pulls up transistor is identical with the work-function layer corresponding to the first p-type threshold voltage area one Kind of semiconductor structure, in semiconductor structure of the present invention, the work-function layer corresponding to area that pulls up transistor described in maintenance etc. While imitating work function value, the equivalent work function value of work-function layer corresponding to the transmission gate transistor area is reduced, so that The transmission gate transistor area has the saturation current of transistor and ON state current increase；Therefore semiconductor junction of the present invention The gamma ratio of memory can be improved in structure, so that the write-in redundancy of memory is improved, and then improve institute The performance of memory is stated, improves the overall performance of semiconductor devices.

Although present disclosure is as above, present invention is not limited to this.Any those skilled in the art are not departing from this It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute Subject to the scope of restriction.

Claims

1. a kind of manufacturing method of semiconductor structure, which is characterized in that including：

Substrate is provided, the substrate includes N-type logic area, p-type logic area, pull up transistor area and transmission gate transistor area, Wherein, the N-type logic area includes：For the first N-type threshold voltage area for forming the first N-type device and for forming the Second N-type threshold voltage area of two N-type devices, the threshold voltage of the first N-type device are less than the threshold of the second N-type device Threshold voltage；The p-type logic area includes：For the first p-type threshold voltage area for forming the first P-type device and for being formed Second p-type threshold voltage area of the second P-type device, the threshold voltage of first P-type device are more than second P-type device Threshold voltage；

The N-type logic area, p-type logic area, pull up transistor area and transmission gate transistor area part of substrate on formed Gate dielectric layer；

The first work-function layer is formed on the gate dielectric layer；

Remove first work-function layer in the first p-type threshold voltage area and the area that pulls up transistor；

It is formed in remaining first work-function layer, on the gate dielectric layer in the first p-type threshold voltage area and the area that pulls up transistor Second work-function layer；

Remove the second work-function layer and the first work-function layer of the first N-type threshold voltage area and transmission gate transistor area；

In remaining second work-function layer, shape on the gate dielectric layer of the first N-type threshold voltage area and transmission gate transistor area Into the 3rd work-function layer；

The 4th work-function layer is formed in the 3rd work-function layer.

2. the manufacturing method of semiconductor structure as described in claim 1, which is characterized in that in remaining first work-function layer The step of forming the second work-function layer on the gate dielectric layer in upper, the first p-type threshold voltage area and the area that pulls up transistor includes：Surplus The first work content is formed in remaining first work-function layer, on the gate dielectric layer in the first p-type threshold voltage area and the area that pulls up transistor Number material layer；Form the second workfunction material in first workfunction material, second workfunction material and First workfunction material is used to form second work-function layer；

After forming first workfunction material in first work-function layer in the second N-type threshold voltage area, the is formed Before two workfunction materials, the manufacturing method further includes：Remove the first work function material in the second N-type threshold voltage area The bed of material and the first work-function layer；

In the step of forming the second workfunction material in first workfunction material, in the second N-type threshold value electricity Second workfunction material is formed on the gate dielectric layer of pressure area；

Remove second work-function layer in the first N-type threshold voltage area and transmission gate transistor area and the step of the first work-function layer In rapid, the second workfunction material, first work content in the first N-type threshold voltage area and transmission gate transistor area are removed successively Number material layer and the first work-function layer；

In remaining second work-function layer, shape on the gate dielectric layer of the first N-type threshold voltage area and transmission gate transistor area The step of three work-function layers in, described is formed in second workfunction material in the second N-type threshold voltage area Three work-function layers.

3. the manufacturing method of semiconductor structure as claimed in claim 2, which is characterized in that the material of first work-function layer For one or more of Ta, TiN, TaN, TaSiN or TiSiN；The material of first workfunction material for Ta, TiN, One or more of TaN, TaSiN or TiSiN；The material of second workfunction material for Ta, TiN, TaN, TaSiN or One or more of TiSiN；The material of 3rd work-function layer be Ta, TiN, TaN, TaSiN or TiSiN in one kind or It is several.

4. the manufacturing method of semiconductor structure as claimed in claim 2 or claim 3, which is characterized in that first work-function layer, The material of one workfunction material, the second workfunction material and the 3rd work-function layer is TiN；The thickness of first work-function layer It spends and isExtremelyThe thickness of first workfunction material isExtremelySecond workfunction material Thickness isExtremelyThe thickness of 3rd work-function layer isExtremely

5. the manufacturing method of semiconductor structure as described in claim 1, which is characterized in that after forming the gate dielectric layer, It is formed on the gate dielectric layer before the first work-function layer, the manufacturing method further includes：

Cap layer is formed on the gate dielectric layer；Etching stop layer is formed in the cap layer；

After the second work-function layer and the first work-function layer that remove the first N-type threshold voltage area and transmission gate transistor area, The is formed in remaining second work-function layer, on the gate dielectric layer of the first N-type threshold voltage area and transmission gate transistor area Before three work-function layers, the manufacturing method further includes：Remove the etching stop layer and cap layer of the transmission gate transistor area.

6. the manufacturing method of semiconductor structure as claimed in claim 5, which is characterized in that the material of the cap layer is TiN Or TiSiN.

7. the manufacturing method of semiconductor structure as claimed in claim 5, which is characterized in that the material of the etching stop layer is TaN or TaSiN.

8. the manufacturing method of semiconductor structure as described in claim 1, which is characterized in that described in the step of substrate is provided Transmission gate transistor area includes the first transmission gate transistor area and the second transmission gate transistor area；

The processing step that is carried out to the first transmission gate transistor area and the first N-type threshold voltage area is carried out Processing step is identical；

Alternatively, the processing step carried out to the second transmission gate transistor area with to institute of the first N-type threshold voltage area The processing step of progress is identical；

Alternatively, to the first transmission gate transistor area, the second transmission gate transistor area and the first N-type threshold voltage area institute into Capable processing step is identical.

9. the manufacturing method of semiconductor structure as described in claim 1, which is characterized in that the first N-type threshold voltage area Including N-type ultralow threshold value voltage zone and N-type low-threshold power pressure area, the second N-type threshold voltage area is N-type standard threshold voltage Area；The first p-type threshold voltage area is p-type standard threshold voltage area, and it is ultralow that the second p-type threshold voltage area includes p-type Threshold voltage area and p-type low-threshold power pressure area；

It after the substrate is provided, is formed before the gate dielectric layer, the manufacturing method further includes：To the N-type ultralow threshold value The corresponding substrate in voltage zone carries out the first N-type threshold value and adjusts doping treatment, to the corresponding substrate of the N-type low-threshold power pressure area into The second N-type of row threshold value adjusts doping treatment；First p-type threshold value tune is carried out to the corresponding substrate in the p-type ultralow threshold value voltage zone Doping treatment is saved, carrying out the second p-type threshold value to the corresponding substrate of the p-type low-threshold power pressure area adjusts doping treatment.

10. the manufacturing method of semiconductor structure as described in claim 1, which is characterized in that the gate dielectric layer includes interface Layer and the high-k gate dielectric layer positioned at the interface layer surfaces.

11. the manufacturing method of semiconductor structure as described in claim 1, which is characterized in that the substrate is used to form fin Field-effect tube, in the step of providing substrate, the substrate includes substrate and discrete fin on the substrate；

In the step of forming gate dielectric layer, the gate dielectric layer covers the atop part table of the fin across the fin Face and sidewall surfaces.

12. a kind of semiconductor structure, which is characterized in that including：

Substrate, the substrate includes N-type logic area, p-type logic area, pull up transistor area and transmission gate transistor area, wherein, The N-type logic area includes：The first N-type threshold voltage area with the first N-type device and the with the second N-type device Two N-type threshold voltage areas, the threshold voltage of the first N-type device are less than the threshold voltage of the second N-type device；The P Type logic area includes：The first p-type threshold voltage area with the first P-type device and the second p-type with the second P-type device Threshold voltage area, the threshold voltage of first P-type device are more than the threshold voltage of second P-type device；

Gate dielectric layer, positioned at the N-type logic area, p-type logic area, pull up transistor area and transmission gate transistor area part In substrate；

First work-function layer, on the gate dielectric layer in the second p-type threshold voltage area；

Second work-function layer, it is on the gate dielectric layer in the first p-type threshold voltage area and the area that pulls up transistor and described In first work-function layer；

3rd work-function layer, on the gate dielectric layer of the first N-type threshold voltage area and transmission gate transistor area, Yi Jisuo It states in the second work-function layer.

13. semiconductor structure as claimed in claim 12, which is characterized in that second work-function layer includes：Positioned at described The first work content on the gate dielectric layer in the first p-type threshold voltage area and the area that pulls up transistor and in first work-function layer Number material layer；The second workfunction material in first workfunction material, second workfunction material and First workfunction material is used to form second work-function layer；

Second workfunction material is also located on the gate dielectric layer in the second N-type threshold voltage area；

3rd work-function layer is also located in second workfunction material in the second N-type threshold voltage area.

14. semiconductor structure as claimed in claim 13, which is characterized in that the material of first work-function layer for Ta, One or more of TiN, TaN, TaSiN or TiSiN；The material of first workfunction material for Ta, TiN, TaN, One or more of TaSiN or TiSiN；The material of second workfunction material for Ta, TiN, TaN, TaSiN or One or more of TiSiN；The material of 3rd work-function layer be Ta, TiN, TaN, TaSiN or TiSiN in one kind or It is several.

15. the semiconductor structure as described in claim 13 or 14, which is characterized in that first work-function layer, the first work content The material of number material layer, the second workfunction material and the 3rd work-function layer is TiN；The thickness of first work-function layer isExtremelyThe thickness of first workfunction material isExtremelyThe thickness of second workfunction material ForExtremelyThe thickness of 3rd work-function layer isExtremely

16. semiconductor structure as claimed in claim 13, which is characterized in that the transmission gate transistor area includes the first transmission Door transistor area and the second transmission gate transistor area；

Second workfunction material is also located on the gate dielectric layer of the first transmission gate transistor area, the 3rd work content Several layers are also located in the second workfunction material of the first transmission gate transistor area and the second transmission gate transistor area On gate dielectric layer；

Alternatively, second workfunction material is also located on the gate dielectric layer of the second transmission gate transistor area, described Three work-function layers are also located in the second workfunction material of the second transmission gate transistor area and the first transmission gate crystal On the gate dielectric layer in area under control；

Alternatively, the 3rd work-function layer is also located at the grid of the first transmission gate transistor area and the second transmission gate transistor area On dielectric layer.

17. semiconductor structure as claimed in claim 12, which is characterized in that the gate dielectric layer includes boundary layer and is located at The high-k gate dielectric layer of the interface layer surfaces.

18. semiconductor structure as claimed in claim 12, which is characterized in that the semiconductor structure is fin field effect pipe, The substrate includes substrate and discrete fin on the substrate；

The gate dielectric layer covers atop part surface and the sidewall surfaces of the fin across the fin.