CN108122912B - SRAM device and its manufacturing method - Google Patents
SRAM device and its manufacturing method Download PDFInfo
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- CN108122912B CN108122912B CN201611081243.8A CN201611081243A CN108122912B CN 108122912 B CN108122912 B CN 108122912B CN 201611081243 A CN201611081243 A CN 201611081243A CN 108122912 B CN108122912 B CN 108122912B
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Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
- H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/495—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
Abstract
A kind of SRAM device and its manufacturing method, manufacturing method include: to form gate dielectric layer on the part of substrate for pulling up transistor area and pull-down transistor area；The first work-function layer is formed on gate dielectric layer；Etching removes first work-function layer in the pull-down transistor area；The second work-function layer is formed in remaining first work-function layer and pull-down transistor area, the material of second work-function layer is p-type work function material；Diffusion barrier layer is formed on residue the second work-function layer side wall and remaining first work-function layer side wall in the area that pulls up transistor；On the diffusion barrier layer, third work-function layer is formed at the top of second work-function layer in the area that pulls up transistor on the upper and gate dielectric layer in pull-down transistor area, the material of the third work-function layer is N-type work function material；Gate electrode layer is formed in the third work-function layer.The present invention improves the electrical parameter mismatch of SRAM device, optimizes the electric property of the SRAM device of formation.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, in particular to a kind of SRAM device and its manufacturing method.
Background technique
In current semiconductor industry, IC products can be divided mainly into three categories type: logic, memory and simulation
Circuit, wherein memory device accounts for sizable ratio in IC products.As semiconductor technology develops, to memory
Part is more widely applied, and needs for the memory device and other device regions to be formed simultaneously on a single die, with shape
At embedded semiconductor storing equipment.Such as central processing unit will be embedded in the memory device, then it is required that described deposit
Memory device carries out specification and corresponding electricity compatible, and that keep original memory device with the central processing unit platform of insertion
Performance.
Generally, it needs to carry out the memory device with the standard logical devices of insertion compatible.It is partly led for embedded
For body device, it is generally divided into logic area and memory block, logic area generally includes logical device, and memory block then includes memory
Part.With the development of memory technology, there is various types of semiconductor memories, such as static random random access memory
(SRAM, Static Random Access Memory), dynamic RAM (DRAM, Dynamic Random Access
Memory), Erasable Programmable Read Only Memory EPROM (EPROM, Erasable Programmable Read-Only Memory),
Electrically erasable programmable read-only memory (EEPROM, Electrically Erasable Programmable Read-Only)
With flash memory (Flash).Since Static RAM has many advantages, such as low-power consumption and very fast operating rate, so that static random is deposited
Reservoir and forming method thereof receives more and more attention.
However, the electric property for the SRAM device that the prior art is formed is to be improved.
Summary of the invention
Problems solved by the invention is to provide a kind of SRAM device and its manufacturing method, improves the electricity of the SRAM device of formation
Learn performance.
To solve the above problems, the present invention provides a kind of manufacturing method of SRAM device, comprising: provide substrate, the base
Bottom includes adjacent pull up transistor area and pull-down transistor area；In area and the pull-down transistor area of pulling up transistor
Part of substrate on form gate dielectric layer；The first work-function layer is formed on the gate dielectric layer, first work-function layer
Material is p-type work function material；Etching removes first work-function layer in the pull-down transistor area；In remaining first work-function layer
And the second work-function layer is formed in pull-down transistor area, the material of second work-function layer is p-type work function material；Etching
Remove second work-function layer in the pull-down transistor area；The area that pulls up transistor residue the second work-function layer side wall with
And diffusion barrier layer is formed on remaining first work-function layer side wall；On the diffusion barrier layer, the area that pulls up transistor second
Third work-function layer is formed at the top of work-function layer on the upper and gate dielectric layer in pull-down transistor area, the third work-function layer
Material is N-type work function material；Gate electrode layer is formed in the third work-function layer.
Optionally, the diffusion barrier layer is formed using depositing operation；In the processing step for forming the diffusion barrier layer
In, the shape on the gate dielectric layer in the upper and described pull-down transistor area also at the top of second work-function layer in the area that pulls up transistor
At the diffusion barrier layer；In the processing step for forming the third work-function layer, the third work-function layer position of formation
In on the diffusion barrier layer in pull up transistor area and the pull-down transistor area.
Optionally, the diffusion barrier layer is formed using atom layer deposition process.
Optionally, the diffusion barrier layer with a thickness of 5 angstroms~20 angstroms.
Optionally, the material of the diffusion barrier layer is TaN or TaCN.
Optionally, after the second work-function layer that etching removes the pull-down transistor area, remaining first work-function layer with
And remaining second work-function layer flushes in the area that pulls up transistor with the side wall at adjacent place, pull-down transistor area.
Optionally, the material of first work-function layer is one or more of Ta, TiN, TaN, TaSiN or TiSiN；
The material of second work-function layer is one or more of Ta, TiN, TaN, TaSiN or TiSiN；The third work function
The material of layer is one of TiAl, TiAlC, TaAlN, TiAlN, TaCN and AlN or a variety of.
Optionally, after forming the gate dielectric layer, before formation first work-function layer, further includes: described
Protective layer is formed on gate dielectric layer.
Optionally, the processing step for forming the protective layer includes: to form cap on the gate dielectric layer；Described
Etching stop layer is formed in cap, and the material of the etching stop layer is different from the material of first work-function layer.
Optionally, the substrate further includes channel gate transistor area；In the work for forming the gate dielectric layer and protective layer
In skill step, gate dielectric layer and the guarantor on gate dielectric layer are formed also on the part of substrate in channel gate transistor area
Sheath；In the processing step for forming first work-function layer, the first work content also is formed in channel gate transistor area
Several layers；In the processing step for forming second work-function layer, described second also is formed in channel gate transistor area
Work-function layer；In the processing step for forming the third work-function layer, also in channel gate transistor area described in formation
Third work-function layer.
Optionally, before forming second work-function layer, first function in etching removal channel gate transistor area
Function layer and protective layer；Grid in the processing step for forming second work-function layer, in channel gate transistor area
The second work-function layer is formed on dielectric layer.
The present invention also provides a kind of SRAM devices, comprising: substrate, the substrate include it is adjacent pull up transistor area with
And pull-down transistor area；Gate dielectric layer on the part of substrate in pull up transistor area and the pull-down transistor area；Position
In the first work-function layer on the gate dielectric layer for pulling up transistor area and second in first work-function layer
The material of work-function layer, first work-function layer and the second work-function layer is p-type work function material；Positioned at the pull-up
The the second work-function layer side wall and the diffusion barrier layer on the first work-function layer side wall of transistor area；Positioned at the diffusion barrier
Third work function on floor, at the top of second work-function layer in the area that pulls up transistor on the upper and gate dielectric layer in pull-down transistor area
Layer, the material of the third work-function layer are N-type work function material；Gate electrode layer in the third work-function layer.
Optionally, the diffusion barrier layer be also located at it is upper at the top of second work-function layer in the area that pulls up transistor and under
On the gate dielectric layer in crystal pulling area under control.
Optionally, the diffusion barrier layer with a thickness of 5 angstroms~20 angstroms.
Optionally, the material of the diffusion barrier layer is TaN or TaCN.
Optionally, first work-function layer and the second work-function layer pull up transistor and area's pull-down transistor described
The side wall at adjacent place, area flushes.
Optionally, the SRAM device further include: gate dielectric layer and the first work function positioned at the area that pulls up transistor
Layer between protective layer, and the protective layer be also located at the pull-down transistor area gate dielectric layer and the third work-function layer
Between.
Optionally, the substrate further includes channel gate transistor area；Wherein, the gate dielectric layer is also located at the channel grid
On the part of substrate of transistor area；And second work-function layer is also located on the gate dielectric layer in channel gate transistor area；
The third work-function layer is also located in second work-function layer in channel gate transistor area.
Optionally, the substrate includes substrate and the discrete fin on the substrate.
Optionally, the area that pulls up transistor is with a fin；There are two fins for the pull-down transistor area tool.
Compared with prior art, technical solution of the present invention has the advantage that
In the technical solution of the manufacturing method of SRAM device provided by the invention, in area and the lower crystal pulling of pulling up transistor
After forming the first work-function layer on the gate dielectric layer in area under control, etching removes first work-function layer in the pull-down transistor area；It connects
Form the second work-function layer, first work-function layer and second in remaining first work-function layer and pull-down transistor area
The material of work-function layer is p-type work function material；Then etching removes second work-function layer in the pull-down transistor area；So
Diffusion barrier layer is formed on the first work-function layer side wall and the second work-function layer side wall in the area that pulls up transistor afterwards；Described
It is formed on the upper and gate dielectric layer in pull-down transistor area on diffusion barrier layer, at the top of second work-function layer in the area that pulls up transistor
Third work-function layer, the material of the third work-function layer are N-type work function material；Grid are formed in the third work-function layer
Electrode layer.The present invention meet pull up transistor and pull-down transistor to threshold voltage requirements while, in the pull-up
It is formed and is spread on the first work-function layer side wall and the second work-function layer side wall of transistor area and pull-down transistor area intersection
Barrier layer, the diffusion barrier layer are conducive to stop the cross between the first work-function layer of the intersection and third work-function layer
To diffusion, be conducive to the horizontal proliferation between the second work-function layer for stopping the intersection and the third work-function layer, from
And the electrical parameter mismatch to pull up transistor between pull-down transistor formed is improved, improve the electricity of the SRAM device of formation
Performance.
In optinal plan, the substrate further includes channel gate transistor area；Before forming the second work-function layer, institute is removed
First work-function layer and gate dielectric layer in channel gate transistor area are stated, so that the corresponding work function in channel gate transistor area
Layer thinner thickness, therefore the channel gate transistor threshold voltage being correspondingly formed is lower, and then improves the operation of channel gate transistor
Rate, the further electric property for improving the SRAM device formed.
In optinal plan, after the second work-function layer that etching removes the pull-down transistor area, remaining first work content
Several floor and remaining second work-function layer flush in the area that pulls up transistor with the side wall at adjacent place, pull-down transistor area, are
Diffusion barrier layer is formed in the intersection and provides good process conditions, to improve the thickness of the diffusion barrier layer of formation
Uniformity further improves the ability that the diffusion barrier layer stops the intersection work-function layer phase counterdiffusion.
The present invention also provides a kind of superior SRAM device of structural behaviour, area and the pull-down transistor area of pulling up transistor
It is adjacent, and since first work-function layer and the second work-function layer are only located at the area that pulls up transistor；Upper crystal pulling
Quilt between the first work-function layer and the second work-function layer and the third work-function layer of area under control and pull-down transistor area intersection
The diffusion barrier layer stops, and the diffusion barrier layer is conducive to the first work-function layer for stopping the intersection and third work content
Mutually transverse diffusion between several layers, and be conducive to stop the intersection the second work-function layer and the third work-function layer it
Between mutually transverse diffusion, so as to improve the electric property of SRAM device, for example, improve pull up transistor with pull-down transistor it
Between electrical parameter mismatch.
Detailed description of the invention
Fig. 1 is a kind of overlooking structure diagram of SRAM device；
Fig. 2 to Figure 14 is the structural schematic diagram of SRAM device forming process provided in an embodiment of the present invention.
Specific embodiment
It can be seen from background technology that the electric property for the SRAM device that the prior art is formed is to be improved.
It is analyzed now in conjunction with a kind of SRAM device, with reference to Fig. 1, Fig. 1 is a kind of overlooking structure diagram of SRAM device,
The SRAM device include pull-up (PU, Pull Up) transistor, drop-down (PD, Pull Down) transistor and channel grid (PG,
Pass Gate) transistor, wherein first area 101 is to be formed with the region to pull up transistor, and second area 102 is to be formed with
The region of pull-down transistor, third region 103 is the region for being formed with channel gate transistor, common, pull up transistor for
PMOS tube, pull-down transistor and channel gate transistor are NMOS tube.
By taking SRAM device is FinFET as an example, first area 101 and second area 102 are adjacent, and described first
Region 101, second area 102 and third region 103 all have fin 105, and the first area 101 has 1 fin
105, the second area 102 has 2 fins 105, and the second area 102 and third region 103 have 1 fin jointly
Portion 105；And the first area 101 and second area 102 share same gate electrode layer 106.
Described to pull up transistor as PMOS device, the pull-down transistor is NMOS device.In order to meet PMOS device simultaneously
The requirement of part and NMOS device improvement threshold voltage (Threshold Voltage), generallys use different metal material conducts
Work-function layer (WF, Work Function) material in NMOS device and the gate structure of PMOS device, work content in NMOS device
Several layers are known as N-type work function material, and work-function layer is known as p-type work function material in PMOS device.When NMOS device and PMOS device
When part shares the same gate electrode layer, between NMOS device and PMOS device intersection N-type workfunction layer and P-type workfunction layer
Can have the interface N/P (N/P boundary Interface), the mutual shadow of work function material phase counterdiffusion of the interface N/P
It rings, the performance of NMOS device and PMOS device is caused to change.
For SRAM device, pulling up transistor with the work-function layer of pull-down transistor intersection is usually lamination knot
Structure, and existing N-type workfunction layer has P-type workfunction layer again in the work-function layer of the intersection, so that the function to pull up transistor
It influences each other between function layer and the work-function layer of pull-down transistor, for example, the work-function layer and drop-down to pull up transistor
The work-function layer of transistor it is mutually transverse diffusion influence each other, so as to cause SRAM device pull up transistor and pull-down transistor
Between electrical parameter mismatch (Mismatch) be deteriorated, and then influence SRAM device electric property.
Wherein, the horizontal proliferation is mainly that the Al ion in N-type work function material is spread into p-type work function material,
It is further to influence upper crystal pulling accordingly to affect the equivalent work function value of N-type workfunction layer and P-type workfunction layer
The threshold voltage of pipe and pull-down transistor.
If it is described pull up transistor it is more single with the work-function layer type of pull-down transistor intersection, can be effective
It reduces the phase counterdiffusion to pull up transistor between the work-function layer of pull-down transistor intersection to influence each other, so as to improve SRAM
The electric property of device, and meet reading redundancy (read margin) and wanting for redundancy (read margin) is written
It asks.
To solve the above problems, the present invention provides a kind of manufacturing method of SRAM device, comprising: provide substrate, the base
Bottom includes adjacent pull up transistor area and pull-down transistor area；In area and the pull-down transistor area of pulling up transistor
Part of substrate on form gate dielectric layer；The first work-function layer is formed on the gate dielectric layer, first work-function layer
Material is p-type work function material；Etching removes first work-function layer in the pull-down transistor area；In remaining first work-function layer
And the second work-function layer is formed in pull-down transistor area, the material of second work-function layer is p-type work function material；Etching
Remove second work-function layer in the pull-down transistor area；It is upper at the top of second work-function layer in the area that pulls up transistor, on
On residue the second work-function layer side wall in crystal pulling area under control and remaining first work-function layer side wall and the pull-down transistor
Third work-function layer is formed in area, the material of the third work-function layer is N-type work function material；In the third work-function layer
Upper formation gate electrode layer.
In the SRAM device that the present invention is formed, pull up transistor and the work-function layer interface of pull-down transistor intersection list
One, the problem of work-function layer phase counterdiffusion of the intersection has been reduced or avoided, so as to improve pulling up transistor and pulling down
The electrical parameter mismatch of transistor, optimizes the electric property for the SRAM device to be formed.
To make the above purposes, features and advantages of the invention more obvious and understandable, with reference to the accompanying drawing to the present invention
Specific embodiment be described in detail.
Fig. 2 to Figure 14 is the structural schematic diagram of SRAM device forming process provided in an embodiment of the present invention.
It is overlooking structure diagram with reference to Fig. 2 and Fig. 3, Fig. 2, Fig. 3 is the schematic diagram of the section structure in Fig. 2 along the direction AA1,
And for the ease of illustration and explanation, the part between pull-down transistor area and channel gate transistor area in Fig. 3 and isolation
Structure is not shown, and provides substrate, and the substrate includes the adjacent area I and pull-down transistor area II that pulls up transistor.
The area I that pulls up transistor is to be subsequently formed to pull up transistor to provide technique platform, the pull-down transistor area II
Technique platform is provided to be subsequently formed pull-down transistor.
In the present embodiment, the pull-down transistor area II includes the first pull-down transistor area (not indicating) and the second drop-down
Transistor area (does not indicate), wherein first pull-down transistor area and the area that pulls up transistor are adjacent；Under described first
Crystal pulling area under control provides technique platform to be subsequently formed the first pull-down transistor, and second pull-down transistor area is to be subsequently formed
Second pull-down transistor provides technique platform, and first pull-down transistor is in parallel with the second pull-down transistor composition
Pull-down transistor.
In the present embodiment, the substrate further includes channel gate transistor area III, after channel gate transistor area III is
The continuous channel gate transistor that formed provides technique platform.
In the present embodiment, the area I that pulls up transistor is PMOS area, and the pull-down transistor area II is NMOS area,
Channel gate transistor area III is NMOS area.
By the SRAM device of formation be FinFET for, the substrate include the substrate include: substrate 201 and
Discrete fin 202 on the substrate 201.In order to be electrically isolated adjacent fin 202 and adjacent devices, the substrate is also
It include: the isolation structure 214 on the substrate 201 that the fin 202 exposes, the isolation structure 214 covers fin 202
Partial sidewall, and lower than 202 top of fin at the top of the isolation structure 214.
The material of the isolation structure 214 is silica, silicon nitride or silicon oxynitride.In the present embodiment, the isolation junction
The material of structure 214 is silica.
In another embodiment, the SRAM device is planar transistor, and the substrate is planar substrates, the plane base
Bottom is silicon substrate, germanium substrate, silicon-Germanium substrate or silicon carbide substrates, silicon-on-insulator substrate or germanium substrate on insulator, glass lined
Bottom or III-V compound substrate (such as gallium nitride substrate or gallium arsenide substrate etc.), gate structure are formed in the plane base
Bottom surface.
The material of the substrate 201 is silicon, germanium, SiGe, silicon carbide, GaAs or gallium indium, and the substrate 201 can also
It is enough the germanium substrate on the silicon substrate or insulator on insulator；The material of the fin 202 includes silicon, germanium, SiGe, carbon
SiClx, GaAs or gallium indium.In the present embodiment, the substrate 201 is silicon substrate, and the material of the fin 202 is silicon.
In the present embodiment, the area II, pull-down transistor area includes the first pull-down transistor area and the second pull-down transistor
Area；Correspondingly, the area I that pulls up transistor is with a fin 202, the pull-down transistor area II has there are two fin 202,
One of fin 202 provides technique platform to form the first pull-down transistor, another fin 202 is to form the second lower crystal pulling
Body pipe provides technique platform；Channel gate transistor area III has a fin 202, and channel gate transistor area III
A fin 202 is shared with the pull-down transistor area II.
It should also be noted that, in other embodiments, it can also be according to the different performance of SRAM device to be formed
Demand, quantity, the quantity and channel grid of the fin in pull-down transistor area of the fin in the area that accordingly pulls up transistor described in adjustment
The quantity of the fin of transistor area.
In conjunction with reference Fig. 4, in the present embodiment, gate electrode layer (high k is formed after forming high-k gate dielectric layer after
Last metal gate last) technique, form the gate structure of SRAM device.Therefore, the forming method further include:
Pseudo- grid structure 210 is formed in the substrate of the area I and pull-down transistor area II that pulls up transistor.
Dummy gate structure 210 is to be subsequently formed the gate structure of SRAM device to take up space position.Specifically, described
The pseudo- grid structure 210 of the fin 202 is developed across on isolation structure 214, and dummy gate structure 210 covers the fin
202 atop part surface and partial sidewall surface.
Dummy gate structure 210 is single layer structure or laminated construction.Dummy gate structure 210 includes pseudo- grid layer；Or institute
Stating pseudo- grid structure 210 includes pseudo- oxide layer and the pseudo- grid layer in the pseudo- oxide layer.Wherein, the material of the pseudo- grid layer
For polysilicon, silica, silicon nitride, silicon oxynitride, silicon carbide, carbonitride of silicium, carbon silicon oxynitride or amorphous carbon, the pseudo- oxidation
The material of layer is silica or silicon oxynitride.
In the present embodiment, the work of pseudo- grid structure 210 is formed on the area I and pull-down transistor area II that pulls up transistor
In skill step, pseudo- grid structure 210 is formed also on channel gate transistor area II.
In the present embodiment, since the area I and pull-down transistor area II that pulls up transistor is adjacent, accordingly make institute
Pseudo- grid structure 210 is stated across the area I and pull-down transistor area II that pulls up transistor, correspondingly, the gate electrode being subsequently formed
Floor is across the area I and pull-down transistor area II that pulls up transistor.
After forming dummy gate structure 210, the manufacturing method further include: in each 210 two sides of region puppet grid structure
Fin 202 in form the source and drain doping area of each transistor.
After forming the source and drain doping area, dummy gate structure 210 is removed.In the present embodiment, dry method can be used
Etching technics, wet-etching technology or SiCoNi etching system remove dummy gate structure 210.
It should be noted that before removing dummy gate structure 210, the manufacturing method further include: in the pseudo- grid
Interlayer dielectric layer (not shown) is formed in the substrate that structure 210 exposes, the interlayer dielectric layer exposes dummy gate structure 210
Top.
With reference to Fig. 5, after removing dummy gate structure 210, in area I and the pull-down transistor area of pulling up transistor
Gate dielectric layer 204 is formed on the part of substrate of II.
The substrate further includes channel gate transistor area III, therefore in the processing step for forming the gate dielectric layer 204
In, gate dielectric layer 204 is formed also on the part of substrate of channel gate transistor area III.
In the present embodiment, the gate dielectric layer 204 include boundary layer (IL, Interfacial Layer) (not indicating) with
And the high-k gate dielectric layer (not indicating) positioned at the interface layer surfaces.Specifically, described in the step of forming gate dielectric layer 204
Gate dielectric layer 204 covers atop part surface and the sidewall surfaces of the fin 202 across the fin 202.
The boundary layer provides good interface basis to form the high-k gate dielectric layer, is situated between to improve the high k grid
The quality of matter layer reduces the interface state density between the high-k gate dielectric layer and fin 202, and avoids the high-k gate dielectric layer
Adverse effect caused by directly being contacted with fin 202.The material of the boundary layer is silica or silicon oxynitride.
In the present embodiment, the boundary layer is formed using oxidation technology, is formed by boundary layer and is only formed in and expose
202 top surface of fin and sidewall surfaces.In other embodiments, the boundary layer, example can also be formed using depositing operation
Such as chemical vapor deposition process, physical gas-phase deposition or atom layer deposition process, be formed by boundary layer be also located at it is described
On isolation structure.
The material of the high-k gate dielectric layer is the gate medium material that relative dielectric constant is greater than silica relative dielectric constant
Material.In the present embodiment, the material of the high-k gate dielectric layer is HfO2.In other embodiments, the material of the high-k gate dielectric layer
Material can also be HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2Or Al2O3.Chemical vapor deposition, physics can be used
Vapor deposition or atom layer deposition process form the high-k gate dielectric layer.In the present embodiment, formed using atom layer deposition process
The high-k gate dielectric layer.
Subsequent step includes forming work-function layer on gate dielectric layer 204.In order in subsequent processing step, to described
Gate dielectric layer 204 plays a protective role, before forming the first work-function layer, further includes: formed on the gate dielectric layer 204
Protective layer.
With reference to Fig. 6, the processing step for forming the protective layer includes: to form cap on the gate dielectric layer 204
205；Form etching stop layer 206 in the cap 205, and the material of the etching stop layer 206 be subsequently formed
The material of first work-function layer is different.
Grid in the present embodiment, in the processing step for forming the protective layer, also in channel gate transistor area III
The protective layer is formed on dielectric layer 204.
The cap 205 can play the role of the protection gate dielectric layer 204, prevent subsequent etching technics to institute
Stating gate dielectric layer 204 causes unnecessary etching to lose, and the cap 205, which also helps, stops subsequent formed gate electrode layer
In easy diffused metal ions spread into the gate dielectric layer 204.
In the present embodiment, the material of the cap 205 is TiN, forms the cap using atom layer deposition process,
Make the cap 205 that there is good step coverage.
The etching stop layer 206 is different from the material of subsequent formed work-function layer, so that described in subsequent etching
The etching technics of work-function layer is smaller to the etch rate of the etching stop layer 206, therefore the etching stop layer 206 is rear
Play the role of etching stopping in the etching technics of the continuous etching work-function layer, can be made to avoid to the gate dielectric layer 204
At etching injury.
In the present embodiment, the material of the etching stop layer is TaN, forms the etch-stop using atom layer deposition process
Only layer makes the etching stop layer have good step coverage.
With reference to Fig. 7, the first work-function layer 207 is formed on the gate dielectric layer 204, first work-function layer 207
Material is p-type work function material.
In the processing step for forming first work-function layer 207, also formed on channel gate transistor area III
First work-function layer 207.In the present embodiment, due to forming matcoveredn on the gate dielectric layer 204, in the guarantor
First work-function layer 207 is formed on sheath；Specifically, first work function is formed on the etching stop layer 206
Layer 207.
The a part of first work-function layer 207 as the corresponding work-function layer of area I that pulls up transistor.
The p-type work function material workfunction range is 5.1eV to 5.5eV, for example, 5.2eV, 5.3eV or 5.4eV.Institute
The material for stating the first work-function layer 207 is one or more of Ta, TiN, TaN, TaSiN or TiSiN, can use chemical gas
Phase depositing operation, physical gas-phase deposition or atom layer deposition process form first work-function layer 207.
In the present embodiment, the material of first work-function layer 207 is TiN, first work-function layer 207 with a thickness of
10 angstroms~30 angstroms.
With reference to Fig. 8, etching removes the first work-function layer 207 of the pull-down transistor area II.
In the present embodiment, in order to meet the needs of pull-down transistor is to threshold voltage, the removal lower crystal pulling need to be etched
The first work-function layer 207 of area under control II retains the first work-function layer 207 for being located at the area I that pulls up transistor as upper crystal pulling
A part of the work-function layer of body pipe.
Specifically, the processing step that etching removes the first work-function layer 207 of the pull-down transistor area II includes: in institute
It states and forms the first graph layer, first figure in the first work-function layer 207 of pull up transistor area I and channel gate transistor area
Shape floor exposes the first work-function layer 207 of the pull-down transistor area II；Using first graph layer as exposure mask, etching removal institute
State the first work-function layer 207 of pull-down transistor area II；Remove first graph layer.
In the technical process that etching removes the first work-function layer 207 of the pull-down transistor area II, under described
The etching stop layer 206 of crystal pulling area under control II plays the role of etching stopping, avoids the gate dielectric layer to pull-down transistor area II
204 cause etching injury.
With reference to Fig. 9, the first work-function layer 207 and protective layer of etching removal channel gate transistor area III.
In the present embodiment, also etching removes the first work-function layer 207 of channel gate transistor area III and protects
Layer, exposes the gate dielectric layer 204 of channel gate transistor area III.Its benefit includes:
Since the first work-function layer 207 and protective layer of channel gate transistor area III are etched removal, so that
The subsequent work-function layer thinner thickness being correspondingly formed in channel gate transistor area III；Channel gate transistor area III is NMOS
Region, for the gate transistor of channel, the more thin corresponding threshold voltage of work-function layer is lower, to be conducive to improve subsequent shape
At channel gate transistor operating rate.
Specifically, the first work-function layer 207 of etching removal channel grid crystal region III and the technique step of protective layer
It suddenly include: shape in the first work-function layer 207 of the area I that pulls up transistor and on the protective layer of pull-down transistor area II
At second graph layer, the second graph floor exposes the first work-function layer 207 of channel gate transistor area III；With institute
Stating second graph layer is exposure mask, the first work-function layer 207 of etching removal channel gate transistor area III, etching stop layer
206 and cap 205, until exposing the gate dielectric layer 204 of channel gate transistor area III；Remove the second graph
Layer.
It should be noted that first etching removes the first work-function layer of the pull-down transistor area II in the present embodiment
207, the first work-function layer 207 and protective layer of rear etching removal channel gate transistor area III.In other embodiments
In, first work-function layer and protective layer in removal channel gate transistor area can also be first etched, it is rear to etch described in removal
First work-function layer in pull-down transistor area；Alternatively, first etching removes the pull-down transistor area and channel gate transistor area
The first work-function layer, the protective layer in rear etching removal channel gate transistor area.
With reference to Figure 10, the second work-function layer is formed in remaining first work-function layer 207 and pull-down transistor area II
208, the material of second work-function layer 208 is p-type work function material.
In the present embodiment, in the processing step for forming second work-function layer 207, in the pull-down transistor area II
Protective layer on form second work-function layer 208.
And in the processing step for forming second work-function layer 208, the shape also on channel gate transistor area III
At second work-function layer 208.Specifically, in the processing step for forming second work-function layer 208, in the channel
Second work-function layer 208 is formed on the gate dielectric layer 204 of gate transistor area III.
Specifically, positioned at the second work function layer 208 of the area I that pulls up transistor and the common structure of the first work-function layer 207
At the work-function layer to pull up transistor being subsequently formed；The second work-function layer 208 positioned at channel gate transistor area III is made
For a part of the work-function layer for the channel gate transistor being subsequently formed.
The material of second work-function layer 208 is one or more of Ta, TiN, TaN, TaSiN or TiSiN.
In the present embodiment, the material of second work-function layer 208 is different from the material of the etching stop layer 207, institute
State the second work-function layer 208 material be TiN, second work-function layer 208 with a thickness of 5 angstroms~30 angstroms.
With reference to Figure 11, etching removes the second work-function layer 208 of the pull-down transistor area II.
In order to meet the requirement of pull-down transistor that pull-down transistor area II is subsequently formed to threshold voltage, needs to etch and go
Except the second work-function layer 208 of the pull-down transistor area II.
Specifically, the processing step that etching removes the second work-function layer 208 of the pull-down transistor area II includes: in institute
State in the second work-function layer 208 formation third graph layer, the third graph layer exposes the of the pull-down transistor area II
Two work-function layers 208；Using the third graph layer as exposure mask, etching removes the second work-function layer of the pull-down transistor area II
208, until exposing the protective layer；Remove the third graph layer.
In the technical process that etching removes the second work-function layer 208 of the pull-down transistor area II, the lower crystal pulling
The etching stop layer 206 of body area under control II plays the role of etching stopping, and the gate dielectric layer 204 to pull-down transistor area II is avoided to make
At etching injury.
In the present embodiment, after the second work-function layer 208 that etching removes the pull-down transistor area II, remaining first function
Function floor 207 and remaining second work-function layer 208 are at area I and the adjacent place II, pull-down transistor area of pulling up transistor
Side wall flush.
208 side wall of the second work-function layer of residue and remaining first work content with reference to Figure 12, in the area I that pulls up transistor
Diffusion barrier layer 212 is formed on several layers of 207 side wall.
The effect of the diffusion barrier layer 212 includes: rear extended meeting in area I and the pull-down transistor area of pulling up transistor
Third work-function layer is formed on II, and the material of the third work-function layer is N-type work function material；The diffusion barrier layer
212 be conducive to stop described in pull up transistor it is mutually transverse between area I and the work-function layer of pull-down transistor area II intersection
Diffusion, for example, stopping the mutually transverse expansion between the first work-function layer 207 of the intersection and third work-function layer material
It dissipates, stops the mutually transverse diffusion between the second work-function layer 208 of the intersection and the third work-function layer material, from
And improve the electrical parameter mismatch to pull up transistor between pull-down transistor being subsequently formed.
In the present embodiment, in order to reduce the technology difficulty to form the diffusion barrier layer 212, institute is formed using depositing operation
State diffusion barrier layer 212；In the processing step for forming the diffusion barrier layer 212, also in the area I that pulls up transistor the
The diffusion barrier layer 212 is formed on the upper and gate dielectric layer 204 of pull-down transistor area II at the top of two work-function layers 208.
Specifically, in the present embodiment, due to being also formed with protection on the gate dielectric layer 204 of the pull-down transistor area II
Layer, therefore on the gate dielectric layer 204 of the pull-down transistor area II in the processing step of formation diffusion barrier layer 212, in institute
It states and forms the diffusion barrier layer 212 on the protective layer of pull-down transistor area II.
The substrate further includes channel gate transistor area III, for this purpose, in the technique step for forming the diffusion barrier layer 212
In rapid, the diffusion barrier layer 212 also is formed in the second work-function layer 208 of channel gate transistor area III.
In the present embodiment, the material of the diffusion barrier layer 212 is TaN.In other embodiments, the diffusion barrier layer
212 material can also be TaCN.
The thickness of the diffusion barrier layer 212 is unsuitable excessively thin, also unsuitable blocked up.If the thickness of the diffusion barrier layer 212
Spend thin, then the diffusion barrier layer 212 stops the ability of mutually transverse diffusion between the work-function layer of subsequent intersection excessively weak；
If the thickness of the diffusion barrier layer 212 is blocked up, the diffusion barrier layer 212 can be to the threshold that pulls up transistor being subsequently formed
Threshold voltage or pull-down transistor threshold voltage cause adverse effect.
For this purpose, in the present embodiment, the diffusion barrier layer 212 with a thickness of 5 angstroms~20 angstroms.
In the present embodiment, the diffusion barrier layer 212 is formed using atom layer deposition process, is conducive to improve the diffusion
The Step Coverage ability on barrier layer 212 improves the thickness uniformity of the diffusion barrier layer 212 of formation.It should be noted that at it
In his embodiment, chemical vapor deposition or physical gas-phase deposition can also be used, the diffusion barrier layer is formed.
Further, since remaining first work-function layer 207 and remaining second work-function layer 208 are in the area that pulls up transistor
I and the side wall at the adjacent place II, pull-down transistor area flush, so that in 207 side wall of the first work-function layer and the second function
The pattern of the diffusion barrier layer 212 formed on 208 side wall of function layer is good and the thickness uniformity is good, to further improve institute
State the ability that diffusion barrier layer 212 stops mutually transverse diffusion between work-function layer.
With reference to Figure 13, on the diffusion barrier layer 212, at the top of the second work-function layer 208 for the area I that pulls up transistor on
And third work-function layer 209, the material of the third work-function layer 209 are formed on the gate dielectric layer 204 of pull-down transistor area II
For N-type work function material.
In the present embodiment, in the processing step for forming the third work-function layer 209, the third work function of formation
Floor 209 is located on the diffusion barrier layer 212 of the area I and pull-down transistor area II that pulls up transistor；And described the formed
Three work-function layers 209 are also located on the diffusion barrier layer 212 of channel gate transistor area III.
Third work-function layer 209 positioned at the pull-down transistor area II is as the corresponding work function of pull-down transistor area II
Layer, for adjusting the threshold voltage for the pull-down transistor being subsequently formed；Positioned at the third work content of channel gate transistor area III
Several floor 209 and the second work-function layer 208 are as the corresponding work-function layer of channel gate transistor area III, for adjusting subsequent shape
At channel gate transistor threshold voltage.
Upper crystal pulling is used as positioned at the first work-function layer 207 of the area I that pulls up transistor and the second work-function layer 208
The corresponding work-function layer of area under control I, for adjusting the threshold voltage to pull up transistor being subsequently formed.
It should be noted that in the present embodiment, forming the third work content to reduce processing step, save light shield
After several layers 209, retain the third work-function layer 209 for being located at the area I that pulls up transistor.It should also be noted that, at other
In embodiment, after forming the third work-function layer, the third work content in the area that pulls up transistor described in removal can also be etched
Several layers.
The third work-function layer 209 be N-type work function material, N-type work function material workfunction range be 3.9eV extremely
4.5eV, for example, 4eV, 4.1eV or 4.3eV.The material of the third work-function layer 209 be TiAl, TiAlC, TaAlN,
One of TiAlN, TaCN and AlN or a variety of can use chemical vapor deposition process, physical gas-phase deposition or atom
Layer depositing operation forms the third work-function layer 209.In the present embodiment, the material of the third work-function layer 209 is TiAl.
209 thickness of third work-function layer pull up transistor according to and the threshold voltage of channel gate transistor and
It is fixed.In the present embodiment, the third work-function layer 209 with a thickness of 20 angstroms~70 angstroms.
With reference to Figure 14, gate electrode layer 211 is formed in the third work-function layer 209.
In the present embodiment, in the area I that pulls up transistor, pull-down transistor area II and channel gate transistor area III
The gate electrode layer 211 is formed in third work-function layer 209.Wherein, the area I and pull-down transistor area II that pulls up transistor
Gate electrode layer 211 across the area I and pull-down transistor area II that pulls up transistor, it can also be expected that the upper crystal pulling
Area under control I and pull-down transistor area II share the same gate electrode layer 211.
In the present embodiment, the material of the gate electrode layer 211 include one of Al, Cu, Ag, Au, Pt, Ni, Ti or W or
It is a variety of.
Specifically, the processing step for forming the gate electrode layer 211 includes: to be formed in the third work-function layer 209
Gate electrode film, the gate electrode film top are higher than interlayer dielectric layer top (not shown)；Grinding removal is higher than the interlayer
Gate electrode film at the top of dielectric layer forms the gate electrode layer 211.
In the forming method technical solution of SRAM device provided in an embodiment of the present invention, the area I that pulls up transistor is under
Crystal pulling area under control II is adjacent, and since first work-function layer 207 and the second work-function layer 208 are only located at the pull-up
Transistor area I；Pull up transistor the first work-function layer 207 and the second work-function layer of area I and pull-down transistor area II intersection
Stopped between 208 and the third work-function layer 209 by the diffusion barrier layer 212, the diffusion barrier layer 212 is conducive to hinder
Mutually transverse diffusion between the first work-function layer 207 of the intersection and third work-function layer 209 is kept off, and is conducive to stop institute
Mutually transverse diffusion between the second work-function layer 208 of intersection and the third work-function layer 209 is stated, so as to improve being formed
SRAM device electric property, such as improve the electrical parameter mismatch that pulls up transistor between pull-down transistor.
Specifically, the diffusion barrier layer 212 be conducive to stop the Al in the third work-function layer 209 of the intersection from
Son also helps the Al ion in the third work-function layer 209 for stopping the intersection to 207 horizontal proliferation of the first work-function layer
To 208 horizontal proliferation of the second work-function layer.Pull up transistor described in guarantee area I work-function layer equivalent work function value keep not
Become, the equivalent work function value of the work-function layer of the pull-down transistor area II remains unchanged, thus avoid to pull up transistor with
And the threshold voltage of pull-down transistor causes adverse effect, improves the electrical parameter mismatch to pull up transistor with pull-down transistor.
In the present embodiment, in the first work-function layer of pull up transistor the area I and the adjacent place pull-down transistor area II
207 side walls are flushed with 208 side wall of the second work-function layer, and 212 thickness of diffusion barrier layer for being conducive to improve the intersection is uniform
Property, so that the ability that the diffusion barrier layer 212 stops diffusion is further improved, it is further to improve the SRAM device formed
Electric property.
In addition, the SRAM device of the formation also meets reading redundancy and wanting for redundancy is written in the present embodiment
It asks.
Correspondingly, with reference to Figure 14, the SRAM device includes: the present invention also provides a kind of SRAM device
Substrate, the substrate include the adjacent area I and pull-down transistor area II that pulls up transistor；
Gate dielectric layer 204 on the part of substrate for pulling up transistor area I and pull-down transistor area II；
The first work-function layer 207 on the gate dielectric layer 204 for pulling up transistor area I and it is located at described first
The material of the second work-function layer 208 in work-function layer 207, first work-function layer 207 and the second work-function layer 208 is equal
For p-type work function material；
On 207 side wall of 208 side wall of the second work-function layer and the first work-function layer of the area I that pulls up transistor
Diffusion barrier layer 212；
On the diffusion barrier layer 212, upper at the top of the second work-function layer 208 for the area I that pulls up transistor and drop-down
Third work-function layer 209 on the gate dielectric layer 204 of transistor area II, the material of the third work-function layer 209 are N-type work content
Number material；
Gate electrode layer 211 in the third work-function layer 209.
SRAM device provided in an embodiment of the present invention is described in detail below with reference to attached drawing.
In the present embodiment, the pull-down transistor area II includes the first pull-down transistor area and the second pull-down transistor area,
And first pull-down transistor area and the area that pulls up transistor are adjacent, first pull-down transistor area has under first
Pull transistor, second pull-down transistor area have the second pull-down transistor.
The substrate further includes channel gate transistor area III, and the gate dielectric layer 204 is also located at the channel grid crystal
In the substrate of area under control III；Wherein, second work-function layer 208 is also located at the gate dielectric layer of channel gate transistor area III
On 204；The diffusion barrier layer 212 is also located in the second work-function layer 208 of channel gate transistor area III；Described
Three work-function layers 209 are also located on the diffusion barrier layer 212 of channel gate transistor area III.
By the SRAM device be fin field effect pipe for, the substrate include substrate 201 and be located at the substrate
Fin 202 on 201, the substrate further include the isolation structure 214 on the substrate 201 that the fin 202 exposes, institute
It states isolation structure 214 and covers 202 partial sidewall of fin, and pushed up at the top of the isolation structure 214 lower than the fin 202
Portion.
In the present embodiment, the area I that pulls up transistor is with a fin 202；The pull-down transistor area II has two
A fin 202 a, wherein fin 202 provides technique platform for first pull-down transistor area, another fin 202 is
Second pull-down transistor area provides technique platform；Channel gate transistor area III has a fin 202.
Detailed description in relation to the substrate and gate dielectric layer 204 can please refer to the corresponding description of previous embodiment,
This is repeated no more.
The material of first work-function layer 207 is one or more of Ta, TiN, TaN, TaSiN or TiSiN；It is described
The material of second work-function layer 208 is one or more of Ta, TiN, TaN, TaSiN or TiSiN；The third work-function layer
209 material is one or more of TiAl, TiAlC, TaAlN, TiAlN, TaCN and AlN.
In the present embodiment, the material of first work-function layer 207 is TiN, and the material of second work-function layer 208 is
TiN；The material of the third work-function layer 209 is TiAl.
In the present embodiment, first work-function layer 207 with a thickness of 10 angstroms~30 angstroms；Second work-function layer 208
With a thickness of 5 angstroms~30 angstroms；The third work-function layer 209 with a thickness of 20 angstroms~70 angstroms.
The SRAM device further include: gate dielectric layer 204 and first work function positioned at the area I that pulls up transistor
Protective layer between layer 207, and the protective layer is also located at the gate dielectric layer 204 and third work content of the pull-down transistor area II
Between several layers 209.
The protective layer plays the role of protecting gate dielectric layer 204.In the present embodiment, the protective layer includes: positioned at institute
State the cap 205 on gate dielectric layer 204 and the etching stop layer 206 in the cap 205.Wherein, the lid
The material of cap layers 205 is TiN, and the material of the etching stop layer 206 is TaN.
The diffusion barrier layer 212 be also located at it is upper at the top of the second work-function layer 208 of the area I that pulls up transistor and under
On the gate dielectric layer 204 of crystal pulling area under control II.Due to having protective layer on the gate dielectric layer 204 of the pull-down transistor area II,
For this purpose, the diffusion barrier layer 212 of the pull-down transistor area II is located on the protective layer of the pull-down transistor area II.
In the present embodiment, the material of the diffusion barrier layer 212 is TiaN.In other embodiments, the diffusion barrier
The material of layer can also be TaCN.
In the present embodiment, the diffusion barrier layer 212 with a thickness of 5 angstroms~20 angstroms.The related diffusion barrier layer 212
The selection principle of thickness can refer to the respective description of previous embodiment, and details are not described herein.
In SRAM device provided by the invention, the area I and pull-down transistor area II that pulls up transistor is adjacent, and due to
First work-function layer 207 and the second work-function layer 208 are only located at the area I that pulls up transistor；Pull up transistor area I with
First work-function layer 207 of pull-down transistor area II intersection and the second work-function layer 208 and the third work-function layer 209 it
Between stopped by the diffusion barrier layer 212, the diffusion barrier layer 212 is conducive to the first work-function layer for stopping the intersection
Mutually transverse diffusion between 207 and third work-function layer 209, and be conducive to the second work-function layer 208 for stopping the intersection
The mutually transverse diffusion between the third work-function layer 209 so as to improve the electric property of SRAM device, such as improves
Electrical parameter mismatch between pull transistor and pull-down transistor.
Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (20)
1. a kind of manufacturing method of SRAM device characterized by comprising
Substrate is provided, the substrate includes adjacent pull up transistor area and pull-down transistor area；
Gate dielectric layer is formed on the part of substrate in pull up transistor area and the pull-down transistor area；
The first work-function layer is formed on the gate dielectric layer, the material of first work-function layer is p-type work function material；
Etching removes first work-function layer in the pull-down transistor area；
The second work-function layer, the material of second work-function layer are formed in remaining first work-function layer and pull-down transistor area
Material is p-type work function material；
Etching removes second work-function layer in the pull-down transistor area；
It is formed and is expanded on residue the second work-function layer side wall and remaining first work-function layer side wall in the area that pulls up transistor
Dissipate barrier layer；
Upper and pull-down transistor area grid are situated between on the diffusion barrier layer, at the top of second work-function layer in the area that pulls up transistor
Third work-function layer is formed on matter layer, the material of the third work-function layer is N-type work function material；
Gate electrode layer is formed in the third work-function layer.
2. the manufacturing method of SRAM device as described in claim 1, which is characterized in that form the diffusion using depositing operation
Barrier layer；
In the processing step for forming the diffusion barrier layer, also at the top of second work-function layer in the area that pulls up transistor on
And the diffusion barrier layer is formed on the gate dielectric layer in the pull-down transistor area；
In the processing step for forming the third work-function layer, the third work-function layer of formation is located at the upper crystal pulling
On the diffusion barrier layer in area under control and pull-down transistor area.
3. the manufacturing method of SRAM device as claimed in claim 1 or 2, which is characterized in that use atom layer deposition process shape
At the diffusion barrier layer.
4. the manufacturing method of SRAM device as claimed in claim 2, which is characterized in that the diffusion barrier layer with a thickness of 5
Angstrom~20 angstroms.
5. the manufacturing method of SRAM device as described in claim 1, which is characterized in that the material of the diffusion barrier layer is
TaN or TaCN.
6. the manufacturing method of SRAM device as described in claim 1, which is characterized in that remove the pull-down transistor in etching
After second work-function layer in area, remaining first work-function layer and remaining second work-function layer are in the area that pulls up transistor under
The side wall at the adjacent place in crystal pulling area under control flushes.
7. the manufacturing method of SRAM device as described in claim 1, which is characterized in that the material of first work-function layer is
One or more of Ta, TiN, TaN, TaSiN or TiSiN；The material of second work-function layer be Ta, TiN, TaN,
One or more of TaSiN or TiSiN；The material of the third work-function layer be TiAl, TiAlC, TaAlN, TiAlN,
One or more of TaCN and AlN.
8. the manufacturing method of SRAM device as described in claim 1, which is characterized in that after forming the gate dielectric layer,
It is formed before first work-function layer, further includes: form protective layer on the gate dielectric layer.
9. the manufacturing method of SRAM device as claimed in claim 8, which is characterized in that form the processing step of the protective layer
It include: to form cap on the gate dielectric layer；Etching stop layer, and the etching stop layer are formed in the cap
Material it is different from the material of first work-function layer.
10. the manufacturing method of SRAM device as claimed in claim 8, which is characterized in that the substrate further includes that channel grid are brilliant
Body area under control；
Part of substrate in the processing step for forming the gate dielectric layer and protective layer, also in channel gate transistor area
Upper formation gate dielectric layer and the protective layer on gate dielectric layer；
In the processing step for forming first work-function layer, the first work function also is formed in channel gate transistor area
Layer；
In the processing step for forming second work-function layer, second function is also formed in channel gate transistor area
Function layer；
In the processing step for forming the third work-function layer, the third function is also formed in channel gate transistor area
Function layer.
11. the manufacturing method of SRAM device as claimed in claim 10, which is characterized in that forming second work-function layer
Before, first work-function layer and protective layer in etching removal channel gate transistor area；Forming second work function
In the processing step of layer, the second work-function layer is formed on the gate dielectric layer in channel gate transistor area.
12. a kind of SRAM device characterized by comprising
Substrate, the substrate include adjacent pull up transistor area and pull-down transistor area；
Gate dielectric layer on the part of substrate in pull up transistor area and the pull-down transistor area；
The first work-function layer on the gate dielectric layer for pulling up transistor area and it is located in first work-function layer
The second work-function layer, the material of first work-function layer and the second work-function layer is p-type work function material；
Diffusion barrier layer on the second work-function layer side wall and the first work-function layer side wall in the area that pulls up transistor；
On the diffusion barrier layer, second work-function layer in the area that pulls up transistor top is gone up and the grid in pull-down transistor area
Third work-function layer on dielectric layer, the material of the third work-function layer are N-type work function material；
Gate electrode layer in the third work-function layer.
13. SRAM device as claimed in claim 12, which is characterized in that the diffusion barrier layer is also located at the upper crystal pulling
At the top of second work-function layer in area under control on the upper and gate dielectric layer in pull-down transistor area.
14. SRAM device as claimed in claim 13, which is characterized in that the diffusion barrier layer with a thickness of 5 angstroms~20 angstroms.
15. SRAM device as claimed in claim 12, which is characterized in that the material of the diffusion barrier layer be TaN or
TaCN。
16. SRAM device as claimed in claim 12, which is characterized in that first work-function layer and the second work-function layer
It is flushed in described pull up transistor with the side wall at adjacent place, pull-down transistor area, area.
17. SRAM device as claimed in claim 12, which is characterized in that the SRAM device further include: be located at the pull-up
Protective layer between the gate dielectric layer of transistor area and the first work-function layer, and the protective layer is also located at the pull-down transistor
Between the gate dielectric layer in area and the third work-function layer.
18. SRAM device as claimed in claim 12, which is characterized in that the substrate further includes channel gate transistor area；Its
In, the gate dielectric layer is also located on the part of substrate in channel gate transistor area；And second work-function layer is also located at
On the gate dielectric layer in channel gate transistor area；The third work-function layer is also located at the second of channel gate transistor area
In work-function layer.
19. SRAM device as claimed in claim 12, which is characterized in that the substrate include substrate and be located at the substrate
On discrete fin.
20. SRAM device as claimed in claim 19, which is characterized in that the area that pulls up transistor is with a fin；Institute
Stating pull-down transistor area tool, there are two fins.
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