CN108054256A - A kind of LED luminescence chips and processing method - Google Patents
A kind of LED luminescence chips and processing method Download PDFInfo
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- CN108054256A CN108054256A CN201711332487.3A CN201711332487A CN108054256A CN 108054256 A CN108054256 A CN 108054256A CN 201711332487 A CN201711332487 A CN 201711332487A CN 108054256 A CN108054256 A CN 108054256A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/04—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
- H01L33/06—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/14—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
- H01L33/145—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure with a current-blocking structure
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Abstract
The present invention provides a kind of LED luminescence chips and processing methods, are related to LED technology field.LED luminescence chips provided by the invention, including basal layer and luminescent layer, luminescent layer includes the N-type layer, mqw layer and the P-type layer that are stacked, wherein, insulation layer is provided in mqw layer, which has been arranged on the lower section of electrode.Since mqw layer is to be substantially carried out luminous one layer, and the substantially no electric current of insulation layer passes through, insulation layer is caused not shine substantially, so that electric current is more passed through by the conduction region (region in mqw layer in addition to insulation layer) in mqw layer, so as to enhance the luminous degree of conduction region, the light that is sent by conduction region is more difficult to be blocked (compared to insulation layer) by electrode, and then, illumination effect is improved to a certain extent.
Description
Technical field
The present invention relates to LED technology field, in particular to a kind of LED luminescence chips and processing method.
Background technology
With advances in technology, the LED luminescence chips using LED technology as core emerge in an endless stream.
Led luminescence chips, are the core component of LED lamp, that is, the P-N junction referred to.Its major function is：Electric energy is converted
For luminous energy, the main material of chip is monocrystalline silicon.Semiconductor wafer is made of two parts, and a part is P-type semiconductor, in it
Face hole is occupied an leading position, and the other end is N-type semiconductor, is mainly electronics in this side.But what both semiconductors connected
When, a P-N junction is just formed between them.When electric current acts on this chip by conducting wire, electronics will be pushed away
To P areas, in P areas then electronics will send energy, here it is the principles that LED shines with hole-recombination in the form of photon.
And the wavelength of light i.e. the color of light, it is to be determined by the material for forming P-N junction.
The content of the invention
It is an object of the invention to provide a kind of LED luminescence chips and processing methods.
In a first aspect, an embodiment of the present invention provides a kind of LED luminescence chips, including：
Basal layer, luminescent layer and the electrode being cascading, basal layer include silicon substrate, and luminescent layer includes being stacked
N-type layer, mqw layer and P-type layer；
Insulation layer is internally provided in mqw layer, insulation layer is located at the lower section of electrode.
With reference to first aspect, an embodiment of the present invention provides the first possible embodiment of first aspect, wherein,
Mqw layer is that the MQW gesture for including being stacked builds layer and MQW gesture well layers.
With reference to first aspect, an embodiment of the present invention provides second of possible embodiment of first aspect, wherein, base
Plinth layer further includes mirror surface, and mirror surface is between silicon substrate and luminescent layer.
With reference to first aspect, an embodiment of the present invention provides the third possible embodiment of first aspect, wherein, absolutely
Edge area is formed from a side surface of the luminescent layer away from basal layer to the extension of another side surface, and insulation layer at least extends to
Mqw layer.
With reference to first aspect, an embodiment of the present invention provides the 4th kind of possible embodiment of first aspect, wherein,
The upper surface of luminescent layer is provided with connecting line, one end of connecting line and contact electrode, and the other end is with conduction region away from basal layer
A side surface joint；Conduction region is the region in addition to insulation layer in luminescent layer.
With reference to first aspect, an embodiment of the present invention provides the 5th kind of possible embodiment of first aspect, wherein, absolutely
Include following one or more filled with insulating materials, insulating materials in edge area：Transparent glass glue and liquid crystal and transparent nitridation
Object；
The insulation layer is tapered or cylindric.
With reference to first aspect, an embodiment of the present invention provides the 6th kind of possible embodiment of first aspect, wherein, absolutely
Edge area includes silicon dioxide layer and liquid crystal filling area, and silicon dioxide layer is arranged between liquid crystal filling area and conduction region, so that liquid
Brilliant fill area is in contact by silicon dioxide layer with conduction region.
Second aspect, the embodiment of the present invention additionally provide a kind of processing method of LED luminescence chips, including：
Luminescent layer is grown on basal layer；Basal layer includes silicon substrate；
Luminescent layer is carried out to hollow out processing, hollows out processing at least in empty, the empty position of mqw layer to formation inside mqw layer
In the lower section of electrode position, luminescent layer includes P-type layer, mqw layer and the N-type layer that order is stacked；
The fill insulant in cavate cavity, to form insulation layer；
Electrode is set on reserved electrode position, so that electrode is in contact with the conduction region of luminescent layer, conduction region is hair
Region in photosphere in addition to insulation layer.
With reference to second aspect, an embodiment of the present invention provides the first possible embodiment of second aspect, wherein, step
Suddenly the fill insulant in cavate cavity, is included with forming insulation layer：
Silicon dioxide layer is set on the hole wall in cavity；
The filling liquid crystal in cavity, so that liquid crystal is in contact by silicon dioxide layer with conduction region, conduction region is luminescent layer
In region in addition to insulation layer.
The third aspect, the embodiment of the present invention additionally provide a kind of processing method of LED luminescence chips, which is characterized in that bag
It includes：
On basal layer by the way of photoresist reservation, the luminescent layer for including insulation layer and conduction region is sputtered；Base
Plinth layer includes silicon substrate；Luminescent layer includes the N-type layer, mqw layer and the P-type layer that are stacked；Insulation layer in mqw layer is located at reserved
Electrode position lower section；
Electrode is set on reserved electrode position, so that electrode is in contact with conduction region.
LED luminescence chips provided in an embodiment of the present invention, including basal layer and luminescent layer, luminescent layer includes what is be stacked
N-type layer, mqw layer and P-type layer, wherein, insulation layer is provided in mqw layer, which has been arranged on the lower section of electrode.Due to
Mqw layer is to be substantially carried out luminous one layer, and insulation layer substantially without electric current by, insulation layer is caused not shine substantially,
So that electric current is more by the conduction region (region in mqw layer in addition to insulation layer) in mqw layer by so as to enhance
The luminous degree of conduction region, the light that is sent by conduction region is more difficult to block (compared to insulation layer) by electrode,
And then illumination effect is improved to a certain extent.
For the above objects, features and advantages of the present invention is enable to be clearer and more comprehensible, preferred embodiment cited below particularly, and coordinate
Appended attached drawing, is described in detail below.
Description of the drawings
It in order to illustrate the technical solution of the embodiments of the present invention more clearly, below will be to needed in the embodiment attached
Figure is briefly described, it should be understood that the following drawings illustrates only certain embodiments of the present invention, therefore is not construed as pair
The restriction of scope, for those of ordinary skill in the art, without creative efforts, can also be according to this
A little attached drawings obtain other relevant attached drawings.
Fig. 1 shows the structure of the LED luminescence chips in correlation technique；
Fig. 2 shows a kind of basic structure for LED luminescence chips that the embodiment of the present invention is provided；
Fig. 3 shows a kind of the first distressed structure for LED luminescence chips that the embodiment of the present invention is provided；
Fig. 4 shows a kind of second of distressed structure of LED luminescence chips that the embodiment of the present invention is provided；
Fig. 5 shows a kind of the third distressed structure for LED luminescence chips that the embodiment of the present invention is provided；
Fig. 6 shows a kind of the 4th kind of distressed structure of LED luminescence chips that the embodiment of the present invention is provided.
Specific embodiment
Below in conjunction with attached drawing in the embodiment of the present invention, the technical solution in the embodiment of the present invention is carried out clear, complete
Ground describes, it is clear that described embodiment is only part of the embodiment of the present invention, instead of all the embodiments.Usually exist
The component of the embodiment of the present invention described and illustrated in attached drawing can configure to arrange and design with a variety of herein.Cause
This, the detailed description of the embodiment of the present invention to providing in the accompanying drawings is not intended to limit claimed invention below
Scope, but it is merely representative of the selected embodiment of the present invention.Based on the embodiment of the present invention, those skilled in the art are not doing
Go out all other embodiments obtained on the premise of creative work, belong to the scope of protection of the invention.
As shown in Figure 1, showing a kind of LED luminescence chips existing for correlation technique center, the luminescent device is from the bottom to top
What is stacked gradually is provided with silicon substrate, mirror surface and luminescent layer, wherein, luminescent layer is mainly as P-type layer (mentioned in the application
P-type layer refer both to P+Gap layers), mqw layer (multiple quantum well layer) and N-type layer formed, N-type layer upper surface is provided with electrode,
Electrode is generally arranged at the middle part of N-type layer upper surface.Wherein, mqw layer mainly builds what is be alternatively formed with MQW gesture wells by MQW gesture,
Mqw layer primarily serves luminous function.
Inventor has found that in actual use, the light that mqw layer is sent can be blocked by electrode, absorbed to a certain extent,
Which results in the luminous efficiency reductions of LED luminescence chips entirety.
For this kind of situation, this application provides a kind of improved LED luminescence chips, as shown in Fig. 2, the LED shines
Chip includes：
Basal layer, luminescent layer and the electrode being cascading, basal layer include silicon substrate, and luminescent layer includes being stacked
N-type layer, mqw layer and P-type layer；
Insulation layer is internally provided in luminescent layer, insulation layer at least gos deep into mqw layer, the insulation layer in mqw layer
Positioned at the lower section of electrode.
Wherein, mqw layer mainly builds layer by the MQW gesture being stacked and MQW gesture well layers are formed.Digging may be employed in insulation layer
Empty form is set, and be can also be when mqw layer is sputtered, is blocked using photoresist, to reserve insulation layer.Afterwards
It is continuous to can also use insulating materials and be filled in insulation layer.
When specifically used, be also provided with mirror surface in basal layer, mirror surface be located at silicon substrate and luminescent layer it
Between, to improve luminous efficiency.
Insulation layer is located at the lower section of electrode, and there are two types of meaning, the first meaning refers to that insulation layer is integrally respectively positioned on electrode
Underface (for example, insulation layer can be in the form of a column)；Second of meaning refers to that a part for insulation layer is located at the underface of electrode
(insulation layer in mqw layer is located at the underface of electrode in other words), whether which kind of meaning, it is should obtaining the result is that：Such as
Insulation layer in mqw layer is replaced with luminescent material by fruit, then the utilization rate for the light that the luminescent material is sent can be less than big portion
Divide the utilization rate of the light that conduction region (region in addition to insulation layer) is sent in mqw layer；Utilization rate herein refers to light
(a certain some light is blocked by electrode without projecting LED core the ratio of total amount of the amount of line injection LED chip with generating light
Piece).Similar, utilization rate can also be defined using other modes of equal value, for example light projects the amount and light of LED chip
The ratio for the amount blocked by electrode.
As shown in Fig. 2, if insulation layer is located at the centre of mqw layer, the light sent is easier to be blocked by electrode,
, whereas if insulation layer is located at the left and right sides of mqw layer, then its light for sending is more difficult is blocked by electrode.
Above-mentioned scheme provided herein, when LED chip works, insulation layer is not have electric current stream substantially
Cross, therefore, electric current all concentrated on conduction region (conduction region is the region in addition to insulation layer, is more primarily referred to as in mqw layer,
Region in addition to insulation layer) on, the framework in the framework and correlation technique of conduction region is basically identical, therefore the electric current of conduction region
Strengthened, so as to improve the illumination effect of conduction region.Simultaneously as electrode has been arranged on above insulation layer, and absolutely
Edge area does not shine substantially, therefore the light that is sent of luminescent layer is less is blocked and absorbed by electrode, so as to carry on the whole
The high luminous efficiency of LED chip.
In LED luminescence chips provided herein, technological core in mqw layer in setting nonconducting insulation
Area.Alternatively, it is that substitute the target area in mqw layer, (target area is referred in mqw layer, is sent using insulating materials
The light region easily being blocked, absorb by electrode), more shine so that being not easy the region blocked by electrode
(having more electric currents to pass through), the region easily blocked by electrode, which is reduced, to shine or does not shine.
In said program, insulation layer can be to be formed in mqw layer, but in some cases, for some manufacturing enterprises
For, this structure processes excessively complexity, and therefore, for the purpose for simplifying technique, insulation layer provided herein can
Such a way to be taken to set：
Insulation layer is formed from a side surface of the luminescent layer away from basal layer to the extension of another side surface, and insulation layer is extremely
Mqw layer is extended to less.
As it can be seen that in the case of this kind, insulation layer is no longer simply present in mqw layer, but (separate by the upper surface of luminescent layer
One side surface of basal layer) extend downwardly, so in processing, difficulty of processing is lower.During concrete operations, can be
It after luminescent layer integrally is grown completion, is from top to bottom etched, it is no longer necessary to individually mqw layer be carried out to hollow out place
Reason.
Under normal circumstances, the upper surface of insulation layer can be with contact electrode, can not also be with contact electrode；It can be with
It is that the lower surface of electrode is entirely fallen on the upper surface of insulation layer.The shape of insulation layer can be adjusted as needed, such as
Can be column, ellipsoid, triangle body shape, taper (as shown in fig. 6, preferably coniform, can to prolong the service life) etc..For
Simplified technique, usual insulation layer are in the form of a column.It is furthermore preferred that insulation layer is in the form of a column, and the upper surface of insulation layer is (away from base
One side surface of plinth layer) it is overlapped with the lower surface of electrode (towards a side surface of basal layer)；Either and insulation layer
Upper surface is in contact with the lower surface of electrode, and (that is, electrode can be simultaneously with conduction region upper surface joint for the lower surface of electrode
Touch conduction region and insulation layer), conduction region is the region in addition to insulation layer in luminescent layer；The lower surface of either electrode leads to
Crossing insulation layer, (i.e. electrode can not directly contact conduction region, be merely able to touch conduction by insulation layer with conduction region joint
Area).
When the lower surface of electrode is merely able to touch conduction region by insulation layer, electrode need by connecting line with
Conduction region is attached, to complete the conducting of electric current.
And then in scheme provided herein, it can also set as follows：
Connecting line, one end of connecting line and contact electrode, the other end and conduction region are provided in the upper surface of luminescent layer
A side surface joint away from basal layer；Conduction region is the region in addition to insulation layer in luminescent layer.
Herein, the main purpose for setting connecting line is to pass to electric current, i.e., so that luminescent layer generates electric connection with electrode.It is logical
It often, just can be by the way of this set connecting line only when the area of conduction region and contact electrode is less than predetermined threshold.
Such as description hereinbefore, luminescent layer includes P-type layer, mqw layer and the N-type layer that order is stacked, and insulation layer can be with
It is to prolong vertical direction, be in contact successively with P-type layer, mqw layer and N-type layer (i.e. insulation layer order has run through upper two layers, and with the
Three layers are in contact)；Can also be insulation layer be only in contact with upper two layers (such as insulation layer only penetrates N-type layer, and with mqw layer phase
Contact, and be not in contact with P-type layer).Both set insulation layers mode can, as long as ensure insulation layer can occupy
In mqw layer, the segment space immediately below electrode.
The insulating materials of high impedance in insulation layer should be set, passed through to avoid electric current by insulation layer.It needs to illustrate
, in scheme provided herein, insulating materials refers to the poor material of electric conductivity, and non-fully non-conductive.It can
Have much with the material used, but in view of many factors such as cost, effect, the insulating materials in the application is preferably transparent
Glass cement, liquid crystal and and transparent nitride.Certainly, in the case of certain, can simultaneously using these three materials any one or
Arbitrary two kinds or these three all uses.
Liquid crystal is in contact with the other materials in luminescent layer in order to prevent when liquid crystal is used, and should also set dioxy
The transparent insulating layers such as SiClx layer, silicon nitride are protected.
And then it in scheme provided herein, further includes：Insulation layer includes silicon dioxide layer and insulating materials is filled
Area, silicon dioxide layer are arranged between insulating materials fill area and conduction region, so that insulating materials fill area passes through silica
Layer is in contact with conduction region.
In the following, a kind of LED luminescence chips provided herein are illustrated with a specific structure example, LED hairs
Optical chip includes：
Silicon substrate, mirror surface and the luminescent layer set gradually from the bottom to top, is additionally provided with electrode and company on the light-emitting layer
Wiring, electrode are located at the middle part of luminescent layer upper surface；
Luminescent layer includes the insulation layer positioned at middle part and the conduction region around insulation layer setting；
Conduction region includes the P-type layer, mqw layer and the N-type layer that set gradually from the bottom to top；
Transparent glass glue is filled in insulation layer；
The upper surface of insulation layer is in contact with the lower surface of electrode, and electrode is in contact by insulation layer with conduction region, with
And electrode is in contact by connecting line with conduction region, so that electrode is electrically connected by connecting line and conduction region；
Insulation layer is located at the underface of electrode, and insulation layer passes through N-type layer and mqw layer, and the lower surface of insulation layer and P
Type layer is in contact.
For above-mentioned LED luminescence chips, present invention also provides corresponding processing methods, and there are two types of processing methods, and one
Kind is to generate the LED luminescence chips using sputtering mode, and another kind is to generate the LED luminescence chips by the way of growth.
In the following, introducing the processing method of growth first, include the following steps：
Step 101, luminescent layer is grown on basal layer；Basal layer includes silicon substrate；
Step 102, luminescent layer is carried out hollowing out processing, hollows out processing at least in empty, the mqw layer to formation inside mqw layer
Cavity be located at the lower section of electrode position, luminescent layer includes P-type layer, mqw layer and the N-type layer that order is stacked；
Step 103, the fill insulant in cavate cavity, to form insulation layer；
Step 104, electrode is set on reserved electrode position, so that electrode is in contact with the conduction region of luminescent layer, leads
Electric area is the region in addition to insulation layer in luminescent layer.
By above-mentioned steps, it can realize and in the lower section of electrode insulation layer be set (to fill insulation material in the cavity in mqw layer
The formed region of material) so that conduction region of the current convergence beside insulation layer be so as in the case where source current is constant,
The magnitude of current of conduction region is added as far as possible, also just improves illumination effect.Fill insulant, general requirement is to fill out cavity
It is flat, so that the position height in the region in cavity and the integral position of luminescent layer are highly consistent.
After step 104, can also increase roughening, annealing and etc..
Insulation layer is located at the lower section of electrode, and there are two types of meaning, the first meaning refers to that insulation layer is integrally respectively positioned on electrode
Underface (for example, insulation layer can be in the form of a column)；Second of meaning refers to that a part for insulation layer is located at the underface of electrode
(insulation layer in mqw layer is located at the underface of electrode in other words), whether which kind of meaning, it is should obtaining the result is that：Such as
Insulation layer in mqw layer is replaced with luminescent material by fruit, then the utilization rate for the light that the luminescent material is sent can be less than big portion
Divide the utilization rate of the light that conduction region (region in addition to insulation layer) is sent in mqw layer；Utilization rate herein refers to light
(a certain some light is blocked by electrode without projecting LED core the ratio of total amount of the amount of line injection LED chip with generating light
Piece).Similar, utilization rate can also be defined using other modes of equal value, for example light projects the amount and light of LED chip
The ratio for the amount blocked by electrode.
As shown in Fig. 2, if insulation layer is located at the centre of mqw layer, the light sent is easier to be blocked by electrode,
, whereas if insulation layer is located at the left and right sides of mqw layer, then its light for sending is more difficult is blocked by electrode.
The processing that hollows out in above-mentioned steps is from top to bottom hollowed out (by electrode position towards the direction of basal layer
Hollowed out), mqw layer should be at least deep by hollowing out operation, so that insulation layer occupies the space of a part of mqw layer.
Specifically, according to the difference for hollowing out depth, step 102 illustrates separately below there are two types of realization method.
The first, as shown in figure 3, showing that insulation layer has run through N-type layer, and is deep into mqw layer, meanwhile, no and P
The situation that type layer is in contact.I.e. in step 102, N-type layer has been run through in cavate cavity, and is deep into mqw layer, and not with P
Type layer is in contact.
Second, as shown in figure 4, showing that insulation layer has run through N-type layer and mqw layer, and it is deep into the feelings in P-type layer
Condition.I.e. in step 102, N-type layer and mqw layer have been run through in cavate cavity, and are deep into P-type layer.
Both above-mentioned modes are compared, and the cost of the first is lower.
Based on the above method, insulating materials is preferably transparent glass glue and liquid crystal, when insulating materials is liquid crystal, is gone back
Silicon dioxide layer should be set, to play the role of protection, and then, step 103 can perform in accordance with the following steps：
Step 1031, silicon dioxide layer is set on the hole wall in cavity；
Step 1032, the filling liquid crystal in cavity, so that liquid crystal is in contact by silicon dioxide layer with conduction region, conduction region
It is the region in luminescent layer in addition to insulation layer.
When the area of conduction region and contact electrode is less than predetermined threshold, connecting line should be also set, with connection electrode
And conduction region, and then, method provided herein further includes following steps on the basis of above-mentioned steps 101- steps 104：
Connecting line is set in the upper surface of luminescent layer, one end of connecting line and contact electrode, the other end are remote with conduction region
A side surface joint from basal layer；Conduction region is the region in addition to insulation layer in luminescent layer.
Secondly, the processing method of sputtering is introduced, is included the following steps：
Step 201, on basal layer the hair for including insulation layer and conduction region is sputtered by the way of photoresist reservation
Photosphere；Basal layer includes silicon substrate；Luminescent layer includes the N-type layer, mqw layer and the P-type layer that are stacked；Insulation layer in mqw layer
Positioned at the lower section of reserved electrode position；
Step 202, electrode is set on reserved electrode position, so that electrode is in contact with conduction region.
By above-mentioned steps, it can realize and in the lower section of electrode insulation layer be set (to fill insulation material in the cavity in mqw layer
The formed region of material) so that conduction region of the current convergence beside insulation layer be so as in the case where source current is constant,
The magnitude of current of conduction region is added as far as possible, also just improves illumination effect.Fill insulant, general requirement is to fill out cavity
It is flat, so that the position height in the region in cavity and the integral position of luminescent layer are highly consistent.
Insulation layer is located at the lower section of electrode, and there are two types of meaning, the first meaning refers to that insulation layer is integrally respectively positioned on electrode
Underface (for example, insulation layer can be in the form of a column)；Second of meaning refers to that a part for insulation layer is located at the underface of electrode
(insulation layer in mqw layer is located at the underface of electrode in other words), whether which kind of meaning, it is should obtaining the result is that：Such as
Insulation layer in mqw layer is replaced with luminescent material by fruit, then the utilization rate for the light that the luminescent material is sent can be less than big portion
Divide the utilization rate of the light that conduction region (region in addition to insulation layer) is sent in mqw layer；Utilization rate herein refers to light
(a certain some light is blocked by electrode without projecting LED core the ratio of total amount of the amount of line injection LED chip with generating light
Piece).Similar, utilization rate can also be defined using other modes of equal value, for example light projects the amount and light of LED chip
The ratio for the amount blocked by electrode.
As shown in Fig. 2, if insulation layer is located at the centre of mqw layer, the light sent is easier to be blocked by electrode,
, whereas if insulation layer is located at the left and right sides of mqw layer, then its light for sending is more difficult is blocked by electrode.
When the area of conduction region and contact electrode is less than predetermined threshold, connecting line should be also set, with connection electrode
And conduction region, and then, method provided herein further includes following steps on the basis of above-mentioned steps 201- steps 202：
Connecting line is set in the upper surface of luminescent layer, one end of connecting line and contact electrode, the other end are remote with conduction region
A side surface joint from basal layer；Conduction region is the region in addition to insulation layer in luminescent layer.
During specific implementation, there are two types of realization method, lower mask body to illustrate step 201：
The first, only sets insulation layer in mqw layer, is as follows：
Step 301, the first luminescent layer is sputtered on basal layer；
Step 302, litho pattern is set on the first luminescent layer；
Step 303, mqw layer is sputtered on the first luminescent layer；
Step 304, the region corresponding to litho pattern is peeled off, to form conduction region in mqw layer and hollow out area；
Step 305, the fill insulant in area is hollowed out, to form insulation layer；
Step 306, the second luminescent layer is sputtered on mqw layer, the first luminescent layer and the second luminescent layer are N-type layer and P respectively
Type layer；
Step 202, electrode is set in the second luminescent layer upper surface.
Second, while insulation layer is set in mqw layer and the second luminescent layer, it is as follows：
Step 401, the first luminescent layer is sputtered on basal layer；
Step 402, litho pattern is set on the first luminescent layer；
Step 403, mqw layer and the second luminescent layer are sputtered successively on the first luminescent layer, the first luminescent layer and second shine
Layer is N-type layer and P-type layer respectively；
Step 404, the region corresponding to litho pattern is peeled off, to be respectively formed conduction in mqw layer and the second luminescent layer
Area and hollow out area, the lower section for hollowing out area and being located at electrode in mqw layer；
Step 405, the fill insulant in area is hollowed out, to form insulation layer；
Step 406, electrode is set in the second luminescent layer upper surface, so that the lower surface of electrode and the conduction of the second luminescent layer
Area is in contact.
Above two mode is compared, and from the perspective of technical difficulty, the second way is more reasonable.Certainly, except elder generation
The first luminescent layer is sputtered on basal layer, and is set on the first luminescent layer outside the mode of litho pattern, it can also be directly in base
Litho pattern on plinth layer is set, and carries out sputtering work (subsequent step undertaking step 304 or the step of the first luminescent layer and mqw layer
It is rapid 404).
Step 304 and 404 upon execution, can use blue film adherency to peel off corresponding region.
As shown in figure 5, show the structure of the LED luminescence chips obtained using the first sputtering mode, it can be apparent
See only just there is insulation layer in mqw layer, be no insulation layer in N-type layer and P-type layer.In such cases, electrode can be straight
It connects and is in contact with the second motor layer, also there is no need to set connecting line.
It should be noted that there is no the content limited to be referred to foregoing LED in the processing method of LED luminescence chips
Content in the structure of chip.Also, there is no the content limited during processing LED luminescence chips using sputtering mode
It is referred to foregoing process the content during LED luminescence chips using growth pattern.
In said program, the size of insulation layer can be arbitrarily adjusted, and be not necessarily arranged to shown in attached drawing
The size and shape gone out.For example, the shape of insulation layer can be the shapes such as circle.
More than, it is only specific embodiment of the invention, but protection scope of the present invention is not limited thereto, and it is any to be familiar with
Those skilled in the art in the technical scope disclosed by the present invention, can readily occur in change or replacement, should all cover
Within protection scope of the present invention.Therefore, protection scope of the present invention should be subject to the protection scope in claims.
Claims (11)
1. a kind of LED luminescence chips, which is characterized in that including：
Basal layer, luminescent layer and the electrode being cascading, the basal layer include silicon substrate, and the luminescent layer includes being stacked
N-type layer, mqw layer and the P-type layer of setting；
Insulation layer is internally provided in the mqw layer, the insulation layer is located at the lower section of electrode.
2. LED luminescence chips according to claim 1, which is characterized in that
The MQW gesture that the mqw layer includes being stacked builds layer and MQW gesture well layers.
3. LED luminescence chips according to claim 1, which is characterized in that the basal layer further includes mirror surface, described
Mirror surface is between the silicon substrate and luminescent layer.
4. LED luminescence chips according to claim 1, which is characterized in that
The insulation layer is formed from a side surface of the luminescent layer away from basal layer to the extension of another side surface, described
Insulation layer at least extends to mqw layer.
5. LED luminescence chips according to claim 1, which is characterized in that
Connecting line, one end of the connecting line and contact electrode are provided in the upper surface of the luminescent layer, the other end is with leading
A side surface joint of the electric area away from basal layer；The conduction region is the region in addition to insulation layer in luminescent layer.
6. LED luminescence chips according to claim 1, which is characterized in that filled with insulating materials, institute in the insulation layer
Stating insulating materials includes following one or more：Transparent glass glue, liquid crystal and transparent nitride；
The insulation layer is tapered or cylindric.
7. LED luminescence chips according to claim 1, which is characterized in that insulation layer includes silicon dioxide layer and liquid crystal is filled out
Area is filled, silicon dioxide layer is arranged between liquid crystal filling area and conduction region, so that the liquid crystal filling area passes through silicon dioxide layer
It is in contact with conduction region.
8. a kind of processing method of LED luminescence chips, which is characterized in that including：
Luminescent layer is grown on basal layer；Basal layer includes silicon substrate；
Luminescent layer is carried out to hollow out processing, hollows out processing at least to formation cavity inside mqw layer, the cavity of mqw layer is located at electricity
The lower section of pole position, luminescent layer include P-type layer, mqw layer and the N-type layer that order is stacked；
The fill insulant in cavate cavity, to form insulation layer；
Electrode is set on reserved electrode position, so that electrode is in contact with the conduction region of luminescent layer, conduction region is luminescent layer
In region in addition to insulation layer.
9. the processing method of LED luminescence chips according to claim 8, which is characterized in that step is in cavate sky
Fill insulant in hole is included with forming insulation layer：
Silicon dioxide layer is set on the hole wall in cavity；
The filling liquid crystal in cavity, so that liquid crystal is in contact by silicon dioxide layer with conduction region, conduction region is removed in luminescent layer
Region beyond insulation layer.
10. a kind of processing method of LED luminescence chips, which is characterized in that including：
The first luminescent layer is sputtered on basal layer；
Litho pattern is set on the first luminescent layer；
Mqw layer is sputtered on the first luminescent layer；
The region corresponding to litho pattern is peeled off, to form conduction region in mqw layer and hollow out area；
The fill insulant in area is hollowed out, to form insulation layer；
The second luminescent layer is sputtered on mqw layer, the first luminescent layer and the second luminescent layer are N-type layer and P-type layer respectively；
Electrode is set in the second luminescent layer upper surface, so that electrode is in contact with conduction region.
11. a kind of processing method of LED luminescence chips, which is characterized in that including：
The first luminescent layer is sputtered on basal layer；
Litho pattern is set on the first luminescent layer；
Sputter mqw layer and the second luminescent layer successively on the first luminescent layer, the first luminescent layer and the second luminescent layer are N-type layer respectively
And P-type layer；
The region corresponding to litho pattern is peeled off, to be respectively formed conduction region in mqw layer and the second luminescent layer and hollow out area,
The lower section for hollowing out area and being located at electrode in mqw layer；
The fill insulant in area is hollowed out, to form insulation layer；
Electrode is set in the second luminescent layer upper surface, so that the lower surface of electrode is in contact with the conduction region of the second luminescent layer.
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| US20030122251A1 (en) * | 1995-03-13 | 2003-07-03 | Toyoda Gosei Co., Ltd. | Optical semiconductor device |
| CN101901860A (en) * | 2009-05-28 | 2010-12-01 | 夏普株式会社 | Nitride semiconductor luminescent element and manufacture method thereof |
| CN102208506A (en) * | 2010-03-30 | 2011-10-05 | 厦门乾照光电股份有限公司 | Buried high-brightness light emitting diode structure |
| CN102651437A (en) * | 2011-02-23 | 2012-08-29 | 新世纪光电股份有限公司 | Light emitting diode structure |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030122251A1 (en) * | 1995-03-13 | 2003-07-03 | Toyoda Gosei Co., Ltd. | Optical semiconductor device |
| CN101901860A (en) * | 2009-05-28 | 2010-12-01 | 夏普株式会社 | Nitride semiconductor luminescent element and manufacture method thereof |
| CN102208506A (en) * | 2010-03-30 | 2011-10-05 | 厦门乾照光电股份有限公司 | Buried high-brightness light emitting diode structure |
| CN102651437A (en) * | 2011-02-23 | 2012-08-29 | 新世纪光电股份有限公司 | Light emitting diode structure |
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