CN108054103A - Display base plate and its manufacturing method, display device - Google Patents
Display base plate and its manufacturing method, display device Download PDFInfo
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- CN108054103A CN108054103A CN201711325127.0A CN201711325127A CN108054103A CN 108054103 A CN108054103 A CN 108054103A CN 201711325127 A CN201711325127 A CN 201711325127A CN 108054103 A CN108054103 A CN 108054103A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 35
- 238000000034 method Methods 0.000 claims abstract description 149
- 239000004065 semiconductor Substances 0.000 claims abstract description 145
- 239000004020 conductor Substances 0.000 claims abstract description 141
- 238000005530 etching Methods 0.000 claims abstract description 138
- 230000008569 process Effects 0.000 claims abstract description 97
- 239000000758 substrate Substances 0.000 claims abstract description 76
- 238000009413 insulation Methods 0.000 claims abstract description 29
- 238000005516 engineering process Methods 0.000 claims abstract description 28
- 239000000463 material Substances 0.000 claims description 125
- 229910052751 metal Inorganic materials 0.000 claims description 59
- 239000002184 metal Substances 0.000 claims description 59
- 229920002120 photoresistant polymer Polymers 0.000 claims description 48
- 239000007789 gas Substances 0.000 claims description 36
- 238000001039 wet etching Methods 0.000 claims description 24
- 230000015572 biosynthetic process Effects 0.000 claims description 23
- 238000000059 patterning Methods 0.000 claims description 20
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 14
- 229910052750 molybdenum Inorganic materials 0.000 claims description 12
- 239000011733 molybdenum Substances 0.000 claims description 11
- MGRWKWACZDFZJT-UHFFFAOYSA-N molybdenum tungsten Chemical compound [Mo].[W] MGRWKWACZDFZJT-UHFFFAOYSA-N 0.000 claims description 8
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 7
- 239000011248 coating agent Substances 0.000 claims description 7
- 238000000576 coating method Methods 0.000 claims description 7
- 239000001301 oxygen Substances 0.000 claims description 7
- 229910052760 oxygen Inorganic materials 0.000 claims description 7
- SFZCNBIFKDRMGX-UHFFFAOYSA-N sulfur hexafluoride Chemical compound FS(F)(F)(F)(F)F SFZCNBIFKDRMGX-UHFFFAOYSA-N 0.000 claims description 7
- 229910052715 tantalum Inorganic materials 0.000 claims description 7
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 7
- 238000011161 development Methods 0.000 claims description 6
- 229960000909 sulfur hexafluoride Drugs 0.000 claims description 6
- 229910052782 aluminium Inorganic materials 0.000 claims description 4
- 239000004411 aluminium Substances 0.000 claims description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 4
- 230000003628 erosive effect Effects 0.000 claims description 4
- 239000001307 helium Substances 0.000 claims description 4
- 229910052734 helium Inorganic materials 0.000 claims description 4
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 claims description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 2
- 229910052737 gold Inorganic materials 0.000 claims description 2
- 239000010931 gold Substances 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 24
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- 239000007769 metal material Substances 0.000 description 5
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 4
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 4
- 229910021389 graphene Inorganic materials 0.000 description 4
- 239000004973 liquid crystal related substance Substances 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
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- 229910052733 gallium Inorganic materials 0.000 description 2
- 229910052738 indium Inorganic materials 0.000 description 2
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 2
- 239000011261 inert gas Substances 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 238000004904 shortening Methods 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- 239000011787 zinc oxide Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 206010021703 Indifference Diseases 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 208000027418 Wounds and injury Diseases 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000002305 electric material Substances 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 208000014674 injury Diseases 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
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- 238000002156 mixing Methods 0.000 description 1
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- 238000001259 photo etching Methods 0.000 description 1
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78603—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the insulating substrate or support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
Abstract
The present invention discloses a kind of display base plate and its manufacturing method, display device, belongs to display technology field.This method includes：Grid, gate insulation layer and semiconductor layer are sequentially formed on underlay substrate；Conductive material layer is formed on the underlay substrate for be formed with semiconductor layer；Conductive material layer is performed etching, obtains source-drain electrode layer, wherein, the position contacted on conductive material layer with semiconductor layer is etched by dry etch process.The present invention helps avoid influence of the etching process to the electrology characteristic of semiconductor layer.The present invention manufactures for display base plate.
Description
Technical field
The present invention relates to display technology field, more particularly to a kind of display base plate and its manufacturing method, display device.
Background technology
Display base plate is the main display unit of display device, and display base plate can be divided into etching barrier layer according to its structure
(English：Etch Stop Layer；Referred to as：ESL) structure display base plate, back of the body channel etching (English：Back Channel
Etched；Referred to as：BCE) structure display base plate and top-gated (English：Top Gate) structure display base plate.BCE structure display base plates
It is the following emphasis direction researched and developed with advantages of simple structure and simple.
BCE structures display base plate include underlay substrate and, grid, the gate insulation layer being successively set on underlay substrate
(English：Gate Insulator；Referred to as：GI), semiconductor layer and source-drain electrode metal layer etc., source-drain electrode metal layer include source electrode and
Drain electrode is formed with raceway groove between source electrode and drain electrode.BCE structures display base plate during fabrication, the shape successively first on underlay substrate
Into grid, GI and semiconductor layer, metal material layer is then formed on the underlay substrate for be formed with semiconductor layer, is carved by wet method
Etching technique performs etching metal material layer to obtain source-drain electrode metal layer.
But influenced by the etching precision of wet-etching technology, when being performed etching to metal material layer, positioned at metal
Semiconductor layer below material layers can have quarter phenomenon (that is to say that semiconductor layer is etched), and the electricity for influencing semiconductor layer is special
Property.
The content of the invention
The present invention provides a kind of display base plate and its manufacturing method, display device, can be to avoid etching process to semiconductor
The influence of the electrology characteristic of layer.Technical scheme is as follows：
In a first aspect, a kind of manufacturing method of display base plate is provided, the described method includes：
Grid, gate insulation layer and semiconductor layer are sequentially formed on underlay substrate；
Conductive material layer is formed on the underlay substrate of the semiconductor layer is formed with；
The conductive material layer is performed etching, obtains source-drain electrode layer, wherein, it is partly led with described on the conductive material layer
The position of body layer contact is etched by dry etch process.
Optionally, it is described that the conductive material layer is performed etching, source-drain electrode layer is obtained, wherein, the conductive material layer
The upper position contacted with the semiconductor layer is etched by dry etch process, including：
The conductive material layer is performed etching by dry etch process, obtains source-drain electrode layer.
Optionally, it is described that conductive material layer is formed on the underlay substrate of the semiconductor layer is formed with, including：
Conductive material layer, the default material are formed on the underlay substrate of the semiconductor layer is formed with using predetermined material
Material includes any one in metal molybdenum, metal tantalum and tungsten molybdenum.
Optionally, the conductive material layer include at least two subconductivity material layers, it is described to the conductive material layer into
Row etching, obtains source-drain electrode layer, wherein, the position contacted on the conductive material layer with the semiconductor layer passes through dry etching
Technique etches, including：
By wet-etching technology to the subconductivity material layers that in the conductive material layer, are not contacted with the semiconductor layer
It performs etching；
By dry etch process to the subconductivity material layers that in the conductive material layer, are contacted with the semiconductor layer into
Row etching, obtains source-drain electrode layer.
Optionally, it is described that conductive material layer is formed on the underlay substrate of the semiconductor layer is formed with, including：
Conductive material layer is formed on the underlay substrate of the semiconductor layer is formed with, the conductive material layer is included at least
Two sub- conductive material layers, the subconductivity material layers contacted with the semiconductor layer in at least two subconductivity material layers
Formation material is predetermined material, and the predetermined material includes any one in metal molybdenum, metal tantalum and tungsten molybdenum.
Optionally, the conductive material layer include three sub- conductive material layers, three sub- conductive material layers according to by
The nearly semiconductor layer is followed successively by metal molybdenum, metallic aluminium and metal molybdenum to the formation material away from the semiconductor layer.
Optionally, the etching gas of the dry etch process are the mixed gas of sulfur fluoride gas and oxygen；Alternatively, institute
The etching gas for stating dry etch process are the mixed gas of sulfur fluoride gas, oxygen and helium.
Optionally, it is described that the conductive material layer is performed etching, source-drain electrode layer is obtained, including：
The conductive material layer is handled by patterning processes, obtains source-drain electrode layer, the patterning processes include light
Photoresist coating, exposure, development, etching and photoresist lift off.
Second aspect provides what a kind of method using described in any optional mode of first aspect or first aspect manufactured
Display base plate, the display base plate include：Underlay substrate and, grid, the gate insulation being successively set on the underlay substrate
Layer, semiconductor layer and source-drain electrode layer.
The third aspect, provides a kind of display device, and the display device includes the display base plate described in second aspect.
The advantageous effect that technical solution provided by the invention is brought is：
Display base plate provided by the invention and its manufacturing method, display device, this method include：On underlay substrate successively
Form grid, gate insulation layer and semiconductor layer；Conductive material layer is formed on the underlay substrate for be formed with semiconductor layer；To conduction
Material layers perform etching, and obtain source-drain electrode layer, wherein, the position contacted on conductive material layer with semiconductor layer passes through dry etching
Technique etches.Since the position contacted on conductive material layer with semiconductor layer is etched by dry etch process, and dry etching
The etching precision of technique is easier to control, and dry etch process can not perform etching semiconductor layer, therefore can be to avoid quarter
Influence of the erosion process to the electrology characteristic of semiconductor layer.
It should be appreciated that above general description and following detailed description is only exemplary, this can not be limited
Invention.
Description of the drawings
To describe the technical solutions in the embodiments of the present invention more clearly, make required in being described below to embodiment
Attached drawing is briefly described, it should be apparent that, the accompanying drawings in the following description is only some embodiments of the present invention, for
For those of ordinary skill in the art, without creative efforts, other are can also be obtained according to these attached drawings
Attached drawing.
Fig. 1 is a kind of structure diagram for display base plate that correlation technique provides；
Fig. 2 is a kind of method flow diagram of the manufacturing method of display base plate provided in an embodiment of the present invention；
Fig. 3 is the method flow diagram of the manufacturing method of another display base plate provided in an embodiment of the present invention；
Fig. 4 is a kind of schematic diagram on underlay substrate after formation grid provided in an embodiment of the present invention；
Fig. 5 is a kind of showing after formation gate insulation layer on the underlay substrate for be formed with grid provided in an embodiment of the present invention
It is intended to；
Fig. 6 be it is provided in an embodiment of the present invention it is a kind of on the underlay substrate for be formed with gate insulation layer formed semiconductor layer after
Schematic diagram；
Fig. 7 is a kind of formation conducting medium layer on the underlay substrate for be formed with semiconductor layer provided in an embodiment of the present invention
Schematic diagram afterwards；
Fig. 8 be it is provided in an embodiment of the present invention it is a kind of be formed on the underlay substrate of conducting medium layer formed photoresist layer after
Schematic diagram；
Fig. 9 be it is provided in an embodiment of the present invention it is a kind of photoresist layer is exposed and developed after schematic diagram；
Figure 10 be it is provided in an embodiment of the present invention it is a kind of conducting medium layer is performed etching after schematic diagram；
Figure 11 is the schematic diagram after a kind of stripping photoresist provided in an embodiment of the present invention；
Figure 12 is the method flow diagram of the manufacturing method of another display base plate provided in an embodiment of the present invention；
Figure 13 is provided in an embodiment of the present invention a kind of conducting medium to be formed on the underlay substrate for be formed with semiconductor layer
Schematic diagram after layer；
Figure 14 is that a kind of be formed on the underlay substrate of conducting medium layer provided in an embodiment of the present invention forms photoresist layer
Schematic diagram afterwards；
Figure 15 be it is provided in an embodiment of the present invention it is a kind of photoresist layer is exposed and developed after schematic diagram；
Figure 16 is that a kind of subconductivity dielectric layer to not contacted with semiconductor layer provided in an embodiment of the present invention performs etching
Schematic diagram afterwards；
Figure 17 is after a kind of pair provided in an embodiment of the present invention subconductivity dielectric layer contacted with semiconductor layer performs etching
Schematic diagram；
Figure 18 is the schematic diagram after a kind of stripping photoresist provided in an embodiment of the present invention.
Attached drawing herein is merged in specification and forms the part of this specification, shows the implementation for meeting the present invention
Example, and the principle for explaining the present invention together with specification.
Specific embodiment
In order to make the object, technical solutions and advantages of the present invention clearer, the present invention is made below in conjunction with attached drawing into
It is described in detail to one step, it is clear that described embodiment is only the implementation of part of the embodiment of the present invention rather than whole
Example.Based on the embodiments of the present invention, those of ordinary skill in the art are obtained without making creative work
All other embodiment, belongs to the scope of protection of the invention.
With the progress of display product manufacture, new display technology gradually substitutes old-fashioned tft liquid crystal to show
Show device (English：Thin Film Transistor Liquid Crystal Display；Referred to as：TFT LCD) technology, for example,
Organic Light Emitting Diode (English：Organic Light-Emitting Diode；Referred to as：OLED) product small size field by
Gradually substitute liquid crystal display product.Main display unit of the display base plate as display product can be divided into ESL knots according to structure
Structure display base plate, BCE structures display base plate and top gate structure display base plate.Compared with ESL structure display base plates, BCE structures are shown
Show that the structural manufacturing process of substrate is more simple, be the emphasis direction of following research and development.It please refers to Fig.1, it illustrates correlation technique offers
A kind of display base plate 00 structure diagram, which can be BCE structure display base plates.Referring to Fig. 1, base is shown
Plate 00 includes underlay substrate 001 and the grid 002, gate insulation layer 003, the semiconductor layer that are successively set on underlay substrate 001
004 and source-drain electrode metal layer 005, source-drain electrode metal layer 005 includes source electrode 0051 and drain electrode 0052, source electrode 0051 and drain electrode 0052
Between be formed with raceway groove (not marked in Fig. 1).The display base plate 00 during fabrication, sequentially forms on underlay substrate 001 first
Then grid 002, gate insulation layer 003 and semiconductor layer 004 form gold on the underlay substrate 001 for be formed with semiconductor layer 004
Belong to material layers, metal material layer is performed etching by wet-etching technology to obtain source-drain electrode metal layer 005.But due to wet
The etching precision of method etching technics is more difficult to control, when being performed etching by wet-etching technology to metal material layer, such as Fig. 1 institutes
Show, crossing for semiconductor layer 004 can be caused to carve, the homogeneity for causing 004 remainder of semiconductor layer is poor, influences semiconductor layer
004 electrology characteristic, the manufacture difficulty of display base plate is larger, is unfavorable for the volume production of display base plate.
It, can be to avoid etching process to semiconductor layer an embodiment of the present invention provides a kind of manufacturing method of display base plate
The influence of electrology characteristic reduces the manufacture difficulty of display base plate, is conducive to the volume production of display base plate, provided in an embodiment of the present invention
The manufacturing method of display base plate refer to following each embodiments.
It please refers to Fig.2, it illustrates a kind of method flows of the manufacturing method of display base plate provided in an embodiment of the present invention
Figure, referring to Fig. 2, this method includes：
Step 201 sequentially forms grid, gate insulation layer and semiconductor layer on underlay substrate.
Step 202 forms conductive material layer on the underlay substrate for be formed with semiconductor layer.
Step 203 performs etching conductive material layer, obtains source-drain electrode layer, wherein, on conductive material layer and semiconductor layer
The position of contact is etched by dry etch process.
In conclusion the manufacturing method of display base plate provided in an embodiment of the present invention, due on conductive material layer with partly leading
The position of body layer contact is etched by dry etch process, and the etching precision of dry etch process is easier to control, and dry method
Etching technics can not perform etching semiconductor layer, therefore can be to avoid etching process to the shadow of the electrology characteristic of semiconductor layer
It rings.
In a kind of possible realization method, step 203 can include：By dry etch process to conductive material layer into
Row etching, obtains source-drain electrode layer.
Step 202 can include：Conductive material is formed on the underlay substrate for be formed with semiconductor layer using predetermined material
Layer, predetermined material include any one in metal molybdenum, metal tantalum and tungsten molybdenum.
In alternatively possible realization method, conductive material layer includes at least two subconductivity material layers, and step 203 can
To include：
The subconductivity material layers in conductive material layer, not contacted with semiconductor layer are carved by wet-etching technology
Erosion；
The subconductivity material layers in conductive material layer, contacted with semiconductor layer are performed etching by dry etch process,
Obtain source-drain electrode layer.
Step 202 can include：Conductive material layer, conductive material layer are formed on the underlay substrate for be formed with semiconductor layer
Including at least two subconductivity material layers, the subconductivity material layers that are contacted at least two subconductivity material layers with semiconductor layer
Formation material is predetermined material, and predetermined material includes any one in metal molybdenum, metal tantalum and tungsten molybdenum.
Optionally, conductive material layer includes three sub- conductive material layers, and three sub- conductive material layers are according to close to semiconductor
Layer is followed successively by metal molybdenum, metallic aluminium and metal molybdenum to the formation material away from semiconductor layer.
Optionally, the etching gas of dry etch process are the mixed gas of sulfur fluoride gas and oxygen；Alternatively,
The etching gas of dry etch process are the mixed gas of sulfur fluoride gas, oxygen and helium.
Optionally, step 203 can include：Conductive material layer is handled by patterning processes, obtains source-drain electrode layer,
Patterning processes include photoresist coating, exposure, development, etching and photoresist lift off.
The alternative embodiment that any combination forms the present invention may be employed, herein no longer in above-mentioned all optional technical solutions
It repeats one by one.
In conclusion the manufacturing method of display base plate provided in an embodiment of the present invention, due on conductive material layer with partly leading
The position of body layer contact is etched by dry etch process, and the etching precision of dry etch process is easier to control, and dry method
Etching technics can not perform etching semiconductor layer, therefore can be to avoid etching process to the shadow of the electrology characteristic of semiconductor layer
It rings.
It please refers to Fig.3, it illustrates the method streams of the manufacturing method of another display base plate provided in an embodiment of the present invention
Cheng Tu, referring to Fig. 3, this method includes：
Step 301 forms grid on underlay substrate.
It please refers to Fig.4, after forming grid 012 on underlay substrate 011 it illustrates one kind provided in an embodiment of the present invention
Schematic diagram.Wherein, underlay substrate 011 can be transparent substrate, can be specifically using glass, quartz or transparent resin etc.
Substrate made of leaded light and nonmetallic materials with certain robustness.Metal molybdenum (Mo), metallic copper may be employed in grid 012
(Cu), metallic aluminium (Al) and its alloy material are formed, and the thickness of grid 012 can be set according to actual conditions, for example, according to grid
The formation material of pole 012 and the resistance of grid 012 need to set the thickness of grid 012, and the embodiment of the present invention does not limit this
It is fixed.
Illustratively, exemplified by forming grid 012 using metal Mo.Increased using magnetron sputtering, thermal evaporation or plasma
Extensive chemical vapour deposition process (Plasma Enhanced Chemical Vapor Deposition；Referred to as：PECVD) the methods of
One layer of certain thickness metal Mo is deposited on underlay substrate 011, metal Mo material layers is obtained, then passes through a patterning processes
Metal Mo material layers are handled to obtain grid 012.Wherein, a patterning processes include：Photoresist coating, exposure, development,
Therefore etching and photoresist lift off, are handled to obtain grid 012 and can wrapped by a patterning processes to metal Mo material layers
It includes：One layer of photoresist is coated in metal Mo material layers and forms photoresist layer, photoresist layer is exposed using mask plate, is made
It obtains photoresist layer and forms complete exposure region and non-exposed area, handled afterwards using developing process, make the photoresist of complete exposure region
It is completely removed, the photoresist of non-exposed area all retains, by etching technics to complete exposure region pair in metal Mo material layers
The region answered performs etching, afterwards the photoresist of stripping non-exposed area, the corresponding region shape in non-exposed area in metal Mo material layers
Into grid 012.It should be noted that the embodiment of the present invention is illustrated exemplified by forming grid 012 using positive photoresist
, in practical application, negative photoresist can also be used to form grid 012, details are not described herein for the embodiment of the present invention.
Step 302 forms gate insulation layer on the underlay substrate for be formed with grid.
Fig. 5 is refer to, a kind of the underlay substrate 011 of grid 012 is being formed with it illustrates provided in an embodiment of the present invention
The upper schematic diagram formed after gate insulation layer 013.Wherein, SiO may be employed in gate insulation layer 0132(Chinese：Silica), SiNx
(Chinese：Silicon nitride) or the insulating materials such as resin formed, the thickness of gate insulation layer 013 can be set according to actual conditions,
For example, the thickness of setting gate insulation layer 013 is needed according to the resistance of the formation material of gate insulation layer 013 and gate insulation layer 013,
The embodiment of the present invention is not construed as limiting this.
Illustratively, to use SiNxIt is formed exemplified by gate insulation layer 013.The lining of grid 012 is being formed with using pecvd process
One layer of certain thickness SiN is deposited on substrate 011x, obtain SiNxMaterial layers, then to SiNxMaterial layers carry out baking processing
Form gate insulation layer 013.It should be noted that in practical application, when gate insulation layer 013 includes figure, structure can also be passed through
Figure technique is to SiNxMaterial layers form gate insulation layer 013 after being handled, and it is not limited in the embodiment of the present invention.
Step 303 forms semiconductor layer on the underlay substrate for be formed with gate insulation layer.
Fig. 6 is refer to, a kind of the underlay substrate of gate insulation layer 013 is being formed with it illustrates provided in an embodiment of the present invention
The schematic diagram after semiconductor layer 014 is formed on 011.Indium gallium zinc oxide (English may be employed in the semiconductor layer 014：indium
gallium zinc oxide；Referred to as：) etc. IGZO transparent amorphous oxides are formed, and the thickness of the semiconductor layer 014 can root
It is set according to actual conditions, the embodiment of the present invention is not construed as limiting this.
Illustratively, exemplified by forming semiconductor layer 014 using IGZO.Using the side such as magnetron sputtering, thermal evaporation or PECVD
Method deposits one layer of certain thickness IGZO on the underlay substrate 011 for be formed with gate insulation layer 013 and obtains IGZO material layers, then
IGZO material layers are handled by a patterning processes to obtain semiconductor layer 014.Wherein, a patterning processes pair are passed through
The process that IGZO material layers are handled is similar with the process handled by a patterning processes metal Mo material layers, this
Details are not described herein for inventive embodiments.It should be understood that being limited by the formation material of semiconductor layer 014, passing through
Patterning processes in the process of processing, usually carry out IGZO material layers by wet-etching technology IGZO material layers
Etching.
Step 304 forms conductive material layer on the underlay substrate for be formed with semiconductor layer.
Fig. 7 is refer to, a kind of the underlay substrate of semiconductor layer 014 is being formed with it illustrates provided in an embodiment of the present invention
The schematic diagram after conductive material layer Y is formed on 011.Wherein it is possible to the substrate of semiconductor layer 014 is being formed with using predetermined material
Conductive material layer Y is formed on substrate 011, which can include metal molybdenum (Mo), metal tantalum (Ta) and tungsten molybdenum (MoW)
In any one, certainly, in addition, predetermined material can also be the conductive materials such as graphene.It that is to say, of the invention real
It applies in example, the formation material of conductive material layer Y can be any one in metal Mo, metal Ta, MoW and graphene.At this
In inventive embodiments, the thickness of conductive material layer Y can be according to the resistance for forming material and source-drain electrode layer of conductive material layer Y
It needs to be determined that.Since the resistivity of different materials is different, for the resistance demand of source-drain electrode layer, led using what different materials were formed
The thickness of electric material layers Y is typically different.Optionally, when forming conductive material layer Y using metal Mo, conductive material layer Y's
The value range of thickness can be~extremely(angstrom), when using metal Ta conductive material layer Y, conductive material
The value range of the thickness of layer Y can be 3um~4um (micron), and the embodiment of the present invention is not construed as limiting this.
Illustratively, exemplified by forming conductive material layer Y using metal Mo.Using magnetron sputtering, thermal evaporation or PECVD etc.
Method deposits a layer thickness on the underlay substrate 011 for be formed with semiconductor layer 014 and exists~extremelyBetween
Metal Mo, obtains metal Mo material layers, and metal Mo material layers are conductive material layer Y.
Step 305 performs etching conductive material layer, obtains source-drain electrode layer, wherein, on conductive material layer and semiconductor layer
The position of contact is etched by dry etch process.
In the embodiment of the present invention, in order to avoid wet-etching technology caused quarter to semiconductor layer 014, can directly it pass through
Dry etch process performs etching to obtain source-drain electrode layer to conductive material layer Y；Alternatively, in order to improve etch rate, shorten etching
Duration and wet-etching technology is avoided to cause quarter to semiconductor layer 014, wet-etching technology can be first passed through to conductive material
Layer Y it is upper with semiconductor layer 014 not in contact with position perform etching, but do not carve the conductive material layer Y and then by doing
Method etching technics performs etching the position contacted on conductive material layer Y with semiconductor layer 014, and carves conductive material layer Y thoroughly
Obtain source-drain electrode layer.
It is alternatively possible to obtain source-drain electrode layer to conductive material layer Y processing by patterning processes, patterning processes include
Photoresist coating, exposure, development, etching and photoresist lift off.Fig. 8 to Figure 11 is that one kind provided in an embodiment of the present invention passes through structure
Figure technique obtains the schematic diagram of source-drain electrode layer 015 to conductive material layer Y processing.By patterning processes to conductive material layer
Y in the process of processing, first, as shown in figure 8, on conductive material layer Y coat one layer have certain thickness photoresist
Photoresist layer P is obtained, afterwards, photoresist layer P is exposed using mask plate so that photoresist layer p-shaped is into complete exposure region
And non-exposed area, it is handled afterwards using developing process, is completely removed the photoresist of complete exposure region, the photoetching of non-exposed area
Glue all retains, and obtains structure as shown in Figure 9, and then, complete exposure region on conductive material layer Y is corresponded to by etching technics
Region perform etching, obtain structure as shown in Figure 10, finally, remove non-exposed area photoresist obtain it is as shown in figure 11
Structure.Referring to Figure 11, source-drain electrode layer 015 includes source electrode 0151 and drain electrode 0152, is formed between source electrode 0151 and drain electrode 0152
Raceway groove, and on the semiconductor layer 014 of the lower section of source-drain electrode layer 015 each position thickness it is equal, be not present on semiconductor layer 014
Phenomenon is carved, the conductive characteristic indifference of each position on semiconductor layer 014.It should be noted that the knot shown in Figure 10 and Figure 11
What structure was merely exemplary, in practical application, between source electrode 0151 and semiconductor layer 014 and drain electrode 0152 and semiconductor layer
There may be inclination angle (Taper) between 014.In addition, the embodiment of the present invention is to form source-drain electrode layer using positive photoresist
It is illustrated exemplified by 015, in practical application, negative photoresist can also be used to form source-drain electrode layer 015, the embodiment of the present invention
Details are not described herein.
It should be noted that the complete corresponding region of exposure region on conductive material layer Y is being carried out by etching technics
It, can be direct in order to avoid wet-etching technology caused quarter to semiconductor layer 014 during structure as shown in Figure 10
The corresponding region of complete exposure region on conductive material layer Y is performed etching by dry etch process, and carves conductive material layer
Y obtains structure as shown in Figure 10；Alternatively, in order to improve etch rate, shortening etching duration and avoid wet-etching technology pair
Semiconductor layer 014 caused quarter, can first pass through wet-etching technology to the corresponding region of complete exposure region on conductive material layer Y
It performs etching, but does not carve the conductive material layer Y and then continued by dry etch process on conductive material layer Y,
The part that wet-etching technology is not carved performs etching, and carves conductive material layer Y thoroughly, obtains structure as shown in Figure 10.
In the embodiment of the present invention, the etching gas of dry etch process can be sulfur fluoride (SF6) gas and oxygen (O2)
Mixed gas；Alternatively, the etching gas of dry etch process can be SF6Gas, O2With the mixed gas of helium (He).One side
Face, the etching gas of dry etch process can be chemically reacted with the formation material of conductive material layer Y, but not with partly leading
The formation material of body layer 014 chemically reacts, therefore, what is performed etching by dry etch process to conductive material layer Y
In the process, there is no quarter phenomenon is crossed on semiconductor layer 014, etching process will not injure semiconductor layer 014, avoid etching process
Influence to the electrology characteristic of semiconductor layer 014；On the other hand, the etching precision of dry etch process is higher, and etches equal
One property is preferable, can improve the homogeneity of etching.Wherein, SF6For the main etching gas of conductive material layer Y, it is mainly used for
Chemical reaction occurs so as to be performed etching to conductive material layer Y with the formation material of conductive material layer Y, O2It is mainly used for non-exposure
Photoresist in light area close to complete exposure region is ashed, after etching completion, source electrode 0151 and semiconductor layer 014
Between and drain electrode 0152 and semiconductor layer 014 between form inclination angle, He is mainly used for making SF as inert gas6And O2's
It is uniformly mixed.
After obtaining source-drain electrode layer 015, display base plate has just been obtained.In embodiments of the present invention, display base plate can be battle array
Row substrate, or oled display substrate, and display base plate can also include other structures, for example, display base plate can be with
Including being located at the barrier layer between semiconductor layer 014 and source-drain electrode layer 015, passivation layer and position on source-drain electrode layer 015
In pixel electrode on passivation layer etc., details are not described herein for the embodiment of the present invention.
In conclusion the manufacturing method of display base plate provided in an embodiment of the present invention, due on conductive material layer with partly leading
The position of body layer contact is etched by dry etch process, and the etching precision of dry etch process is easier to control, and dry method
Etching technics can not perform etching semiconductor layer, therefore can be to avoid etching process to the shadow of the electrology characteristic of semiconductor layer
It rings.The manufacturing method of display base plate provided in an embodiment of the present invention can be good at solving the manufacture of BCE structure display base plates
Cheng Zhong, the problem of using wet-etching technology etching conductive material layers semiconductor layer being caused to spend quarter are BCE structure display base plates
Manufacture provides scheme.
2 are please referred to Fig.1, it illustrates the method streams of the manufacturing method of another display base plate provided in an embodiment of the present invention
Cheng Tu, referring to Figure 12, this method includes：
Step 1201 forms grid on underlay substrate.
Step 1202 forms gate insulation layer on the underlay substrate for be formed with grid.
Step 1203 forms semiconductor layer on the underlay substrate for be formed with gate insulation layer.
The realization process of above-mentioned steps 1201 to step 1203 may be referred to step 301 in embodiment illustrated in fig. 3 to step
Rapid 303, details are not described herein for the present embodiment.
Step 1204 forms conductive material layer on the underlay substrate for be formed with semiconductor layer, and conductive material layer is included extremely
Few two sub- conductive material layers.
In the embodiment of the present invention, conductive material layer can be formed on the underlay substrate 011 for be formed with semiconductor layer 014,
Conductive material layer includes at least two subconductivity material layers, is contacted in at least two subconductivity material layers with semiconductor layer 014
The formation materials of subconductivity material layers can be predetermined material, which can include metal Mo, in metal Ta and MoW
Any one.Certainly, in addition, predetermined material can also be the conductive materials such as graphene.It that is to say, in the present embodiment
In, the formation material of the subconductivity material layers contacted with semiconductor layer 014 can be in metal Mo, metal Ta, MoW and graphene
Any one, the thickness of each subconductivity material layers can be according to the formation material of the subconductivity material layers and source-drain electrode layer
Resistance it needs to be determined that, and for the resistance needs for ensureing source-drain electrode layer, the subconductivity material layers contacted with semiconductor layer 014
Thickness is usually larger.
The embodiment of the present invention is by taking conductive material layer includes three sub- conductive material layers as an example.3 are please referred to Fig.1, it illustrates
A kind of showing after formation conductive material layer Y on the underlay substrate 011 for be formed with semiconductor layer 014 provided in an embodiment of the present invention
Be intended to, referring to Figure 13, conductive material layer Y include subconductivity material layers Y1, subconductivity material layers Y2 and subconductivity material layers Y3 this
Three sub- conductive material layers, in this three sub- conductive material layers, subconductivity material layers Y1 is contacted with semiconductor layer 014, therefore, should
Subconductivity material layers Y1's forms material as any one in metal Mo, metal Ta and MoW, the thickness of each subconductivity material layers
Degree can according to the resistance for forming material and source-drain electrode layer of the subconductivity material layers it needs to be determined that.Optionally, the present invention is real
Example is applied to form subconductivity material layers Y1 using metal Mo, subconductivity material layers Y2 is formed using metal Al, using metal Mo shapes
Into exemplified by subconductivity material layers Y3, then the value range of the thickness of subconductivity material layers Y1 can beSon
The value range of the thickness of conductive material layer Y2 can beThe value model of the thickness of subconductivity material layers Y3
Enclosing to be
Illustratively, conductive material layer Y being formed on the underlay substrate 011 for be formed with semiconductor layer 014 can include：It is first
First, using depositing one on the underlay substrate 011 for being formed with semiconductor layer 014 the methods of magnetron sputtering, thermal evaporation or PECVD
Layer thickness existsMetal Mo, obtain metal Mo material layers, metal Mo material layers are subconductivity material
Layer Y1；Then, it is being formed with the underlay substrate 011 of metal Mo material layers using the methods of magnetron sputtering, thermal evaporation or PECVD
Upper deposition a layer thickness existsMetal Al, obtain metal Al material layers, metal Al material layers are son
Conductive material layer Y2；Finally, it is being formed with the lining of metal Al material layers using the methods of magnetron sputtering, thermal evaporation or PECVD
A layer thickness is deposited on substrate 011 to existMetal Mo, obtain metal Mo material layers, metal Mo materials
Layer is subconductivity material layers Y3, so far, obtains conductive material layer Y as shown in fig. 13 that.
Step 1205 performs etching conductive material layer, obtains source-drain electrode layer, wherein, on conductive material layer and semiconductor
The position of layer contact is etched by dry etch process.
In the embodiment of the present invention, in order to avoid wet-etching technology caused quarter to semiconductor layer 014, can directly it pass through
Dry etch process performs etching conductive material layer to obtain source-drain electrode layer；Alternatively, in order to improve etch rate, when shortening etching
It grows and wet-etching technology is avoided to cause quarter to semiconductor layer 014, wet-etching technology can be first passed through to conductive material layer
In, the subconductivity material layers not contacted with semiconductor layer 014 perform etching, then by dry etch process to conductive material layer
In, the subconductivity material layers contacted with semiconductor layer 014 perform etching, and obtain source-drain electrode layer.Wherein, connect with semiconductor layer 014
The thickness of tactile subconductivity material layers is usually larger, and the etch rate of wet-etching technology is usually larger, therefore, in order to shorten
The etching duration of conductive material layer, can during the subconductivity material layers to not contacted with semiconductor layer 014 perform etching
Quarter was carried out with pair subconductivity material layers contacted with semiconductor layer 014.It, can be by the way that wet method be controlled to carve in the embodiment of the present invention
The etching duration of etching technique, to be performed etching to the subconductivity material layers not contacted with semiconductor layer 014, and pair and semiconductor layer
The subconductivity material layers of 014 contact carried out quarter.In embodiments of the present invention, the material of group conductive material layer, thickness and
After the etching liquid of wet-etching technology determines, the etching duration of wet-etching technology determines therewith, group conductive material layer
After the etching gas of material, thickness and dry etch process determine, the etching duration of dry etch process determines therewith.Its
In, the etch rate of dry etch process can be determined by etching power, the flow for etching voltage and etching gas etc..
It is alternatively possible to be handled conductive material layer to obtain source-drain electrode layer by patterning processes, patterning processes include
Photoresist coating, exposure, development, etching and photoresist lift off.Figure 14 to Figure 18 is that one kind provided in an embodiment of the present invention passes through
Patterning processes obtain conductive material layer Y processing the schematic diagram of source-drain electrode layer 015, and the present embodiment is to first pass through wet etching
Technique is in conductive material layer Y, the subconductivity material layers not contacted with semiconductor layer 014 perform etching, then pass through dry etching
Technique illustrates exemplified by being performed etching to the subconductivity material layers in conductive material layer Y, contacted with semiconductor layer 014.Logical
Patterning processes are crossed to conductive material layer Y in the process of processing, first, as shown in figure 14, (that is to say in conductive material layer Y
In subconductivity material layers Y3) on coating one layer have certain thickness photoresist obtain photoresist layer P, afterwards, using mask plate
Photoresist layer P is exposed so that photoresist layer p-shaped into complete exposure region and non-exposed area, afterwards using developing process at
Reason, is completely removed the photoresist of complete exposure region, and the photoresist of non-exposed area all retains, and obtains knot as shown in figure 15
Structure then, successively corresponds to complete exposure region on sub- conductive material layer Y3 and subconductivity material layers Y2 by wet-etching technology
Region perform etching, structure as shown in figure 16 is obtained, afterwards, by dry etch process to complete on sub- conductive material layer Y1
The complete corresponding region of exposure region performs etching, and obtains structure as shown in figure 17, finally, the photoresist for removing non-exposed area obtains
Structure as shown in figure 18.Referring to Figure 18, source-drain electrode layer 015 includes source electrode 0151 and drain electrode 0152, source electrode 0151 and drain electrode
It is formed with raceway groove between 0152, source electrode 0151 and drain electrode 0152 are three-decker, and the semiconductor layer of 015 lower section of source-drain electrode layer
Quarter phenomenon was not present on 014.It should be noted that the structure shown in Figure 17 and Figure 18 was merely exemplary, practical application
In, there may be inclination angle between source electrode 0151 and semiconductor layer 014 and between drain electrode 0152 and semiconductor layer 014.This
Outside, the embodiment of the present invention is illustrated exemplified by forming source-drain electrode layer 015 using positive photoresist, in practical application, also
Negative photoresist may be employed and form source-drain electrode layer 015, details are not described herein for the embodiment of the present invention.
In the embodiment of the present invention, the etching gas of dry etch process can be SF6Gas and O2Mixed gas；Alternatively,
The etching gas of dry etch process can be SF6Gas, O2With the mixed gas of He.On the one hand, the etching of dry etch process
Gas can be chemically reacted with the formation material of subconductivity material layers Y1, but not with the formation material of semiconductor layer 014
It chemically reacts, therefore, during being performed etching by dry etch process to sub- conductive material layer Y1, semiconductor layer
There is no quarter phenomenon is crossed on 014, etching process will not injure semiconductor layer 014, avoid etching process to semiconductor layer 014
The influence of electrology characteristic；On the other hand, the etching precision of dry etch process is higher, and the homogeneity etched is preferable, Ke Yiti
The homogeneity of high etching.Wherein, SF6For the main etching gas of subconductivity material layers Y1, it is mainly used for and subconductivity material
Chemical reaction occurs for the formation material of layer Y1 so as to be performed etching to sub- conductive material layer Y1, O2It is mainly used for on non-exposed area
Photoresist close to complete exposure region is ashed, after etching completion, between source electrode 0151 and semiconductor layer 014,
And inclination angle is formed between drain electrode 0152 and semiconductor layer 014, He is mainly used for making SF as inert gas6And O2Mixing it is equal
It is even.
In the embodiment of the present invention, the selectivity of material performs etching conductive material layer using dry etch process, keeps away
Exempt from injury of the etching process to semiconductor layer 014, further, since the etching precision of dry etch process is higher, quarter can be improved
The homogeneity of erosion, and the etching that dry etching is vertical mode, therefore, can be by critical dimension (English：Critical
Dimension；Referred to as：CD) Bais errors are in minimum scope, wherein, the etching of vertical mode is referred to from perpendicular to treating
The direction of etching film surface performs etching, and CD Bais refer to that the width of the complete exposure area of photoresist layer (that is to say photoresist
Layer non-exposed areas between spacing) with etching formed raceway groove width (that is to say source electrode and drain between spacing) it
Difference.Wherein, in order to avoid the influence to the characteristic of semiconductor layer 014 during dry etching, during etching, Ke Yishi
When reducing etching voltage to weaken the bombardment intensity of etching gas, exhaust gas replacement frequency during dry etching can also be increased,
Pollution of the etching reactant to semiconductor layer is avoided, in addition it is also possible to by subsequent technique (for example, CVD techniques or lehr attendant
Skill) Temperature Treatment, semiconductor layer 014 is improved.
After obtaining source-drain electrode layer 015, display base plate has just been obtained.In embodiments of the present invention, which can be
Array substrate, or oled display substrate, and display base plate can also include other structures, for example, display base plate may be used also
To include the barrier layer between semiconductor layer 014 and source-drain electrode layer 015, passivation layer on source-drain electrode layer 015 and
Pixel electrode on passivation layer etc., details are not described herein for the embodiment of the present invention.
In conclusion the manufacturing method of display base plate provided in an embodiment of the present invention, due on conductive material layer with partly leading
The position of body layer contact is etched by dry etch process, and the etching precision of dry etch process is easier to control, and dry method
Etching technics can not perform etching semiconductor layer, therefore can be to avoid etching process to the shadow of the electrology characteristic of semiconductor layer
It rings.The manufacturing method of display base plate provided in an embodiment of the present invention can be good at solving the manufacture of BCE structure display base plates
Cheng Zhong, the problem of using wet-etching technology etching conductive material layers semiconductor layer being caused to spend quarter, and the equal of etching can be improved
One property, the manufacture for BCE structure display base plates provide scheme, suitable for factory's volume production demand.
The embodiment of the present invention additionally provides the display base plate that a kind of method using shown in Fig. 3 or Figure 12 manufactures, the display
Substrate can be array substrate or oled display substrate, and the display base plate can be BCE structure display base plates.The display base plate
Can include underlay substrate and, grid, gate insulation layer, semiconductor layer and the source-drain electrode layer being successively set on underlay substrate.
Wherein, source-drain electrode layer can be a layer structure, or multilayered structure.When source-drain electrode layer is a layer structure,
The display base plate can be the display base plate shown in Figure 11, and the display base plate can also include being located at semiconductor layer 014 and source
Barrier layer between drain electrode layer 015, the passivation layer on source-drain electrode layer 015 and the pixel electrode on passivation layer etc.；
When source-drain electrode layer is multilayered structure, which can be the display base plate shown in Figure 18, and the display base plate can be with
Including being located at the barrier layer between semiconductor layer 014 and source-drain electrode layer 015, passivation layer and position on source-drain electrode layer 015
In pixel electrode on passivation layer etc..
The embodiment of the present invention additionally provides a kind of display device, which can include display base plate, the display base
Plate can be the display base plate shown in Figure 11 or Figure 18.The display device can be liquid crystal panel, Electronic Paper, oled panel, hand
Any product with display function such as machine, tablet computer, television set, display, laptop, Digital Frame or navigator
Or component.
One of ordinary skill in the art will appreciate that hardware can be passed through by realizing all or part of step of above-described embodiment
It completes, relevant hardware can also be instructed to complete by program, the program can be stored in a kind of computer-readable
In storage medium, storage medium mentioned above can be read-only memory, disk or CD etc..
The foregoing is merely the present invention alternative embodiment, be not intended to limit the invention, it is all the present invention spirit and
Within principle, any modifications, equivalent replacements and improvements are made should all be included in the protection scope of the present invention.
Claims (10)
1. a kind of manufacturing method of display base plate, which is characterized in that the described method includes：
Grid, gate insulation layer and semiconductor layer are sequentially formed on underlay substrate；
Conductive material layer is formed on the underlay substrate of the semiconductor layer is formed with；
The conductive material layer is performed etching, obtains source-drain electrode layer, wherein, on the conductive material layer with the semiconductor layer
The position of contact is etched by dry etch process.
2. according to the method described in claim 1, it is characterized in that, described perform etching the conductive material layer, source is obtained
Drain electrode layer, wherein, the position contacted on the conductive material layer with the semiconductor layer is etched by dry etch process, bag
It includes：
The conductive material layer is performed etching by dry etch process, obtains source-drain electrode layer.
It is 3. according to the method described in claim 2, it is characterized in that, described on the underlay substrate of the semiconductor layer is formed with
Conductive material layer is formed, including：
Conductive material layer, the predetermined material bag are formed on the underlay substrate of the semiconductor layer is formed with using predetermined material
Include any one in metal molybdenum, metal tantalum and tungsten molybdenum.
4. according to the method described in claim 1, it is characterized in that, the conductive material layer includes at least two subconductivity materials
Layer, it is described that the conductive material layer is performed etching, source-drain electrode layer is obtained, wherein, it is partly led with described on the conductive material layer
The position of body layer contact is etched by dry etch process, including：
The subconductivity material layers in the conductive material layer, not contacted with the semiconductor layer are carried out by wet-etching technology
Etching；
By dry etch process in the conductive material layer, the subconductivity material layers contacted with the semiconductor layer are carved
Erosion, obtains source-drain electrode layer.
It is 5. according to the method described in claim 4, it is characterized in that, described on the underlay substrate of the semiconductor layer is formed with
Conductive material layer is formed, including：
Conductive material layer is formed on the underlay substrate of the semiconductor layer is formed with, the conductive material layer includes at least two
Subconductivity material layers, the formation of the subconductivity material layers contacted with the semiconductor layer in at least two subconductivity material layers
Material is predetermined material, and the predetermined material includes any one in metal molybdenum, metal tantalum and tungsten molybdenum.
6. according to the method described in claim 5, it is characterized in that, the conductive material layer include three sub- conductive material layers,
Three sub- conductive material layers are followed successively by gold according to close to the semiconductor layer to the formation material away from the semiconductor layer
Belong to molybdenum, metallic aluminium and metal molybdenum.
7. the method according to claim 3 or 5, which is characterized in that
The etching gas of the dry etch process are the mixed gas of sulfur fluoride gas and oxygen；Alternatively,
The etching gas of the dry etch process are the mixed gas of sulfur fluoride gas, oxygen and helium.
8. method according to any one of claims 1 to 6, which is characterized in that it is described that the conductive material layer is performed etching,
Source-drain electrode layer is obtained, including：
The conductive material layer is handled by patterning processes, obtains source-drain electrode layer, the patterning processes include photoresist
Coating, exposure, development, etching and photoresist lift off.
A kind of 9. display base plate manufactured using any method of claim 1 to 8, which is characterized in that the display base
Plate includes：Underlay substrate and, grid, gate insulation layer, semiconductor layer and the source-drain electrode being successively set on the underlay substrate
Layer.
10. a kind of display device, which is characterized in that the display device includes the display base plate described in claim 9.
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