CN108054103B - Display substrate, manufacturing method thereof and display device - Google Patents
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- CN108054103B CN108054103B CN201711325127.0A CN201711325127A CN108054103B CN 108054103 B CN108054103 B CN 108054103B CN 201711325127 A CN201711325127 A CN 201711325127A CN 108054103 B CN108054103 B CN 108054103B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78603—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the insulating substrate or support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
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- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
Abstract
The invention discloses a display substrate, a manufacturing method thereof and a display device, and belongs to the technical field of display. The method comprises the following steps: sequentially forming a grid electrode, a grid insulating layer and a semiconductor layer on a substrate; forming a conductive material layer on the base substrate on which the semiconductor layer is formed; and etching the conductive material layer to obtain a source drain electrode layer, wherein the part of the conductive material layer, which is in contact with the semiconductor layer, is etched by a dry etching process. The invention is helpful to avoid the influence of the etching process on the electrical characteristics of the semiconductor layer. The invention is used for manufacturing the display substrate.
Description
Technical Field
The invention relates to the technical field of display, in particular to a display substrate, a manufacturing method of the display substrate and a display device.
Background
The display substrate is a main display component of the display device, and the display substrate can be divided into an Etch Stop Layer (ESL) structure display substrate, a Back Channel Etched (BCE) structure display substrate, and a Top Gate (Top Gate) structure display substrate according to the structure of the display substrate. The BCE structure display substrate has the advantages of simple structure and the like, and is the key direction of future research and development.
The BCE structure display substrate comprises a substrate base plate, a grid electrode, a grid insulation layer (GI for short), a semiconductor layer, a source drain metal layer and the like, wherein the grid electrode, the GI for short, the semiconductor layer and the source drain metal layer are sequentially arranged on the substrate base plate, the source drain metal layer comprises a source electrode and a drain electrode, and a channel is formed between the source electrode and the drain electrode. When the BCE structure display substrate is manufactured, firstly, a grid electrode, a GI (gate-doped epitaxial) layer and a semiconductor layer are sequentially formed on a substrate base plate, then a metal material layer is formed on the substrate base plate on which the semiconductor layer is formed, and the metal material layer is etched through a wet etching process to obtain a source drain metal layer.
However, due to the influence of the etching precision of the wet etching process, when the metal material layer is etched, the semiconductor layer located below the metal material layer may have an over-etching phenomenon (that is, the semiconductor layer is etched), which affects the electrical characteristics of the semiconductor layer.
Disclosure of Invention
The invention provides a display substrate, a manufacturing method thereof and a display device, which can avoid the influence of an etching process on the electrical characteristics of a semiconductor layer. The technical scheme of the invention is as follows:
in a first aspect, a method for manufacturing a display substrate is provided, the method including:
sequentially forming a grid electrode, a grid insulating layer and a semiconductor layer on a substrate;
forming a conductive material layer on the base substrate on which the semiconductor layer is formed;
and etching the conductive material layer to obtain a source drain electrode layer, wherein the part of the conductive material layer, which is in contact with the semiconductor layer, is etched by a dry etching process.
Optionally, the etching is performed on the conductive material layer to obtain a source drain layer, where a portion of the conductive material layer in contact with the semiconductor layer is etched by a dry etching process, and the etching includes:
and etching the conductive material layer by a dry etching process to obtain a source drain layer.
Optionally, the forming a conductive material layer on the substrate base plate on which the semiconductor layer is formed includes:
and forming a conductive material layer on the substrate with the semiconductor layer by adopting a preset material, wherein the preset material comprises any one of molybdenum metal, tantalum metal and molybdenum tungsten.
Optionally, the conductive material layer includes at least two sub-conductive material layers, and the conductive material layer is etched to obtain a source drain layer, where a portion of the conductive material layer in contact with the semiconductor layer is etched by a dry etching process, including:
etching the sub conductive material layer which is not in contact with the semiconductor layer in the conductive material layer by a wet etching process;
and etching the sub-conductive material layer in contact with the semiconductor layer in the conductive material layer by a dry etching process to obtain the source drain layer.
Optionally, the forming a conductive material layer on the substrate base plate on which the semiconductor layer is formed includes:
forming a conductive material layer on the substrate base plate on which the semiconductor layer is formed, wherein the conductive material layer comprises at least two sub-conductive material layers, the forming material of the sub-conductive material layer in contact with the semiconductor layer in the at least two sub-conductive material layers is a preset material, and the preset material comprises any one of metal molybdenum, metal tantalum and molybdenum tungsten.
Optionally, the conductive material layer includes three sub-conductive material layers, and the three sub-conductive material layers are metal molybdenum, metal aluminum, and metal molybdenum in sequence from a material close to the semiconductor layer to a material far away from the semiconductor layer.
Optionally, the etching gas of the dry etching process is a mixed gas of sulfur fluoride gas and oxygen; or the etching gas of the dry etching process is a mixed gas of sulfur fluoride gas, oxygen and helium.
Optionally, the etching the conductive material layer to obtain a source drain layer includes:
and processing the conductive material layer through a composition process to obtain the source drain layer, wherein the composition process comprises photoresist coating, exposure, development, etching and photoresist stripping.
In a second aspect, there is provided a display substrate manufactured by the method of the first aspect or any alternative form of the first aspect, the display substrate comprising: the semiconductor device comprises a substrate base plate, and a grid electrode, a grid insulation layer, a semiconductor layer and a source drain layer which are sequentially arranged on the substrate base plate.
In a third aspect, a display device is provided, which comprises the display substrate of the second aspect.
The technical scheme provided by the invention has the beneficial effects that:
the invention provides a display substrate, a manufacturing method thereof and a display device, wherein the method comprises the following steps: sequentially forming a grid electrode, a grid insulating layer and a semiconductor layer on a substrate; forming a conductive material layer on the base substrate on which the semiconductor layer is formed; and etching the conductive material layer to obtain a source drain electrode layer, wherein the part of the conductive material layer, which is in contact with the semiconductor layer, is etched by a dry etching process. Because the part of the conductive material layer, which is in contact with the semiconductor layer, is etched by the dry etching process, the etching precision of the dry etching process is easy to control, and the dry etching process cannot etch the semiconductor layer, the influence of the etching process on the electrical characteristics of the semiconductor layer can be avoided.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a display substrate provided in the related art;
FIG. 2 is a flowchart illustrating a method of fabricating a display substrate according to an embodiment of the present invention;
FIG. 3 is a flowchart of a method of fabricating another display substrate according to an embodiment of the present invention;
fig. 4 is a schematic diagram illustrating a gate formed on a substrate according to an embodiment of the present invention;
fig. 5 is a schematic diagram illustrating a gate insulating layer formed on a substrate with a gate formed thereon according to an embodiment of the present invention;
fig. 6 is a schematic view after a semiconductor layer is formed on a substrate having a gate insulating layer formed thereon according to an embodiment of the present invention;
fig. 7 is a schematic view of a substrate with a semiconductor layer formed thereon after forming a conductive medium layer according to an embodiment of the present invention;
FIG. 8 is a schematic diagram illustrating a substrate with a conductive dielectric layer formed thereon after a photoresist layer is formed thereon according to an embodiment of the present invention;
FIG. 9 is a schematic view of a photoresist layer after exposure and development according to an embodiment of the present invention;
FIG. 10 is a schematic diagram illustrating an etched conductive dielectric layer according to an embodiment of the present invention;
FIG. 11 is a schematic view of a photoresist stripped structure according to an embodiment of the present invention;
FIG. 12 is a flowchart illustrating a method of fabricating a display substrate according to another embodiment of the present invention;
fig. 13 is a schematic view of a substrate with a semiconductor layer formed thereon after forming a conductive medium layer according to an embodiment of the present invention;
FIG. 14 is a schematic diagram illustrating a substrate with a conductive dielectric layer formed thereon after a photoresist layer is formed thereon according to an embodiment of the present invention;
FIG. 15 is a schematic view of a photoresist layer after exposure and development in accordance with an embodiment of the present invention;
FIG. 16 is a schematic diagram illustrating a sub-conducting medium layer not in contact with a semiconductor layer after etching according to an embodiment of the present invention;
FIG. 17 is a schematic diagram illustrating a sub-conducting medium layer in contact with a semiconductor layer after etching according to an embodiment of the present invention;
FIG. 18 is a schematic diagram illustrating a process of stripping photoresist according to an embodiment of the present invention.
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer, the present invention will be described in further detail with reference to the accompanying drawings, and it is apparent that the described embodiments are only a part of the embodiments of the present invention, not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
With the progress of the manufacturing process of Display products, the old Thin Film Transistor Liquid Crystal Display (TFT LCD) technology, such as Organic Light-Emitting Diode (OLED) products, is gradually replaced by new Display technologies in the small-sized field. The display substrate is used as a main display component of a display product, and may be classified into an ESL structure display substrate, a BCE structure display substrate, and a top gate structure display substrate according to their structures. Compared with an ESL structure display substrate, the BCE structure display substrate is simpler in structural process and is the key direction of future research and development. Referring to fig. 1, a schematic structural diagram of a display substrate 00 provided in the related art is shown, where the display substrate 00 may be a BCE structural display substrate. Referring to fig. 1, a display substrate 00 includes a substrate 001, and a gate electrode 002, a gate insulating layer 003, a semiconductor layer 004 and a source-drain metal layer 005 sequentially disposed on the substrate 001, wherein the source-drain metal layer 005 includes a source electrode 0051 and a drain electrode 0052, and a channel (not shown in fig. 1) is formed between the source electrode 0051 and the drain electrode 0052. In manufacturing the display substrate 00, first, a gate electrode 002, a gate insulating layer 003 and a semiconductor layer 004 are sequentially formed on a substrate 001, then a metal material layer is formed on the substrate 001 on which the semiconductor layer 004 is formed, and the metal material layer is etched by a wet etching process to obtain a source/drain metal layer 005. However, since the etching precision of the wet etching process is difficult to control, when the metal material layer is etched by the wet etching process, as shown in fig. 1, over-etching of the semiconductor layer 004 may be caused, which may result in poor uniformity of the remaining portion of the semiconductor layer 004, affect the electrical characteristics of the semiconductor layer 004, and cause difficulty in manufacturing the display substrate, which is not favorable for mass production of the display substrate.
Embodiments of the present invention provide a method for manufacturing a display substrate, which can avoid an influence of an etching process on an electrical characteristic of a semiconductor layer, reduce a manufacturing difficulty of the display substrate, and facilitate mass production of the display substrate.
Referring to fig. 2, a flowchart of a method for manufacturing a display substrate according to an embodiment of the present invention is shown, and referring to fig. 2, the method includes:
And 203, etching the conductive material layer to obtain a source drain layer, wherein the part of the conductive material layer, which is in contact with the semiconductor layer, is etched by a dry etching process.
In summary, in the manufacturing method of the display substrate provided in the embodiment of the invention, the portion of the conductive material layer in contact with the semiconductor layer is etched by the dry etching process, and the etching precision of the dry etching process is easy to control, and the dry etching process cannot etch the semiconductor layer, so that the influence of the etching process on the electrical characteristics of the semiconductor layer can be avoided.
In one possible implementation, step 203 may include: and etching the conductive material layer by a dry etching process to obtain the source drain layer.
Step 202 may include: and forming a conductive material layer on the substrate with the semiconductor layer by adopting a preset material, wherein the preset material comprises any one of metal molybdenum, metal tantalum and molybdenum tungsten.
In another possible implementation manner, the conductive material layer includes at least two sub-conductive material layers, and step 203 may include:
etching the sub-conductive material layer which is not in contact with the semiconductor layer in the conductive material layer by a wet etching process;
and etching the sub-conductive material layer in contact with the semiconductor layer in the conductive material layer by a dry etching process to obtain the source drain layer.
Step 202 may include: and forming a conductive material layer on the substrate with the semiconductor layer, wherein the conductive material layer comprises at least two sub-conductive material layers, the forming material of the sub-conductive material layer which is in contact with the semiconductor layer in the at least two sub-conductive material layers is a preset material, and the preset material comprises any one of metal molybdenum, metal tantalum and molybdenum tungsten.
Optionally, the conductive material layer includes three sub-conductive material layers, and the three sub-conductive material layers are metal molybdenum, metal aluminum, and metal molybdenum in sequence from the formation material close to the semiconductor layer to the formation material far from the semiconductor layer.
Optionally, the etching gas of the dry etching process is a mixed gas of sulfur fluoride gas and oxygen; or,
the etching gas of the dry etching process is a mixed gas of sulfur fluoride gas, oxygen and helium.
Optionally, step 203 may comprise: and processing the conductive material layer through a composition process to obtain the source drain layer, wherein the composition process comprises photoresist coating, exposure, development, etching and photoresist stripping.
All the above-mentioned optional technical solutions can be combined arbitrarily to form the optional embodiments of the present invention, and are not described herein again.
In summary, in the manufacturing method of the display substrate provided in the embodiment of the invention, the portion of the conductive material layer in contact with the semiconductor layer is etched by the dry etching process, and the etching precision of the dry etching process is easy to control, and the dry etching process cannot etch the semiconductor layer, so that the influence of the etching process on the electrical characteristics of the semiconductor layer can be avoided.
Referring to fig. 3, a flowchart of another method for manufacturing a display substrate according to an embodiment of the present invention is shown, and referring to fig. 3, the method includes:
Referring to fig. 4, a schematic diagram of a substrate 011 with a gate 012 formed thereon according to an embodiment of the present invention is shown. The substrate base plate 011 may be a transparent base plate, and may be a base plate made of a light-guiding and non-metallic material having a certain firmness, such as glass, quartz, or transparent resin. The gate electrode 012 may be formed of molybdenum (Mo), copper (Cu), aluminum (Al), or an alloy thereof, and a thickness of the gate electrode 012 may be set according to actual conditions, for example, the thickness of the gate electrode 012 is required according to a forming material of the gate electrode 012 and a resistance of the gate electrode 012, which is not limited in the embodiment of the invention.
For example, the gate electrode 012 is formed by using metal Mo. A layer of metal Mo with a certain thickness is deposited on the substrate 011 by magnetron sputtering, thermal evaporation or Plasma Enhanced Chemical Vapor Deposition (PECVD) to obtain a Mo metal layer, and then the Mo metal layer is processed by a one-step patterning process to obtain the gate 012. Wherein, once the picture composition technology includes: coating, exposing, developing, etching and stripping photoresist, so that the processing of the metal Mo material layer by the one-step composition process to obtain the gate 012 may include: coating one deck photoresist on metal Mo material layer and forming the photoresist layer, adopt the mask version to expose the photoresist layer, make the photoresist layer form complete exposure area and non-exposure area, later adopt the development technology to handle, make the photoresist in complete exposure area get rid of completely, the photoresist in non-exposure area all remains, the area that corresponds in complete exposure area on to metal Mo material layer through the etching process is corroded, later strip the photoresist in non-exposure area, the regional grid 012 that forms that the non-exposure area corresponds on the metal Mo material layer. It should be noted that, in the embodiment of the present invention, the gate 012 is formed by using a positive photoresist, and in practical applications, the gate 012 can also be formed by using a negative photoresist, which is not described herein again.
Referring to fig. 5, a schematic diagram of a substrate 011 with a gate electrode 012 formed thereon after a gate insulating layer 013 is formed thereon according to an embodiment of the present invention is shown. Wherein, the gate insulating layer 013 can adopt SiO2(Chinese: silica), SiNxThe thickness of the gate insulating layer 013 may be set according to the actual circumstances, for example, the thickness of the gate insulating layer 013 is set according to the material for forming the gate insulating layer 013 and the resistance of the gate insulating layer 013, and this is not limited in the embodiment of the present invention.
Illustratively, to employ SiNxThe gate insulating layer 013 is formed as an example. A layer of SiN with a certain thickness is deposited on a substrate 011 with a grid 012 formed thereon by PECVD processxTo obtain SiNxMaterial layer, then to SiNxThe material layer is baked to form a gate insulating layer 013. It should be noted that, in practical applications, when the gate insulating layer 013 includes a pattern, the SiN may also be patterned by a patterning processxThe material layer is processed to form a gate insulating layer 013, which is not limited in the embodiment of the invention.
Step 303 is to form a semiconductor layer on the substrate on which the gate insulating layer is formed.
Referring to fig. 6, a schematic diagram of a semiconductor layer 014 formed on a substrate 011 with a gate insulating layer 013 according to an embodiment of the invention is shown. The semiconductor layer 014 may be formed of a transparent amorphous oxide such as Indium Gallium Zinc Oxide (IGZO), and the thickness of the semiconductor layer 014 may be set according to actual conditions, which is not limited in the embodiment of the invention.
For example, the semiconductor layer 014 is formed using IGZO as an example. An IGZO material layer is formed by depositing an IGZO layer with a certain thickness on the substrate 011 on which the gate insulating layer 013 is formed by magnetron sputtering, thermal evaporation, PECVD or the like, and then the IGZO material layer is processed by a one-step patterning process to form the semiconductor layer 014. The process of processing the IGZO material layer by the one-step composition process is similar to the process of processing the metal Mo material layer by the one-step composition process, and details of the embodiment of the present invention are not repeated herein. However, it should be noted that, depending on the material of the semiconductor layer 014, the IGZO material layer is generally etched by a wet etching process in the process of processing the IGZO material layer by a single patterning process.
Fig. 7 is a schematic diagram illustrating a conductive material layer Y formed on a substrate 011 with a semiconductor layer 014 according to an embodiment of the invention. Here, the conductive material layer Y may be formed on the substrate 011 on which the semiconductor layer 014 is formed, using a predetermined material, and the predetermined material may include any one of molybdenum (Mo), tantalum (Ta), and molybdenum tungsten (MoW), and of course, the predetermined material may be a conductive material such as graphene. That is, in the embodiment of the present invention, the conductive material layer Y may be formed of any one of metal Mo, metal Ta, MoW, and graphene. In the embodiment of the present invention, the thickness of the conductive material layer Y may be determined according to the formation material of the conductive material layer Y and the resistance requirement of the source/drain layer. Because the resistivity of different materials is different, the thickness of the conductive material layer Y formed by using different materials is usually different in order to meet the resistance requirement of the source/drain layer. Alternatively, when the conductive material layer Y is formed using metal Mo, the thickness of the conductive material layer Y may have a range of values
To
(angstrom), when the metal Ta conductive material layer Y is used, the thickness of the conductive material layer Y may range from 3um to 4um (micrometers), which is not limited in the embodiments of the present invention.
For example, the conductive material layer Y is formed by using metal Mo. Depositing a layer with a thickness of about 011A on the substrate with the semiconductor layer 014 by magnetron sputtering, thermal evaporation or PECVD
To
The metal Mo between the two layers is the metal Mo material layer, which is the conductive material layer Y.
And 305, etching the conductive material layer to obtain a source drain layer, wherein the part of the conductive material layer, which is in contact with the semiconductor layer, is etched by a dry etching process.
In the embodiment of the present invention, in order to avoid over-etching the semiconductor layer 014 by using the wet etching process, the source drain layer may be obtained by directly etching the conductive material layer Y by using the dry etching process; or, in order to increase the etching rate, shorten the etching time, and avoid overetching the semiconductor layer 014 by the wet etching process, a portion of the conductive material layer Y not in contact with the semiconductor layer 014 may be etched by the wet etching process, but the conductive material layer Y is not etched through, and then a portion of the conductive material layer Y in contact with the semiconductor layer 014 is etched by the dry etching process, and the source/drain electrode layer is obtained by etching through the conductive material layer Y.
Optionally, the source and drain layers may be obtained by processing the conductive material layer Y through a patterning process, where the patterning process includes photoresist coating, exposure, development, etching, and photoresist stripping. Fig. 8 to fig. 11 are schematic diagrams of a source drain layer 015 obtained by processing a conductive material layer Y through a patterning process according to an embodiment of the present invention. In the process of processing the conductive material layer Y by the composition process, first, as shown in fig. 8, a layer of photoresist with a certain thickness is coated on the conductive material layer Y to obtain a photoresist layer P, then, the photoresist layer P is exposed by using a mask to form a fully exposed region and a non-exposed region, then, a developing process is used to completely remove the photoresist in the fully exposed region, the photoresist in the non-exposed region is completely remained to obtain the structure shown in fig. 9, then, the region corresponding to the fully exposed region on the conductive material layer Y is etched by an etching process to obtain the structure shown in fig. 10, and finally, the photoresist in the non-exposed region is stripped to obtain the structure shown in fig. 11. Referring to fig. 11, the source-drain layer 015 includes a source electrode 0151 and a drain electrode 0152, a channel is formed between the source electrode 0151 and the drain electrode 0152, thicknesses of positions on the semiconductor layer 014 below the source-drain layer 015 are equal, an over-etching phenomenon does not occur on the semiconductor layer 014, and conductivity characteristics of the positions on the semiconductor layer 014 are not different. It is to be noted that the structures shown in fig. 10 and 11 are merely exemplary, and in practical applications, an inclination angle (Taper) may exist between the source electrode 0151 and the semiconductor layer 014, and between the drain electrode 0152 and the semiconductor layer 014. In addition, the embodiment of the present invention is described by taking an example of forming the source and drain layer 015 by using a positive photoresist, and in practical applications, the source and drain layer 015 may also be formed by using a negative photoresist, which is not described herein again.
It should be noted that, in the process of obtaining the structure shown in fig. 10 by performing the etching process on the region corresponding to the completely exposed region on the conductive material layer Y, in order to avoid over-etching the semiconductor layer 014 by the wet etching process, the region corresponding to the completely exposed region on the conductive material layer Y may be directly etched by the dry etching process, and the conductive material layer Y is etched through, so as to obtain the structure shown in fig. 10; or, in order to increase the etching rate, shorten the etching time, and avoid the wet etching process from etching the semiconductor layer 014, the wet etching process may be performed to etch the region corresponding to the completely exposed region on the conductive material layer Y, but not to etch through the conductive material layer Y, and then the dry etching process is performed to continue etching the part of the conductive material layer Y that is not etched through the wet etching process, and to etch through the conductive material layer Y, so as to obtain the structure shown in fig. 10.
In the embodiment of the invention, the etching gas of the dry etching process can be Sulfur Fluoride (SF)6) Gas and oxygen (O)2) The mixed gas of (3); alternatively, the etching gas for the dry etching process may be SF6Gas, O2And helium (He). On one hand, the etching gas of the dry etching process can chemically react with the forming material of the conductive material layer Y, but does not chemically react with the forming material of the semiconductor layer 014, so that in the process of etching the conductive material layer Y by the dry etching process, the semiconductor layer 014 is not over-etched, the semiconductor layer 014 is not damaged in the etching process, and the influence of the etching process on the electrical characteristics of the semiconductor layer 014 is avoided; on the other hand, the dry etching process has high etching precision and good etching uniformity, and can improve the etching uniformity. Wherein, SF6A main etching gas for the conductive material layer Y, which is mainly used for performing a chemical reaction with a material forming the conductive material layer Y to etch the conductive material layer Y, O2Mainly used for ashing the photoresist on the non-exposure area close to the fully exposed area so as to form inclination angles between the source 0151 and the semiconductor layer 014 and between the drain 0152 and the semiconductor layer 014 after etching is completed, and He is used as inert gas and is mainly used for enabling SF to be sprayed on the surface of the semiconductor layer 0146And O2Mixing uniformly.
After the source drain layer 015 is obtained, a display substrate is obtained. In the embodiment of the present invention, the display substrate may be an array substrate or an OLED display substrate, and the display substrate may further include other structures, for example, the display substrate may further include a barrier layer located between the semiconductor layer 014 and the source drain layer 015, a passivation layer located on the source drain layer 015, a pixel electrode located on the passivation layer, and the like, which are not described herein again in the embodiment of the present invention.
In summary, in the manufacturing method of the display substrate provided in the embodiment of the invention, the portion of the conductive material layer in contact with the semiconductor layer is etched by the dry etching process, and the etching precision of the dry etching process is easy to control, and the dry etching process cannot etch the semiconductor layer, so that the influence of the etching process on the electrical characteristics of the semiconductor layer can be avoided. The manufacturing method of the display substrate provided by the embodiment of the invention can well solve the problem that the semiconductor layer is over-etched due to the fact that the conductive material layer is etched by adopting a wet etching process in the manufacturing process of the BCE structure display substrate, and provides a scheme for manufacturing the BCE structure display substrate.
Referring to fig. 12, a flowchart of a method for manufacturing a display substrate according to another embodiment of the present invention is shown, and referring to fig. 12, the method includes:
And 1202, forming a gate insulating layer on the substrate with the formed gate.
The implementation process of steps 1201 to 1203 may refer to steps 301 to 303 in the embodiment shown in fig. 3, and this embodiment is not described herein again.
In an embodiment of the present invention, a conductive material layer may be formed on the substrate 011 on which the semiconductor layer 014 is formed, the conductive material layer includes at least two sub-conductive material layers, and a material forming the sub-conductive material layer in contact with the semiconductor layer 014 may be a predetermined material, and the predetermined material may include any one of metal Mo, metal Ta, and MoW. Of course, besides, the predetermined material may also be a conductive material such as graphene. That is, in this embodiment, the material for forming the sub-conductive material layer in contact with the semiconductor layer 014 may be any one of metal Mo, metal Ta, MoW and graphene, the thickness of each sub-conductive material layer may be determined according to the material for forming the sub-conductive material layer and the resistance requirement of the source/drain layer, and the thickness of the sub-conductive material layer in contact with the semiconductor layer 014 is generally large in order to ensure the resistance requirement of the source/drain layer.
In the embodiment of the present invention, the conductive material layer includes three sub-conductive material layers. Referring to fig. 13, which shows a schematic diagram of a conductive material layer Y formed on a substrate 011 with a semiconductor layer 014 according to an embodiment of the present invention, referring to fig. 13, the conductive material layer Y includes three sub-conductive material layers, namely a sub-conductive material layer Y1, a sub-conductive material layer Y2 and a sub-conductive material layer Y3, among the three sub-conductive material layers, the sub-conductive material layer Y1 is in contact with the semiconductor layer 014, therefore, the sub-conductive material layer Y1 is formed of any one of metal Mo, metal Ta and MoW, and the thickness of each sub-conductive material layer can be determined according to the formation material of the sub-conductive material layer and the resistance requirement of the source and drain layers. Optionally, in the embodiment of the present invention, taking metal Mo to form the sub conductive material layer Y1, metal Al to form the sub conductive material layer Y2, and metal Mo to form the sub conductive material layer Y3 as examples, a value range of a thickness of the sub conductive material layer Y1 may be set as
The thickness of the sub-conductive material layer Y2 may have a range of values
The thickness of the sub-conductive material layer Y3 may have a range of values
For example, forming the conductive material layer Y on the substrate base plate 011 on which the semiconductor layer 014 is formed may include: first, a layer of a thickness of about 011, on which a semiconductor layer 014 is formed, is deposited by magnetron sputtering, thermal evaporation, PECVD or the like
Obtaining a metal Mo material layer, wherein the metal Mo material layer is the sub-conductive material layer Y1; then, a magnetron sputtering method, a thermal evaporation method or a PECVD method or the like is adopted to deposit on the substrate 011 on which the metal Mo material layer is formedA layer with a thickness of
Obtaining a metal Al material layer, wherein the metal Al material layer is the sub-conductive material layer Y2; finally, a layer of metal Al material layer is deposited on the substrate 011 by magnetron sputtering, thermal evaporation or PECVD and other methods
The metal Mo layer is the sub-conductive material layer Y3, so that the conductive material layer Y shown in fig. 13 is obtained.
And 1205, etching the conductive material layer to obtain a source drain layer, wherein the part of the conductive material layer, which is in contact with the semiconductor layer, is etched by a dry etching process.
In the embodiment of the present invention, in order to avoid over-etching the semiconductor layer 014 by using the wet etching process, the source drain electrode layer may be obtained by directly etching the conductive material layer by using the dry etching process; or, in order to increase the etching rate, shorten the etching time, and avoid the over-etching of the semiconductor layer 014 by the wet etching process, the sub-conductive material layer not in contact with the semiconductor layer 014 in the conductive material layer may be etched by the wet etching process, and then the sub-conductive material layer in contact with the semiconductor layer 014 in the conductive material layer may be etched by the dry etching process, so as to obtain the source/drain electrode layer. Since the thickness of the sub-conductive material layer in contact with the semiconductor layer 014 is generally large and the etching rate of the wet etching process is generally large, the sub-conductive material layer in contact with the semiconductor layer 014 may be over-etched during the etching of the sub-conductive material layer not in contact with the semiconductor layer 014 in order to shorten the etching time of the conductive material layer. In the embodiment of the present invention, the sub-conductive material layer not in contact with the semiconductor layer 014 may be etched by controlling the etching duration of the wet etching process, and the sub-conductive material layer in contact with the semiconductor layer 014 is over-etched. In the embodiment of the invention, after the material and the thickness of the sub-conductive material layer and the etching liquid of the wet etching process are determined, the etching duration of the wet etching process is determined, and after the material and the thickness of the sub-conductive material layer and the etching gas of the dry etching process are determined, the etching duration of the dry etching process is determined. The etching rate of the dry etching process can be determined by the etching power, the etching voltage, the flow rate of the etching gas and the like.
Optionally, the source/drain layer may be obtained by processing the conductive material layer through a patterning process, where the patterning process includes photoresist coating, exposure, development, etching, and photoresist stripping. Fig. 14 to fig. 18 are schematic diagrams of a source-drain layer 015 obtained by processing a conductive material layer Y through a patterning process according to an embodiment of the present invention, which are described in this embodiment by taking an example that a sub-conductive material layer not in contact with a semiconductor layer 014 in the conductive material layer Y is etched through a wet etching process, and then a sub-conductive material layer in contact with the semiconductor layer 014 in the conductive material layer Y is etched through a dry etching process. In the process of processing the conductive material layer Y by the patterning process, as shown in fig. 14, firstly, a layer of photoresist with a certain thickness is coated on the conductive material layer Y (that is, on the sub-conductive material layer Y3) to obtain a photoresist layer P, then, the photoresist layer P is exposed by using a mask to form a fully exposed region and a non-exposed region, then, the photoresist in the fully exposed region is completely removed by using a developing process, the photoresist in the non-exposed region is completely remained to obtain a structure as shown in fig. 15, then, the regions corresponding to the fully exposed regions on the sub-conductive material layer Y3 and the sub-conductive material layer Y2 are sequentially etched by using a wet etching process to obtain a structure as shown in fig. 16, then, the region corresponding to the fully exposed region on the sub-conductive material layer Y1 is etched by using a dry etching process to obtain a structure as shown in fig. 17, finally, the photoresist in the unexposed areas is stripped to obtain the structure shown in FIG. 18. Referring to fig. 18, the source-drain layer 015 includes a source 0151 and a drain 0152, a channel is formed between the source 0151 and the drain 0152, the source 0151 and the drain 0152 are both of a three-layer structure, and an over-etching phenomenon does not occur on the semiconductor layer 014 below the source-drain layer 015. Note that the structures shown in fig. 17 and 18 are merely exemplary, and in practical applications, an inclination angle may exist between the source electrode 0151 and the semiconductor layer 014, and between the drain electrode 0152 and the semiconductor layer 014. In addition, the embodiment of the present invention is described by taking an example of forming the source and drain layer 015 by using a positive photoresist, and in practical applications, the source and drain layer 015 may also be formed by using a negative photoresist, which is not described herein again.
In the embodiment of the invention, the etching gas of the dry etching process can be SF6Gas and O2The mixed gas of (3); alternatively, the etching gas for the dry etching process may be SF6Gas, O2And He. On one hand, the etching gas of the dry etching process can chemically react with the forming material of the sub-conductive material layer Y1, but cannot chemically react with the forming material of the semiconductor layer 014, so that an over-etching phenomenon cannot occur on the semiconductor layer 014 in the process of etching the sub-conductive material layer Y1 by the dry etching process, the semiconductor layer 014 is not damaged by the etching process, and the influence of the etching process on the electrical characteristics of the semiconductor layer 014 is avoided; on the other hand, the dry etching process has high etching precision and good etching uniformity, and can improve the etching uniformity. Wherein, SF6O is a main etching gas for the sub-conductive material layer Y1, which is mainly used for chemically reacting with the material for forming the sub-conductive material layer Y1 to etch the sub-conductive material layer Y12Mainly used for ashing the photoresist on the non-exposure area close to the fully exposed area so as to form inclination angles between the source 0151 and the semiconductor layer 014 and between the drain 0152 and the semiconductor layer 014 after etching is completed, and He is used as inert gas and is mainly used for enabling SF to be sprayed on the surface of the semiconductor layer 0146And O2Mixing uniformly.
In the embodiment of the invention, the conductive material layer is etched by utilizing the selectivity of the dry etching process to the material, so that the damage of the etching process to the semiconductor layer 014 is avoided, in addition, because the etching precision of the dry etching process is higher, the etching uniformity can be improved, and the dry etching is vertical etching, so that the error of Critical Dimension (CD) Bais can be in a very small range, wherein the vertical etching refers to etching from the direction vertical to the film surface to be etched, and the CD Bais refers to the difference between the width of a complete exposure area of a photoresist layer (namely the distance between non-exposure areas of the photoresist layer) and the width of a channel formed by etching (namely the distance between a source electrode and a drain electrode). In order to avoid the influence on the characteristics of the semiconductor layer 014 during the dry etching, the etching voltage may be appropriately reduced to weaken the bombardment strength of the etching gas during the etching, the frequency of replacing the exhaust gas during the dry etching may be increased to avoid the contamination of the semiconductor layer by the etching reactant, and the semiconductor layer 014 may be improved by the temperature treatment of the subsequent process (e.g., CVD process or annealing process).
After the source drain layer 015 is obtained, a display substrate is obtained. In the embodiment of the present invention, the display substrate may be an array substrate or an OLED display substrate, and the display substrate may further include other structures, for example, the display substrate may further include a blocking layer located between the semiconductor layer 014 and the source drain layer 015, a passivation layer located on the source drain layer 015, a pixel electrode located on the passivation layer, and the like, which are not described herein again in the embodiment of the present invention.
In summary, in the manufacturing method of the display substrate provided in the embodiment of the invention, the portion of the conductive material layer in contact with the semiconductor layer is etched by the dry etching process, and the etching precision of the dry etching process is easy to control, and the dry etching process cannot etch the semiconductor layer, so that the influence of the etching process on the electrical characteristics of the semiconductor layer can be avoided. The manufacturing method of the display substrate provided by the embodiment of the invention can well solve the problem that the semiconductor layer is over-etched due to the fact that the conductive material layer is etched by adopting a wet etching process in the manufacturing process of the BCE structure display substrate, can improve the etching uniformity, provides a scheme for manufacturing the BCE structure display substrate, and is suitable for the requirement of mass production of factories.
The embodiment of the invention also provides a display substrate manufactured by the method shown in fig. 3 or fig. 12, wherein the display substrate can be an array substrate or an OLED display substrate, and the display substrate can be a BCE structure display substrate. The display substrate can comprise a substrate base plate, and a grid electrode, a grid insulation layer, a semiconductor layer and a source drain layer which are sequentially arranged on the substrate base plate.
The source and drain layers may be of a single-layer structure or a multi-layer structure. When the source-drain electrode layer is a layer structure, the display substrate may be the display substrate shown in fig. 11, and the display substrate may further include a barrier layer located between the semiconductor layer 014 and the source-drain electrode layer 015, a passivation layer located on the source-drain electrode layer 015, a pixel electrode located on the passivation layer, and the like; when the source-drain electrode layer has a multilayer structure, the display substrate may be the display substrate shown in fig. 18, and the display substrate may further include a barrier layer located between the semiconductor layer 014 and the source-drain electrode layer 015, a passivation layer located on the source-drain electrode layer 015, a pixel electrode located on the passivation layer, and the like.
Embodiments of the present invention further provide a display device, which may include a display substrate, where the display substrate may be a display substrate shown in fig. 11 or fig. 18. The display device can be any product or component with a display function, such as a liquid crystal panel, electronic paper, an OLED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame or a navigator and the like.
It will be understood by those skilled in the art that all or part of the steps for implementing the above embodiments may be implemented by hardware, or may be implemented by a program instructing relevant hardware, where the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a magnetic disk or an optical disk, etc.
The invention is not to be considered as limited to the particular embodiments shown and described, but is to be understood that various modifications, equivalents, improvements and the like can be made without departing from the spirit and scope of the invention.
Claims (5)
1. The manufacturing method of the display substrate is characterized in that the display substrate is a back channel etching BCE structure display substrate; the method comprises the following steps:
sequentially forming a grid electrode, a grid insulating layer and a semiconductor layer on a substrate;
forming a conductive material layer on the base substrate on which the semiconductor layer is formed;
etching the conductive material layer to obtain a source drain layer, wherein the part of the conductive material layer, which is in contact with the semiconductor layer, is etched by a dry etching process, the thickness of each position on the semiconductor layer is equal, and the conductive characteristics of each position on the semiconductor layer are not different;
the conductive material layer comprises three sub-conductive material layers, the three sub-conductive material layers are metal molybdenum, metal aluminum and metal molybdenum in sequence from the part close to the semiconductor layer to the part far away from the semiconductor layer, and the value ranges of the thicknesses of the three sub-conductive material layers are respectively from the part close to the semiconductor layer to the part far away from the semiconductor layer
And
the etching is carried out on the conductive material layer to obtain a source drain layer, wherein the part, in contact with the semiconductor layer, of the conductive material layer is etched through a dry etching process, and the etching process comprises the following steps:
etching a sub conductive material layer which is not in contact with the semiconductor layer in the conductive material layers by a wet etching process, and etching the sub conductive material layer which is in contact with the semiconductor layer without etching the conductive material layer;
and etching the sub-conductive material layer in the conductive material layer, which is in contact with the semiconductor layer, by a dry etching process, and etching through the conductive material layer to obtain the source drain layer.
2. The method of claim 1,
the etching gas of the dry etching process is a mixed gas of sulfur fluoride gas and oxygen; or,
the etching gas of the dry etching process is a mixed gas of sulfur fluoride gas, oxygen and helium.
3. The method according to claim 1 or 2, wherein the etching the conductive material layer to obtain a source drain layer comprises:
and processing the conductive material layer through a composition process to obtain the source drain layer, wherein the composition process comprises photoresist coating, exposure, development, etching and photoresist stripping.
4. A display substrate manufactured by the method of any one of claims 1 to 3, wherein the display substrate comprises: the semiconductor device comprises a substrate, a grid electrode, a grid insulation layer, a semiconductor layer and a source drain layer which are sequentially arranged on the substrate, wherein the thickness of each position on the semiconductor layer is equal, and the conducting characteristics of each position on the semiconductor layer are not different;
the source drain layer comprises three sublayers, the three sublayers are metal molybdenum, metal aluminum and metal molybdenum in sequence from the part close to the semiconductor layer to the part far away from the semiconductor layer, and the value ranges of the thicknesses of the three sublayers are respectively from the part close to the semiconductor layer to the part far away from the semiconductor layer
And
5. a display device, characterized in that the display device comprises the display substrate of claim 4.
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