CN104600083A - Thin film transistor array substrate and preparation method thereof, display panel and display device - Google Patents
Thin film transistor array substrate and preparation method thereof, display panel and display device Download PDFInfo
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- CN104600083A CN104600083A CN201510046638.3A CN201510046638A CN104600083A CN 104600083 A CN104600083 A CN 104600083A CN 201510046638 A CN201510046638 A CN 201510046638A CN 104600083 A CN104600083 A CN 104600083A
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Abstract
The invention discloses a thin film transistor array substrate, a preparation method of the thin film transistor array substrate, a display panel and a display device. The thin film transistor array substrate comprises a substrate base plate, gate electrodes on the substrate base plate, a gate insulator layer, an active layer, source and drain electrodes, data lines and pixel electrodes; the active layer is an oxide semiconductor one, the source and drain electrodes, the data lines and the pixel electrodes are arranged on the same layer and made of the same material, and the source and drain electrodes directly contact with the active layer. In comparison with the existing technology, the oxide semiconductor thin film transistor array substrate can be reduced in technological process when being prepared, improved in production efficiency and saved in production cost.
Description
Technical field
The present invention relates to Display Technique field, particularly relate to a kind of thin-film transistor array base-plate and preparation method thereof, display floater and display unit.
Background technology
In plane indication example as in liquid crystal display (LCD), display of organic electroluminescence (OLED) or inorganic EL display, thin-film transistor is generally be used as switch element to control the operation of pixel electrode, or being used as driving element drives pixel.At present, except comprising the thin-film transistor of the silicon fiml semiconductors such as amorphous silicon (a-Si) and polysilicon (poly-Si), the thin-film transistor comprising oxide (Oxide) semiconductor more and more receives publicity, it relies on the advantages such as technique is simple, film characteristics is stable, is the main flow of thin-film transistor research and development gradually.
Be illustrated in figure 1 the structural representation of existing oxide semiconductor thin-film transistor array base palte, it comprises: underlay substrate 1, gate electrode 2a, gate insulation layer 3, oxide semiconductor active layer 4a, etching barrier layer 10, source electrode 5a, drain electrode 5b, passivation layer 8 and pixel electrode 9a.This kind of structure is channel etching protection type structure, and this structural principle is: on oxide semiconductor active layer 4a, be coated with one deck etch-protecting layer 10, and object is that protection oxide semiconductor active layer 4a is not damaged when carrying out source-drain electrode etching.In such an embodiment, prepared by the one mask plate technique that the graphical needs of etch-protecting layer 10 are extra, thus add the process time.
Summary of the invention
In view of this, the invention provides a kind of thin-film transistor array base-plate and preparation method thereof, display floater and display unit, the technological process of oxide semiconductor thin-film transistor array base palte can be shortened.
For solving the problems of the technologies described above, the invention provides a kind of thin-film transistor array base-plate, comprise underlay substrate and be arranged at gate electrode, gate insulation layer, active layer, source-drain electrode, data wire and the pixel electrode on underlay substrate, described active layer is oxide semiconductor active layer, described source-drain electrode, data wire and pixel electrode are arranged with material with layer, and described source-drain electrode directly contacts with described active layer.
Preferably, described source-drain electrode, data wire and pixel electrode adopt the electric conducting material being applicable to dry etching to make.
Preferably, described source-drain electrode, data wire and pixel electrode adopt Graphene or carbon nano-tube material to make.
Preferably, described thin-film transistor array base-plate also comprises:
Passivation layer, described passivation layer does not cover described pixel electrode.
The present invention also provides a kind of preparation method of thin-film transistor array base-plate, comprising:
Underlay substrate is formed with active layer, and described active layer is oxide semiconductor active layer;
On described active layer, formed the figure of source-drain electrode, data wire and pixel electrode by patterning processes, wherein, described source-drain electrode directly contacts with described active layer.
Preferably, the described step forming the figure of source-drain electrode, data wire and pixel electrode by patterning processes on described active layer comprises:
Form source and drain material layer film;
Described source and drain material layer film applies photoresist;
Exposure imaging is carried out to described photoresist, the formation complete reserve area of photoresist and photoresist remove region completely, wherein, the corresponding source-drain electrode of the complete reserve area of described photoresist, data wire and pixel electrode graphics field, other regions corresponding, region removed completely by described photoresist;
Dry etch process is adopted to etch away the complete region-wide source and drain material layer film of described photoresist;
Stripping photoresist, forms the figure of source-drain electrode, data wire and pixel electrode.
Preferably, described source-drain electrode, data wire and pixel electrode adopt the electric conducting material being applicable to dry etching to make.
Preferably, described source-drain electrode, data wire and pixel electrode adopt Graphene or carbon nano-tube material to make.
Preferably, described on underlay substrate, be formed with the step of active layer before also comprise:
Described underlay substrate is formed gate electrode and gate insulation layer;
Wherein, described on described active layer, form the step of the figure of source-drain electrode, data wire and pixel electrode by a patterning processes after also comprise:
Form passivation layer figure, described passivation layer figure does not cover described pixel electrode area.
The present invention also provides a kind of display floater, comprises above-mentioned thin-film transistor array base-plate.
The present invention also provides a kind of display unit, comprises above-mentioned display floater.
The beneficial effect of technique scheme of the present invention is as follows:
Because the source electrode of oxide semiconductor thin-film transistor array base palte, drain electrode, data wire and pixel electrode are arranged with material with layer, formed by a patterning processes, thus the technological process of oxide semiconductor thin-film transistor array base palte can be shortened, enhance productivity, save production cost.
Accompanying drawing explanation
Fig. 1 is the structural representation of existing oxide semiconductor thin-film transistor array base palte;
Fig. 2 is the structural representation of the thin-film transistor array base-plate of the embodiment of the present invention;
Fig. 2-1 to Fig. 2-5 is the schematic flow sheet of the preparation method of the thin-film transistor of the embodiment of the present invention.
Description of reference numerals:
Fig. 1:
Underlay substrate 1; Gate electrode 2a; Gate insulation layer 3; Active layer 4a; Etching barrier layer 10; Source electrode 5a; Drain electrode 5b; Passivation layer 8; Pixel electrode 9a.
Fig. 2-Fig. 2-5:
Underlay substrate 1; Gate electrode 2a; Gate insulation layer 3; Active layer 4a; Source electrode 5a; Drain electrode 5b; Pixel electrode 5c; Passivation layer 6.
Embodiment
For making the technical problem to be solved in the present invention, technical scheme and advantage clearly, be described in detail below in conjunction with the accompanying drawings and the specific embodiments.
Please refer to Fig. 2, Fig. 2 is the structural representation of the thin-film transistor array base-plate of the embodiment of the present invention, this thin-film transistor array base-plate comprises: underlay substrate 1 and the gate electrode 2a be arranged on underlay substrate 1, gate insulation layer 3, active layer 4a, source electrode 5a, drain electrode 5b, data wire (scheming not shown), pixel electrode 5c and passivation layer 6, described active layer 4a is oxide semiconductor active layer, described source electrode 5a, drain electrode 5b, data wire and pixel electrode 5c are arranged with material with layer, and described source electrode 5a, drain electrode 5b directly contacts with described active layer 4a, described passivation layer 6 does not cover described pixel electrode 5c.
Because described source electrode 5a, drain electrode 5b, data wire and pixel electrode 5c are arranged with material with layer, formed by a patterning processes, thus can shorten the technological process of oxide semiconductor thin-film transistor array base palte, enhance productivity, save production cost.
Preferably, the source electrode 5a in above-described embodiment, drain electrode 5b, data wire and pixel electrode 5c adopt the electric conducting material being applicable to dry etching to make.Thus, in the embodiment of the present invention, when making source electrode 5a, drain electrode 5b, data wire and pixel electrode 5c, dry etch process can be adopted to etch, dry etch process can not be damaged to oxide semiconductor active layer 4a, then do not need on active layer 4a to arrange etching barrier layer, thus further save one mask plate technique.
Preferably, described source electrode 5a, drain electrode 5b, data wire and pixel electrode 5c adopt Graphene or carbon nano-tube material to make.
Graphene or carbon nano-tube material have the following advantages:
1) can conduct electricity, and there is pliability, can be applicable to flexible oxide semiconductor thin-film transistor array base palte.
2) transparent, do not affect printing opacity.
3) dry etch process can be adopted to etch.
Certainly, the existing material that other have above-mentioned feature all can be used for the making of source electrode 5a, drain electrode 5b, data wire and the pixel electrode 5c made in the present embodiment.
Thin-film transistor array base-plate in the embodiment of the present invention can have flexible thin film transistor array substrate, certainly, also can be inflexibility thin-film transistor array base-plate.
The embodiment of the present invention also provides a kind of display floater, comprises above-mentioned thin-film transistor array base-plate.Described display floater can be display panels, organic EL display panel or inorganic EL display floater.
The embodiment of the present invention also provides a kind of display unit, comprises above-mentioned display floater.
The embodiment of the present invention also provides a kind of preparation method of thin-film transistor array base-plate, said method comprising the steps of:
Step S11: be formed with active layer on underlay substrate, described active layer is oxide semiconductor active layer;
Step S12: the figure being formed source-drain electrode, data wire and pixel electrode by patterning processes on described active layer, wherein, described source-drain electrode directly contacts with described active layer.
Because described source electrode, drain electrode, data wire and pixel electrode are arranged with material with layer, formed by a patterning processes, thus can shorten the technological process of oxide semiconductor thin-film transistor array base palte, enhance productivity, save production cost.
Preferably, the described step forming the figure of source-drain electrode, data wire and pixel electrode by patterning processes on described active layer comprises:
Step S121: form source and drain material layer film;
Step S122: apply photoresist on described source and drain material layer film;
Step S123: exposure imaging is carried out to described photoresist, the formation complete reserve area of photoresist and photoresist remove region completely, wherein, the corresponding source-drain electrode of the complete reserve area of described photoresist, data wire and pixel electrode graphics field, other regions corresponding, region removed completely by described photoresist;
Step S124: adopt dry etch process to etch away the complete region-wide source and drain material layer film of described photoresist;
Step S125: stripping photoresist, forms the figure of source-drain electrode, data wire and pixel electrode.
Preferably, described source-drain electrode, data wire and pixel electrode adopt the electric conducting material being applicable to dry etching to make.Thus, in the embodiment of the present invention, when making source electrode, drain electrode, data wire and pixel electrode, dry etch process can be adopted to etch, dry etch process can not be damaged to oxide semiconductor active layer, active layer does not then need to arrange etching barrier layer, thus further saves one mask plate technique.
Preferably, described source-drain electrode, data wire and pixel electrode adopt Graphene or carbon nano-tube material to make.
Please refer to the schematic flow sheet that Fig. 2-1 to Fig. 2-5, Fig. 2-1 to Fig. 2-5 is the preparation method of the thin-film transistor of the embodiment of the present invention, described manufacture method comprises the following steps:
Step S21: form gate electrode 2a on underlay substrate 1.
Described underlay substrate 1 can be flexible base, board, also can be non-flexible substrate.When underlay substrate 1 is flexible base, board, the materials such as PET (PETG), PEN (PEN), PC (Merlon), PES (polyethersulfone resin), PI (polyimides) can be adopted to make.
The step forming gate electrode 2a can specifically comprise: utilize Sputter (sputtering) process deposits one deck gate electrode metal film, thickness is
material can be the metals such as Mo (molybdenum), Al (aluminium), Cu (copper), W (tungsten), or the composite film of several metal, then utilize mask plate technology to carry out graphically, thus form the grid metal level comprising the figure such as gate electrode 2a and grid line (scheming not shown).
Step S22: form gate insulation layer 3 on the underlay substrate 1 being formed with gate electrode 2a.
Concrete, PECVD (plasma enhanced chemical vapor deposition method) can be utilized to deposit one deck gate insulation layer, and thickness is
material can be the monofilm of SiNx (silicon nitride) or SiOx (silica), or the compound of SiNx and SiOx, corresponding reacting gas can be the mist of SiH4 (silane), NH3 (ammonia) and N2 (nitrogen), or SiH2Cl2 (dichlorosilane), NH3 and N2 mist.
In addition, gate insulation layer 3 also can replace with photosensitive insulating resin.
Step S23: be formed with active layer 4a on the underlay substrate 1 being formed with gate insulation layer 3.
Concrete, can utilize Sputter process deposits layer of metal oxide semiconductor film, thickness is
material can be the metal oxide such as IGZO (indium gallium zinc oxide) or ITZO (indium tin zinc oxide), or the composite membrane of several metal oxide.Then utilize mask plate technology to carry out graphically, thus form the figure of oxide semiconductor active layer 4a.
Step S24: on the underlay substrate 1 being formed with active layer 4a, the figure of source electrode 5a, drain electrode 5b, data wire (scheming not shown) and pixel electrode 5c is formed by patterning processes, wherein, described source electrode 5a directly contacts with described active layer 4a with drain electrode 5b.
Concrete, please refer to Fig. 2-3, can above the figure of active layer 4a, utilize plasma enhanced chemical vapor deposition method to deposit a layer graphene or carbon nano-tube material, or be coated with the water-soluble individual layer of one deck or multi-layer graphene or carbon nano-tube material, form source and drain material layer film 5.
Please refer to Fig. 2-4, then above described source and drain material layer film 5, photoresist is applied, and exposure imaging is carried out to described photoresist, the formation complete reserve area of photoresist and photoresist remove region completely, wherein, the corresponding source-drain electrode of the complete reserve area of described photoresist, data wire and pixel electrode graphics field, other regions corresponding, region removed completely by described photoresist;
Then, the gas such as O2 (oxygen) or Ar (argon gas) is utilized to carry out dry etching to source and drain material layer film 5, get rid of photoresist and remove Graphene in region or carbon nano-tube material completely, and stripping photoresist, form the figure of source electrode 5a, drain electrode 5b, data wire and pixel electrode 5c.
Step S25: the figure forming passivation layer 6, the figure of described passivation layer 6 does not cover described pixel electrode area.
Concrete, PECVD can be utilized to deposit one deck passivation layer, and thickness is
material can select SiNx, SiOx or its compound etc., then carry out exposing, developing, carry out dry etching, etch away the passivation layer above pixel electrode area and peripheral circuit region (as gate electrode external circuits region, source-drain electrode external circuits region etc.), the final figure forming passivation layer 6.
In addition, passivation layer 6 also can replace with photosensitive insulating resin.
The above is the preferred embodiment of the present invention; it should be pointed out that for those skilled in the art, under the prerequisite not departing from principle of the present invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.
Claims (11)
1. a thin-film transistor array base-plate, comprise underlay substrate and be arranged at gate electrode, gate insulation layer, active layer, source-drain electrode, data wire and the pixel electrode on underlay substrate, described active layer is oxide semiconductor active layer, it is characterized in that, described source-drain electrode, data wire and pixel electrode are arranged with material with layer, and described source-drain electrode directly contacts with described active layer.
2. thin-film transistor array base-plate according to claim 1, is characterized in that, described source-drain electrode, data wire and pixel electrode adopt the electric conducting material being applicable to dry etching to make.
3. thin-film transistor array base-plate according to claim 2, is characterized in that, described source-drain electrode, data wire and pixel electrode adopt Graphene or carbon nano-tube material to make.
4. the thin-film transistor array base-plate according to any one of claim 1-3, is characterized in that, also comprises:
Passivation layer, described passivation layer does not cover described pixel electrode.
5. a preparation method for thin-film transistor array base-plate, is characterized in that, comprising:
Underlay substrate is formed with active layer, and described active layer is oxide semiconductor active layer;
On described active layer, formed the figure of source-drain electrode, data wire and pixel electrode by patterning processes, wherein, described source-drain electrode directly contacts with described active layer.
6. preparation method according to claim 5, is characterized in that, the described step forming the figure of source-drain electrode, data wire and pixel electrode by patterning processes on described active layer comprises:
Form source and drain material layer film;
Described source and drain material layer film applies photoresist;
Exposure imaging is carried out to described photoresist, the formation complete reserve area of photoresist and photoresist remove region completely, wherein, the corresponding source-drain electrode of the complete reserve area of described photoresist, data wire and pixel electrode graphics field, other regions corresponding, region removed completely by described photoresist;
Dry etch process is adopted to etch away the complete region-wide source and drain material layer film of described photoresist;
Stripping photoresist, forms the figure of source-drain electrode, data wire and pixel electrode.
7. preparation method according to claim 6, is characterized in that, described source-drain electrode, data wire and pixel electrode adopt the electric conducting material being applicable to dry etching to make.
8. preparation method according to claim 7, is characterized in that, described source-drain electrode, data wire and pixel electrode adopt Graphene or carbon nano-tube material to make.
9. preparation method according to claim 5, is characterized in that, described on underlay substrate, be formed with the step of active layer before also comprise:
Described underlay substrate is formed gate electrode and gate insulation layer;
Wherein, described on described active layer, form the step of the figure of source-drain electrode, data wire and pixel electrode by a patterning processes after also comprise:
Form passivation layer figure, described passivation layer figure does not cover described pixel electrode area.
10. a display floater, is characterized in that, comprises the thin-film transistor array base-plate as described in any one of claim 1-4.
11. 1 kinds of display unit, is characterized in that, comprise display floater as claimed in claim 10.
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| CN108054103A (en) * | 2017-12-13 | 2018-05-18 | 合肥鑫晟光电科技有限公司 | Display base plate and its manufacturing method, display device |
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| CN110161761A (en) * | 2019-05-10 | 2019-08-23 | 香港科技大学 | Liquid crystal display panel and preparation method thereof and display equipment |
| WO2021238481A1 (en) * | 2020-05-28 | 2021-12-02 | 京东方科技集团股份有限公司 | Oled display substrate and manufacturing method therefor, and display apparatus |
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