CN107994775A - Self-adaptive dead-time control circuit for dc-dc - Google Patents
Self-adaptive dead-time control circuit for dc-dc Download PDFInfo
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- CN107994775A CN107994775A CN201711450696.8A CN201711450696A CN107994775A CN 107994775 A CN107994775 A CN 107994775A CN 201711450696 A CN201711450696 A CN 201711450696A CN 107994775 A CN107994775 A CN 107994775A
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
- H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
Abstract
The present invention relates to a kind of self-adaptive dead-time control circuit for DC DC converters, which includes：Sub-circuit 11 is detected, control signal is produced for the voltage according to end to be detected in sub-circuit to be controlled；Be delayed sub-circuit 12, the detection sub-circuit 11 is electrically connected, for producing the non-overlapping clock signal adaptive with the dead time of the power tube in the sub-circuit to be controlled according to the control signal and modulated signal.Provided by the present invention for the self-adaptive dead-time control circuit of DC DC converters, adaptive adjustment dead time can be produced according to different load currents, different input voltages, so as to avoid DC DC converter dead times it is too short caused by loss of efficiency, and reduce dead time excessive in DC DC converters and bring power consumption penalty, improve the overall transformation efficiency of DC DC converters.
Description
Technical field
The invention belongs to microelectronics technology, more particularly to a kind of adaptive dead zone time for dc-dc
Control circuit.
Background technology
The conducting of power tube in dc-dc and terminate in that there are PMOS there are non-ideal effects in transfer process
The state that pipe and NMOS tube simultaneously turn on.In this case, there are path between power supply and ground, so as to result in very big energy
Loss, reduces the transfer efficiency of converter.Therefore, we, which introduce dead time, prevents PMOS tube and NMOS tube from simultaneously turning on.
Meanwhile dead time is long or the too short transfer efficiency that can all influence whole converter.
Traditional converter uses fixed dead time, and in order to which under any circumstance, PMOS tube and NMOS tube are all
It will not simultaneously turn on, this fixation dead time is often configured long.This long dead time can reduce converter
Efficiency.Preferable dead time and the parasitic capacitance of end SW to be detected, converter input voltage Vin and load current
Iload is related.
Therefore, how to control effectively to the dead time of the power tube in dc-dc just becomes of crucial importance.
The content of the invention
In order to solve the above-mentioned technical problem, the present invention proposes that one kind can be reduced in dc-dc due to dead time
The control circuit of the adaptive dead zone time of long or too short caused energy loss problem.
Specifically, An embodiment provides a kind of adaptive dead zone time control for dc-dc
Circuit processed.The control circuit 10 includes：
Sub-circuit 11 is detected, control signal is produced for the voltage according to end to be detected in sub-circuit to be controlled；
Be delayed sub-circuit 12, the detection sub-circuit 11 is electrically connected, for according to the control signal and modulated signal production
The non-overlapping clock signal of the dead time of the raw power tube with the sub-circuit to be controlled adaptively.
In one embodiment of the invention, the detection sub-circuit 11 includes：It is d type flip flop D_TRIGER, first anti-phase
Device INV1, the second phase inverter INV2, the 3rd phase inverter INV3, first resistor R1, the first capacitance C1, the first PMOS tube PM1, second
PMOS tube PM2 and the first NMOS tube NM1；Wherein,
The first PMOS tube PM1 and the first capacitance C1 are sequentially connected in series between end SW to be detected and ground terminal GND；
The first NMOS tube NM1 and the first resistor R1 be sequentially connected in series drain electrode in the first PMOS tube PM1 with
Between the ground terminal GND；
The grid of the first PMOS tube PM1 is electrically connected the output end vo ut, the first PMOS of the dc-dc
The substrate of pipe PM1 is connected with the source electrode and substrate of the second PMOS tube PM2；
The drain electrode of the second PMOS tube PM2 is connected with the grid of the first PMOS tube PM1, second PMOS tube
The grid of PM2 is electrically connected first control signal end Vctrl1；
The grid of the first NMOS tube NM1 is electrically connected second control signal end Vctrl2；
The first phase inverter INV1 and the second phase inverter INV2 is sequentially connected in series in the leakage of the first PMOS tube PM1
Between the input end of clock of pole and the d type flip flop D_TRIGER；
The SD that the 3rd phase inverter INV3 is electrically connected to the modulated signal end PWM and d type flip flop D_TRIGER is inputted
Between end；
The RD input terminals of the d type flip flop D_TRIGER are electrically connected output end vo ut, the D input of the dc-dc
End is electrically connected the ground terminal GND；
Output terminal of the Q output of the d type flip flop D_TRIGER as the detection sub-circuit 11.
In one embodiment of the invention, the delay sub-circuit 12 includes：4th phase inverter INV4, the 5th phase inverter
INV5, hex inverter INV6, the 7th phase inverter INV7, the 8th phase inverter INV8, the first delay unit DELAY1, the second delay
Cells D ELAY2, the first NAND gate NAND1, the second NAND gate NAND2 and nor gate NOR1；Wherein,
The nor gate NOR1, the 4th phase inverter INV4, the first NAND gate NAND1 and the 5th phase inverter
INV5 is serially electrically connected successively, and the second input terminal of the first NAND gate NAND1 is electrically connected the d type flip flop D_TRIGER's
Q output；
The second NAND gate NAND2, the hex inverter INV6, the 7th phase inverter INV7 and described 8th anti-
Phase device INV8 is serially electrically connected successively；
The first input end of the nor gate NOR1 is electrically connected institute with the first input end of the second NAND gate NAND2
State modulated signal end PWM；
The second input terminal of the nor gate NOR1 is anti-phase through the second delay unit DELAY2 electrical connections the described 8th
The output terminal of device INV8；
The second input terminal of the second NAND gate NAND2 is electrically connected the described 5th through the first delay unit DELAY1
The output terminal of phase inverter INV5；
The output terminal of the output terminal and the 8th phase inverter INV8 of the 5th phase inverter INV5 prolongs respectively as described
When sub-circuit 12 the first output terminal and the second output terminal.
In one embodiment of the invention, the first delay unit DELAY1 includes：3rd PMOS tube PM3, the 9th
Phase inverter INV9, the tenth phase inverter INV10, the 11st phase inverter INV11, the 12nd phase inverter INV12, the 13rd phase inverter
INV13, second resistance R2 and the second capacitance C2；Wherein,
It is the 9th phase inverter INV9, the tenth phase inverter INV10, the second resistance R2, the described 11st anti-phase
Device INV11, the 12nd phase inverter INV12 and the 13rd phase inverter INV13 are serially electrically connected successively, and the described 9th is anti-
The input terminal of phase device INV9 is electrically connected the ground terminal GND；
The 3rd PMOS tube PM3 and the second capacitance C2 is sequentially connected in series in the output terminal of the dc-dc
Between Vout and the ground terminal GND；
The grid of the 3rd PMOS tube PM3 is electrically connected the output terminal of the 5th phase inverter INV5, the 3rd PMOS
The drain electrode of pipe PM3 is electrically connected the input terminal of the 11st phase inverter INV11；
Output terminal of the output terminal of the 13rd phase inverter INV13 as the first delay unit DELAY1.
In one embodiment of the invention, the second delay unit DELAY2 includes：Second NMOS tube NM2, the tenth
Four phase inverter INV14, the 15th phase inverter INV15, the tenth hex inverter INV16, the 17th phase inverter INV17, eighteen incompatibilities
Phase device INV18, the 19th phase inverter INV19,3rd resistor R3 and the 3rd capacitance C3；Wherein,
The 14th phase inverter INV14, the 15th phase inverter INV15, the tenth hex inverter INV16, institute
State 3rd resistor R3, the 17th phase inverter INV17, the eighteen incompatibilities phase device INV18 and the 19th phase inverter INV19 according to
Secondary serial electrical connection, the input terminal of the 14th phase inverter INV14 are electrically connected the ground terminal GND；
The second NMOS tube NM2 is electrically connected to the defeated of the 17th phase inverter INV17 with the 3rd capacitance C3
Enter between end and the ground terminal GND；
The grid of the second NMOS tube NM2 is electrically connected the output terminal of the 8th phase inverter INV8；
Output terminal of the output terminal of the 19th phase inverter INV19 as the second delay unit DELAY2.
Compared with prior art, the present invention at least has the advantages that：
Provided by the present invention for the self-adaptive dead-time control circuit of dc-dc, can be born according to different
Electric current, the different adaptive adjustment dead times of input voltage generation are carried, is made so as to avoid dc-dc dead time is too short
Into loss of efficiency, and reduce dead time excessive in dc-dc and bring power consumption penalty, improve DC-DC and turn
The overall transformation efficiency of parallel operation.
Brief description of the drawings
Below in conjunction with attached drawing, the embodiment of the present invention is described in detail.
Fig. 1 is a kind of self-adaptive dead-time control circuit for dc-dc provided in an embodiment of the present invention
Structure diagram；
Fig. 2 is a kind of structure diagram for detecting sub-circuit provided in an embodiment of the present invention；
Fig. 3 is a kind of structure diagram of sub-circuit that is delayed provided in an embodiment of the present invention；
Fig. 4 is a kind of structure diagram of first delay unit DELAY1 provided in an embodiment of the present invention；
Fig. 5 is a kind of structure diagram of second delay unit DELAY2 provided in an embodiment of the present invention；
Fig. 6 is a kind of local circuit structure diagram of dc-dc provided in an embodiment of the present invention；
Simulation waveform when Fig. 7 is input voltage vin=0.9V, load current Iload=1mA in the embodiment of the present invention
Figure；
Simulation waveform when Fig. 8 is input voltage vin=1.6V, load current Iload=100mA in the embodiment of the present invention
Figure；
Fig. 9 is applied to for self-adaptive dead-time control circuit provided by the invention with constant dead-time control circuit
Transfer efficiency simulation curve figure during BOOST converters under different loads electric current.
Embodiment
Below in conjunction with the attached drawing in the embodiment of the present invention, the technical solution in the embodiment of the present invention is carried out clear, complete
Site preparation describes, it is clear that described embodiment is only part of the embodiment of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, those of ordinary skill in the art are obtained every other without creative efforts
Embodiment, belongs to the scope of protection of the invention.
The present invention is described in further details below in conjunction with the accompanying drawings.
Embodiment one
Fig. 1 is referred to, Fig. 1 is a kind of adaptive dead zone time for dc-dc provided in an embodiment of the present invention
The structure diagram of control circuit.The control circuit 10 includes：
Sub-circuit 11 is detected, control signal is produced for the voltage according to end to be detected in sub-circuit to be controlled；
Be delayed sub-circuit 12, the detection sub-circuit 11 is electrically connected, for according to the control signal and modulated signal production
The non-overlapping clock signal of the dead time of the raw power tube with the sub-circuit to be controlled adaptively.
Further, Fig. 2 is referred to, Fig. 2 is a kind of structure diagram for detecting sub-circuit provided in an embodiment of the present invention.
The detection sub-circuit 11 includes：D type flip flop D_TRIGER, the first phase inverter INV1, the second phase inverter INV2, the 3rd phase inverter
INV3, first resistor R1, the first capacitance C1, the first PMOS tube PM1, the second PMOS tube PM2 and the first NMOS tube NM1；Wherein,
The first PMOS tube PM1 and the first capacitance C1 are sequentially connected in series between end SW to be detected and ground terminal GND；
The first NMOS tube NM1 and the first resistor R1 be sequentially connected in series drain electrode in the first PMOS tube PM1 with
Between the ground terminal GND；
The grid of the first PMOS tube PM1 is electrically connected the output end vo ut, the first PMOS of the dc-dc
The substrate of pipe PM1 is connected with the source electrode and substrate of the second PMOS tube PM2；
The drain electrode of the second PMOS tube PM2 is connected with the grid of the first PMOS tube PM1, second PMOS tube
The grid of PM2 is electrically connected first control signal end Vctrl1；
The grid of the first NMOS tube NM1 is electrically connected second control signal end Vctrl2；
The first phase inverter INV1 and the second phase inverter INV2 is sequentially connected in series in the leakage of the first PMOS tube PM1
Between the input end of clock of pole and the d type flip flop D_TRIGER；
The SD that the 3rd phase inverter INV3 is electrically connected to the modulated signal end PWM and d type flip flop D_TRIGER is inputted
Between end；
The RD input terminals of the d type flip flop D_TRIGER are electrically connected output end vo ut, the D input of the dc-dc
End is electrically connected the ground terminal GND；
Output terminal output threeth control of the D output terminals of the d type flip flop D_TRIGER as the detection sub-circuit 11
Signal Vctrl3.
Further, Fig. 3 is referred to, Fig. 3 is a kind of structure diagram of sub-circuit that is delayed provided in an embodiment of the present invention；
The delay sub-circuit 12 includes：4th phase inverter INV4, the 5th phase inverter INV5, hex inverter INV6, the 7th phase inverter
INV7, the 8th phase inverter INV8, the first delay unit DELAY1, the second delay unit DELAY2, the first NAND gate NAND1,
Two NAND gate NAND2 and nor gate NOR1；Wherein,
The nor gate NOR1, the 4th phase inverter INV4, the first NAND gate NAND1 and the 5th phase inverter
INV5 is serially electrically connected successively, and the second input terminal of the first NAND gate NAND1 is electrically connected the d type flip flop D_TRIGER's
Q output；
The second NAND gate NAND2, the hex inverter INV6, the 7th phase inverter INV7 and described 8th anti-
Phase device INV8 is serially electrically connected successively；
The first input end of the nor gate NOR1 is electrically connected institute with the first input end of the second NAND gate NAND2
State modulated signal end PWM；
The second input terminal of the nor gate NOR1 is anti-phase through the second delay unit DELAY2 electrical connections the described 8th
The output terminal of device INV8；
The second input terminal of the second NAND gate NAND2 is electrically connected the described 5th through the first delay unit DELAY1
The output terminal of phase inverter INV5；
The output terminal of the output terminal and the 8th phase inverter INV8 of the 5th phase inverter INV5 prolongs respectively as described
When sub-circuit 12 the first output terminal and the second output terminal, and export the first non-overlapping clock signal P_DRIVE and respectively
Two clock signal N_DRIVE.
Further, Fig. 4 is referred to, Fig. 4 is a kind of knot of first delay unit DELAY1 provided in an embodiment of the present invention
Structure schematic diagram；First delay unit DELAY1 includes：3rd PMOS tube PM3, the 9th phase inverter INV9, the tenth phase inverter
INV10, the 11st phase inverter INV11, the 12nd phase inverter INV12, the 13rd phase inverter INV13, second resistance R2 and second
Capacitance C2；Wherein,
It is the 9th phase inverter INV9, the tenth phase inverter INV10, the second resistance R2, the described 11st anti-phase
Device INV11, the 12nd phase inverter INV12 and the 13rd phase inverter INV13 are serially electrically connected successively, and the described 9th is anti-
The input terminal of phase device INV9 is electrically connected the ground terminal GND；
The 3rd PMOS tube PM3 and the second capacitance C2 is sequentially connected in series in the output terminal of the dc-dc
Between Vout and the ground terminal GND；
The grid of the 3rd PMOS tube PM3 is electrically connected the output terminal of the 5th phase inverter INV5, the 3rd PMOS
The drain electrode of pipe PM3 is electrically connected the input terminal of the 11st phase inverter INV11；
Output terminal of the output terminal of the 13rd phase inverter INV13 as the first delay unit DELAY1.
Further, Fig. 5 is referred to, Fig. 5 is a kind of knot of second delay unit DELAY2 provided in an embodiment of the present invention
Structure schematic diagram；Second delay unit DELAY2 includes：It is second NMOS tube NM2, the 14th phase inverter INV14, the 15th anti-phase
Device INV15, the tenth hex inverter INV16, the 17th phase inverter INV17, eighteen incompatibilities phase device INV18, the 19th phase inverter
INV19,3rd resistor R3 and the 3rd capacitance C3；Wherein,
The 14th phase inverter INV14, the 15th phase inverter INV15, the tenth hex inverter INV16, institute
State 3rd resistor R3, the 17th phase inverter INV17, the eighteen incompatibilities phase device INV18 and the 19th phase inverter INV19 according to
Secondary serial electrical connection, the input terminal of the 14th phase inverter INV14 are electrically connected the ground terminal GND；
The second NMOS tube NM2 is electrically connected to the defeated of the 17th phase inverter INV17 with the 3rd capacitance C3
Enter between end and the ground terminal GND；
The grid of the second NMOS tube NM2 is electrically connected the output terminal of the 8th phase inverter INV8；
Output terminal of the output terminal of the 19th phase inverter INV19 as the second delay unit DELAY2.
Self-adaptive dead-time control circuit provided in this embodiment for dc-dc, can be according to different
Load current, different input voltages produce adaptive adjustment dead time, too short so as to avoid dc-dc dead time
Caused by loss of efficiency, and reduce dead time excessive in dc-dc and bring power consumption penalty, improve DC-DC
The overall transformation efficiency of converter.
Embodiment two
The principle of the present invention and implementation are described in detail with reference to specific application circuit.
Specifically, referring to Fig. 6, Fig. 6 is a kind of local circuit structure of dc-dc provided in an embodiment of the present invention
Schematic diagram；In the circuit structure, including detection sub-circuit and delay sub-circuit as described in embodiment one, further include to be controlled
System circuit and logic controller；
Specifically, sub-circuit to be controlled includes：Inductance L, the 4th PMOS tube PM4, the 3rd NMOS tube NM3, the first driver
DRIVE1, the second driver DRIVE2, the 4th capacitance C4, the 4th resistance R4, the 5th resistance R5 and load resistance Rout；Wherein,
The inductance L, the 4th PMOS tube PM4 and load resistance Rout are sequentially connected in series in the Input voltage terminal Vin with connecing
Between ground terminal GND；
The 3rd NMOS tube NM3 is electrically connected between the source electrode and ground terminal GND of the 4th PMOS tube PM4；
4th capacitance C4 is electrically connected between drain electrode and the ground terminal GND of the 4th PMOS tube PM4；
4th resistance R4 and the 5th resistance R5 are serially connected between drain electrode and the ground terminal GND of the 4th PMOS tube PM4；
The source electrode of 4th PMOS tube PM4 is connected with the source electrode of the first PMOS tube PM1 in detection sub-circuit；4th PMOS tube
The grid of PM4 is electrically connected the output terminal of the 5th phase inverter INV5 through the second driver DRIVE2；
The grid of 3rd NMOS tube NM3 is electrically connected the output terminal of the 8th phase inverter INV8 through the first driver DRIVE1.
The first input end of logic controller is electrically connected to the 4th resistance R4 and is concatenated with the 5th resistance R5 at the node to be formed,
Second input terminal of logic controller is electrically connected reference voltage end Vref, the first output terminal of logic controller, the second output terminal,
3rd output terminal is respectively as first control signal end Vctrl1, second control signal end Vctrl2, modulated signal end PWM；Its
In, the first input end of modulated signal end PWM AND OR NOT gates NOR1 and the first input end of the second NAND gate NAND2 are electrically connected
Connect.
The principle of the present invention and implementation are illustrated with reference to Fig. 6.It is specific as follows：
Logic controller produces modulated signal PWM according to the voltage of the 5th resistance R5.Modulated signal PWM can be input to delay
In sub-circuit.The the first delay unit DELAY1 and the second delay unit DELAY2 being delayed in sub-circuit produce two fixations
Delay, and produce delay it is longer, in any condition, can to avoid the 4th PMOS tube PM4 in sub-circuit to be controlled with
3rd NMOS tube NM3 is simultaneously turned on.Detection sub-circuit can be beaten in advance in delay caused by the second delay unit DELAY2
The 4th PMOS tube PM4 is opened, so as to fulfill adaptive dead time.
When the modulated signal of modulated signal end PWM outputs is from high to low, second clock signal N_DRIVE is changed into low, then
3rd NMOS tube NM3 is closed.If the 3rd control signal Vctrl3 is high level always, the first clock signal P_DRIVE
Need just be changed into low potential after the constant time lag that the second delay unit DELAY2 is produced, at this time the 4th PMOS tube
PM4 is opened.But when long dead time occurs, then end SW (source electrode of the 4th PMOS tube PM4) current potential to be detected will
Rise, after an output voltage Vout high diode voltage of the SW voltages in end to be detected than load resistance Rout, detects son electricity
The first PMOS tube PM1 conductings in road, then the voltage on the first capacitance C1 can raise, while the output of the second phase inverter INV2
Holding the voltage of SW_D also can and then raise.When the voltage signal rising edge of the output terminal SW_D of the second phase inverter INV2 acts on D
During the input end of clock CLK of trigger, the output signal of the Q output of d type flip flop will be changed into low from height, i.e., described 3rd control
Vctrl3 signals processed are changed into low, then the first clock signal P_DRIVE is directly changed into low, and the 4th PMOS tube PM4 need not at this time
Opened in advance by the second delay unit DELAY2 constant time lags produced.When this process realizes adaptive dead band
Between.
Fig. 7 is referred to, when Fig. 7 is input voltage vin=0.9V, load current Iload=1mA in the embodiment of the present invention
Simulation waveform.It will be apparent from this figure that when input voltage vin=0.9V, load current Iload=1mA, dead time is
5.2ns。
Fig. 8 is referred to, when Fig. 8 is input voltage vin=1.6V, load current Iload=100mA in the embodiment of the present invention
Simulation waveform.It will be apparent from this figure that when input voltage vin=1.6V, load current Iload=100mA, during dead band
Between be 1.4ns.
Fig. 9 is referred to, Fig. 9 is self-adaptive dead-time control circuit provided by the invention and fixed Power MOSFET electricity
Transfer efficiency simulation curve figure when road is applied to BOOST converters under different loads electric current.It will be apparent from this figure that
Under different load currents, when self-adaptive dead-time control circuit is applied to BOOST converters, the transfer efficiency of converter
Substantially significantly it is higher than transfer efficiency when constant dead-time control circuit to be applied to BOOST converters.
To sum up, specific case used herein is set forth the structure and embodiment of the present invention, and the above is implemented
The explanation of example is only intended to help the method and its core concept for understanding the present invention；Meanwhile for the general technology people of this area
Member, according to the thought of the present invention, there will be changes in specific embodiments and applications, to sum up, in this specification
Appearance should not be construed as limiting the invention, and protection scope of the present invention should be subject to appended claim.
Claims (5)
- A kind of 1. self-adaptive dead-time control circuit (10) for dc-dc, it is characterised in that including：Sub-circuit (11) is detected, control signal is produced for the voltage according to end to be detected in sub-circuit to be controlled；Be delayed sub-circuit (12), is electrically connected the detection sub-circuit (11), for according to the control signal and modulated signal production The non-overlapping clock signal of the dead time of the raw power tube with the sub-circuit to be controlled adaptively.
- 2. control circuit (10) according to claim 1, it is characterised in that the detection sub-circuit (11) includes：D is triggered Device (D_TRIGER), the first phase inverter (INV1), the second phase inverter (INV2), the 3rd phase inverter (INV3), first resistor (R1), First capacitance (C1), the first PMOS tube (PM1), the second PMOS tube (PM2) and the first NMOS tube (NM1)；Wherein,First PMOS tube (PM1) is sequentially connected in series in end to be detected (SW) and ground terminal (GND) with first capacitance (C1) Between；First NMOS tube (NM1) is sequentially connected in series in the drain electrode of first PMOS tube (PM1) with the first resistor (R1) Between the ground terminal (GND)；The grid of first PMOS tube (PM1) is electrically connected the output terminal (Vout) of the dc-dc, the first PMOS The substrate of pipe (PM1) is connected with the source electrode and substrate of second PMOS tube (PM2)；The drain electrode of second PMOS tube (PM2) is connected with the grid of first PMOS tube (PM1), second PMOS tube (PM2) grid is electrically connected first control signal end (Vctrl1)；The grid of first NMOS tube (NM1) is electrically connected second control signal end (Vctrl2)；First phase inverter (INV1) is sequentially connected in series in first PMOS tube (PM1) with second phase inverter (INV2) Between drain electrode and the input end of clock of the d type flip flop (D_TRIGER)；3rd phase inverter (INV3) is electrically connected to modulated signal end (PWM) and the SD of the d type flip flop (D_TRIGER) is defeated Enter between end；The RD input terminals of the d type flip flop (D_TRIGER) are electrically connected the output terminal (Vout) of the dc-dc, the D The D input terminals of trigger (D_TRIGER) are electrically connected the ground terminal (GND)；Output terminal of the Q output of the d type flip flop (D_TRIGER) as the detection sub-circuit (11).
- 3. control circuit (10) according to claim 2, it is characterised in that the delay sub-circuit (12) includes：4th Phase inverter (INV4), the 5th phase inverter (INV5), hex inverter (INV6), the 7th phase inverter (INV7), the 8th phase inverter (INV8), the first delay unit (DELAY1), the second delay unit (DELAY2), the first NAND gate (NAND1), the second NAND gate (NAND2) and nor gate (NOR1)；Wherein,The nor gate (NOR1), the 4th phase inverter (INV4), first NAND gate (NAND1) and described 5th anti-phase Device (INV5) is serial successively to be electrically connected, and the second input terminal of first NAND gate (NAND1) is electrically connected the d type flip flop (D_ TRIGER Q output)；Second NAND gate (NAND2), the hex inverter (INV6), the 7th phase inverter (INV7) and the described 8th Phase inverter (INV8) is serial successively to be electrically connected；The first input end of the nor gate (NOR1) is electrically connected institute with the first input end of second NAND gate (NAND2) State modulated signal end (PWM)；Second input terminal of the nor gate (NOR1) is anti-phase through second delay unit (DELAY2) electrical connection the described 8th The output terminal of device (INV8)；Second input terminal of second NAND gate (NAND2) is electrically connected the described 5th through first delay unit (DELAY1) The output terminal of phase inverter (INV5)；The output terminal and the output terminal of the 8th phase inverter (INV8) of 5th phase inverter (INV5) prolong respectively as described When sub-circuit (12) the first output terminal and the second output terminal.
- 4. control circuit (10) according to claim 3, it is characterised in that the first delay unit (DELAY1) bag Include：3rd PMOS tube (PM3), the 9th phase inverter (INV9), the tenth phase inverter (INV10), the 11st phase inverter (INV11), 12 phase inverters (INV12), the 13rd phase inverter (INV13), second resistance (R2) and the second capacitance (C2)；Wherein,It is 9th phase inverter (INV9), the tenth phase inverter (INV10), the second resistance (R2), the described 11st anti- Phase device (INV11), the 12nd phase inverter (INV12) and the 13rd phase inverter (INV13) are serial successively to be electrically connected, institute The input terminal for stating the 9th phase inverter (INV9) is electrically connected the ground terminal (GND)；3rd PMOS tube (PM3) is sequentially connected in series in the output terminal of the dc-dc with second capacitance (C2) (Vout) between the ground terminal (GND)；The grid of 3rd PMOS tube (PM3) is electrically connected the output terminal of the 5th phase inverter (INV5), the 3rd PMOS The drain electrode for managing (PM3) is electrically connected the input terminal of the 11st phase inverter (INV11)；Output terminal of the output terminal of 13rd phase inverter (INV13) as first delay unit (DELAY1).
- 5. control circuit (10) according to claim 3, it is characterised in that the second delay unit (DELAY2) bag Include：Second NMOS tube (NM2), the 14th phase inverter (INV14), the 15th phase inverter (INV15), the tenth hex inverter (INV16), the 17th phase inverter (INV17), eighteen incompatibilities phase device (INV18), the 19th phase inverter (INV19), 3rd resistor (R3) and the 3rd capacitance (C3)；Wherein,14th phase inverter (INV14), the 15th phase inverter (INV15), the tenth hex inverter (INV16), The 3rd resistor (R3), the 17th phase inverter (INV17), the eighteen incompatibilities phase device (INV18) and the 19th are anti-phase Device (INV19) is serial successively to be electrically connected, and the input terminal of the 14th phase inverter (INV14) is electrically connected the ground terminal (GND)；Second NMOS tube (NM2) is electrically connected to the 17th phase inverter (INV17) with the 3rd capacitance (C3) Between input terminal and the ground terminal (GND)；The grid of second NMOS tube (NM2) is electrically connected the output terminal of the 8th phase inverter (INV8)；Output terminal of the output terminal of 19th phase inverter (INV19) as second delay unit (DELAY2).
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