CN107994775B - Self-adaptive dead-time control circuit for DC-DC converter - Google Patents
Self-adaptive dead-time control circuit for DC-DC converter Download PDFInfo
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- CN107994775B CN107994775B CN201711450696.8A CN201711450696A CN107994775B CN 107994775 B CN107994775 B CN 107994775B CN 201711450696 A CN201711450696 A CN 201711450696A CN 107994775 B CN107994775 B CN 107994775B
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
- H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
Abstract
The present invention relates to a kind of self-adaptive dead-time control circuit for DC-DC converter, which includes: detection sub-circuit 11, for generating control signal according to the voltage at end to be detected in sub-circuit to be controlled；Be delayed sub-circuit 12, is electrically connected the detection sub-circuit 11, for generating the non-overlapping clock signal adaptive with the dead time of the power tube in the sub-circuit to be controlled according to the control signal and modulated signal.Provided by the present invention for the self-adaptive dead-time control circuit of DC-DC converter, adaptive adjustment dead time can be generated according to different load currents, different input voltages, so as to avoid DC-DC converter dead time it is too short caused by loss of efficiency, and reduce excessive dead time in DC-DC converter and bring power consumption penalty, improve the overall conversion efficiency of DC-DC converter.
Description
Technical field
The invention belongs to microelectronics technology, in particular to a kind of adaptive dead zone time for DC-DC converter
Control circuit.
Background technique
There are non-ideal effects in conversion process for the on and off of power tube in DC-DC converter, and there are PMOS
The state that pipe and NMOS tube simultaneously turn on.In this case, there are accesses between power supply and ground, so as to cause very big energy
Loss, reduces the transfer efficiency of converter.Therefore, we, which introduce dead time, prevents PMOS tube and NMOS tube from simultaneously turning on.
Meanwhile dead time is too long or the too short transfer efficiency that can all influence entire converter.
Traditional converter uses fixed dead time, and in order to which under any circumstance, PMOS tube and NMOS tube are all
It will not simultaneously turn on, this fixation dead time is often configured long.This too long dead time can reduce converter
Efficiency.The parasitic capacitance of ideal dead time and end SW to be detected, converter input voltage Vin and load current
Iload is related.
Therefore, how to control effectively to the dead time of the power tube in DC-DC converter just becomes of crucial importance.
Summary of the invention
In order to solve the above-mentioned technical problem, the present invention proposes that one kind can reduce in DC-DC converter due to dead time
The control circuit of the adaptive dead zone time of too long or too short caused energy loss problem.
Specifically, An embodiment provides a kind of adaptive dead zone time controls for DC-DC converter
Circuit processed.The control circuit 10 includes:
Sub-circuit 11 is detected, for generating control signal according to the voltage at end to be detected in sub-circuit to be controlled；
Be delayed sub-circuit 12, is electrically connected the detection sub-circuit 11, for being produced according to the control signal and modulated signal
The raw non-overlapping clock signal adaptive with the dead time of the power tube in the sub-circuit to be controlled.
In one embodiment of the invention, the detection sub-circuit 11 includes: d type flip flop D_TRIGER, the first reverse phase
Device INV1, the second phase inverter INV2, third phase inverter INV3, first resistor R1, first capacitor C1, the first PMOS tube PM1, second
PMOS tube PM2 and the first NMOS tube NM1；Wherein,
The first PMOS tube PM1 and the first capacitor C1 are sequentially connected in series between end SW to be detected and ground terminal GND；
The first NMOS tube NM1 and the first resistor R1 be sequentially connected in series drain electrode in the first PMOS tube PM1 with
Between the ground terminal GND；
The grid of the first PMOS tube PM1 is electrically connected the output end vo ut, the first PMOS of the DC-DC converter
The substrate of pipe PM1 is connected with the source electrode of the second PMOS tube PM2 and substrate；
The drain electrode of the second PMOS tube PM2 is connected with the grid of the first PMOS tube PM1, second PMOS tube
The grid of PM2 is electrically connected first control signal end Vctrl1；
The grid of the first NMOS tube NM1 is electrically connected second control signal end Vctrl2；
The first phase inverter INV1 and the second phase inverter INV2 are sequentially connected in series in the leakage of the first PMOS tube PM1
Between pole and the input end of clock of the d type flip flop D_TRIGER；
The SD that the third phase inverter INV3 is electrically connected to the modulated signal end PWM and d type flip flop D_TRIGER is inputted
Between end；
The RD input terminal of the d type flip flop D_TRIGER is electrically connected output end vo ut, the D input of the DC-DC converter
End is electrically connected the ground terminal GND；
Output end of the Q output of the d type flip flop D_TRIGER as the detection sub-circuit 11.
In one embodiment of the invention, the delay sub-circuit 12 includes: the 4th phase inverter INV4, the 5th phase inverter
INV5, hex inverter INV6, the 7th phase inverter INV7, the 8th phase inverter INV8, the first delay unit DELAY1, the second delay
Cells D ELAY2, the first NAND gate NAND1, the second NAND gate NAND2 and nor gate NOR1；Wherein,
The nor gate NOR1, the 4th phase inverter INV4, the first NAND gate NAND1 and the 5th phase inverter
INV5 is successively serially electrically connected, and the second input terminal of the first NAND gate NAND1 is electrically connected the d type flip flop D_TRIGER's
Q output；
The second NAND gate NAND2, the hex inverter INV6, the 7th phase inverter INV7 and the described 8th are instead
Phase device INV8 is successively serially electrically connected；
The first input end of the nor gate NOR1 is electrically connected institute with the first input end of the second NAND gate NAND2
State modulated signal end PWM；
The second input terminal of the nor gate NOR1 is electrically connected the 8th reverse phase through the second delay unit DELAY2
The output end of device INV8；
The second input terminal of the second NAND gate NAND2 is through the first delay unit DELAY1 electrical connection the described 5th
The output end of phase inverter INV5；
The output end of the output end and the 8th phase inverter INV8 of the 5th phase inverter INV5 prolongs respectively as described
When sub-circuit 12 the first output end and second output terminal.
In one embodiment of the invention, the first delay unit DELAY1 includes: third PMOS tube PM3, the 9th
Phase inverter INV9, the tenth phase inverter INV10, the 11st phase inverter INV11, the 12nd phase inverter INV12, the 13rd phase inverter
INV13, second resistance R2 and the second capacitor C2；Wherein,
The 9th phase inverter INV9, the tenth phase inverter INV10, the second resistance R2, the 11st reverse phase
Device INV11, the 12nd phase inverter INV12 and the 13rd phase inverter INV13 are successively serially electrically connected, and the described 9th is anti-
The input terminal of phase device INV9 is electrically connected the ground terminal GND；
The third PMOS tube PM3 and the second capacitor C2 are sequentially connected in series in the output end of the DC-DC converter
Between Vout and the ground terminal GND；
The grid of the third PMOS tube PM3 is electrically connected the output end of the 5th phase inverter INV5, the 3rd PMOS
The drain electrode of pipe PM3 is electrically connected the input terminal of the 11st phase inverter INV11；
Output end of the output end of the 13rd phase inverter INV13 as the first delay unit DELAY1.
In one embodiment of the invention, the second delay unit DELAY2 includes: the second NMOS tube NM2, the tenth
Four phase inverter INV14, the 15th phase inverter INV15, the tenth hex inverter INV16, the 17th phase inverter INV17, eighteen incompatibilities
Phase device INV18, the 19th phase inverter INV19,3rd resistor R3 and third capacitor C3；Wherein,
The 14th phase inverter INV14, the 15th phase inverter INV15, the tenth hex inverter INV16, institute
State 3rd resistor R3, the 17th phase inverter INV17, the eighteen incompatibilities phase device INV18 and the 19th phase inverter INV19 according to
The input terminal of secondary serial electrical connection, the 14th phase inverter INV14 is electrically connected the ground terminal GND；
The second NMOS tube NM2 is electrically connected to the defeated of the 17th phase inverter INV17 with the third capacitor C3
Enter between end and the ground terminal GND；
The grid of the second NMOS tube NM2 is electrically connected the output end of the 8th phase inverter INV8；
Output end of the output end of the 19th phase inverter INV19 as the second delay unit DELAY2.
Compared with prior art, the present invention at least has the advantages that
Provided by the present invention for the self-adaptive dead-time control circuit of DC-DC converter, can be born according to different
Electric current, the different adaptive adjustment dead times of input voltage generation are carried, is made so as to avoid DC-DC converter dead time is too short
At loss of efficiency, and reduce excessive dead time in DC-DC converter and bring power consumption penalty, improve DC-DC and turn
The overall conversion efficiency of parallel operation.
Detailed description of the invention
Below in conjunction with attached drawing, specific embodiments of the present invention will be described in detail.
Fig. 1 is a kind of self-adaptive dead-time control circuit for DC-DC converter provided in an embodiment of the present invention
Structural schematic diagram；
Fig. 2 is a kind of structural schematic diagram for detecting sub-circuit provided in an embodiment of the present invention；
Fig. 3 is a kind of structural schematic diagram of sub-circuit that is delayed provided in an embodiment of the present invention；
Fig. 4 is a kind of structural schematic diagram of first delay unit DELAY1 provided in an embodiment of the present invention；
Fig. 5 is a kind of structural schematic diagram of second delay unit DELAY2 provided in an embodiment of the present invention；
Fig. 6 is a kind of local circuit structural schematic diagram of DC-DC converter provided in an embodiment of the present invention；
Simulation waveform when Fig. 7 is input voltage vin=0.9V, load current Iload=1mA in the embodiment of the present invention
Figure；
Simulation waveform when Fig. 8 is input voltage vin=1.6V, load current Iload=100mA in the embodiment of the present invention
Figure；
Fig. 9 is that self-adaptive dead-time control circuit provided by the invention is applied to constant dead-time control circuit
Transfer efficiency simulation curve figure when BOOST converter under different loads electric current.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
The present invention is described in further details with reference to the accompanying drawing.
Embodiment one
Referring to Figure 1, Fig. 1 is a kind of adaptive dead zone time for DC-DC converter provided in an embodiment of the present invention
The structural schematic diagram of control circuit.The control circuit 10 includes:
Sub-circuit 11 is detected, for generating control signal according to the voltage at end to be detected in sub-circuit to be controlled；
Be delayed sub-circuit 12, is electrically connected the detection sub-circuit 11, for being produced according to the control signal and modulated signal
The raw non-overlapping clock signal adaptive with the dead time of the power tube in the sub-circuit to be controlled.
Further, Fig. 2 is referred to, Fig. 2 is a kind of structural schematic diagram for detecting sub-circuit provided in an embodiment of the present invention.
The detection sub-circuit 11 includes: d type flip flop D_TRIGER, the first phase inverter INV1, the second phase inverter INV2, third phase inverter
INV3, first resistor R1, first capacitor C1, the first PMOS tube PM1, the second PMOS tube PM2 and the first NMOS tube NM1；Wherein,
The first PMOS tube PM1 and the first capacitor C1 are sequentially connected in series between end SW to be detected and ground terminal GND；
The first NMOS tube NM1 and the first resistor R1 be sequentially connected in series drain electrode in the first PMOS tube PM1 with
Between the ground terminal GND；
The grid of the first PMOS tube PM1 is electrically connected the output end vo ut, the first PMOS of the DC-DC converter
The substrate of pipe PM1 is connected with the source electrode of the second PMOS tube PM2 and substrate；
The drain electrode of the second PMOS tube PM2 is connected with the grid of the first PMOS tube PM1, second PMOS tube
The grid of PM2 is electrically connected first control signal end Vctrl1；
The grid of the first NMOS tube NM1 is electrically connected second control signal end Vctrl2；
The first phase inverter INV1 and the second phase inverter INV2 are sequentially connected in series in the leakage of the first PMOS tube PM1
Between pole and the input end of clock of the d type flip flop D_TRIGER；
The SD that the third phase inverter INV3 is electrically connected to the modulated signal end PWM and d type flip flop D_TRIGER is inputted
Between end；
The RD input terminal of the d type flip flop D_TRIGER is electrically connected output end vo ut, the D input of the DC-DC converter
End is electrically connected the ground terminal GND；
Output end output third control of the D output end of the d type flip flop D_TRIGER as the detection sub-circuit 11
Signal Vctrl3.
Further, Fig. 3 is referred to, Fig. 3 is a kind of structural schematic diagram of sub-circuit that is delayed provided in an embodiment of the present invention；
The delay sub-circuit 12 includes: the 4th phase inverter INV4, the 5th phase inverter INV5, hex inverter INV6, the 7th phase inverter
INV7, the 8th phase inverter INV8, the first delay unit DELAY1, the second delay unit DELAY2, the first NAND gate NAND1,
Two NAND gate NAND2 and nor gate NOR1；Wherein,
The nor gate NOR1, the 4th phase inverter INV4, the first NAND gate NAND1 and the 5th phase inverter
INV5 is successively serially electrically connected, and the second input terminal of the first NAND gate NAND1 is electrically connected the d type flip flop D_TRIGER's
Q output；
The second NAND gate NAND2, the hex inverter INV6, the 7th phase inverter INV7 and the described 8th are instead
Phase device INV8 is successively serially electrically connected；
The first input end of the nor gate NOR1 is electrically connected institute with the first input end of the second NAND gate NAND2
State modulated signal end PWM；
The second input terminal of the nor gate NOR1 is electrically connected the 8th reverse phase through the second delay unit DELAY2
The output end of device INV8；
The second input terminal of the second NAND gate NAND2 is through the first delay unit DELAY1 electrical connection the described 5th
The output end of phase inverter INV5；
The output end of the output end and the 8th phase inverter INV8 of the 5th phase inverter INV5 prolongs respectively as described
When sub-circuit 12 the first output end and second output terminal, and export non-overlapping the first clock signal P_DRIVE and respectively
Two clock signal N_DRIVE.
Further, Fig. 4 is referred to, Fig. 4 is a kind of knot of first delay unit DELAY1 provided in an embodiment of the present invention
Structure schematic diagram；First delay unit DELAY1 includes: third PMOS tube PM3, the 9th phase inverter INV9, the tenth phase inverter
INV10, the 11st phase inverter INV11, the 12nd phase inverter INV12, the 13rd phase inverter INV13, second resistance R2 and second
Capacitor C2；Wherein,
The 9th phase inverter INV9, the tenth phase inverter INV10, the second resistance R2, the 11st reverse phase
Device INV11, the 12nd phase inverter INV12 and the 13rd phase inverter INV13 are successively serially electrically connected, and the described 9th is anti-
The input terminal of phase device INV9 is electrically connected the ground terminal GND；
The third PMOS tube PM3 and the second capacitor C2 are sequentially connected in series in the output end of the DC-DC converter
Between Vout and the ground terminal GND；
The grid of the third PMOS tube PM3 is electrically connected the output end of the 5th phase inverter INV5, the 3rd PMOS
The drain electrode of pipe PM3 is electrically connected the input terminal of the 11st phase inverter INV11；
Output end of the output end of the 13rd phase inverter INV13 as the first delay unit DELAY1.
Further, Fig. 5 is referred to, Fig. 5 is a kind of knot of second delay unit DELAY2 provided in an embodiment of the present invention
Structure schematic diagram；Second delay unit DELAY2 includes: the second NMOS tube NM2, the 14th phase inverter INV14, the 15th reverse phase
Device INV15, the tenth hex inverter INV16, the 17th phase inverter INV17, eighteen incompatibilities phase device INV18, the 19th phase inverter
INV19,3rd resistor R3 and third capacitor C3；Wherein,
The 14th phase inverter INV14, the 15th phase inverter INV15, the tenth hex inverter INV16, institute
State 3rd resistor R3, the 17th phase inverter INV17, the eighteen incompatibilities phase device INV18 and the 19th phase inverter INV19 according to
The input terminal of secondary serial electrical connection, the 14th phase inverter INV14 is electrically connected the ground terminal GND；
The second NMOS tube NM2 is electrically connected to the defeated of the 17th phase inverter INV17 with the third capacitor C3
Enter between end and the ground terminal GND；
The grid of the second NMOS tube NM2 is electrically connected the output end of the 8th phase inverter INV8；
Output end of the output end of the 19th phase inverter INV19 as the second delay unit DELAY2.
Self-adaptive dead-time control circuit provided in this embodiment for DC-DC converter, can be according to different
Load current, different input voltages generate adaptive adjustment dead time, too short so as to avoid DC-DC converter dead time
Caused by loss of efficiency, and reduce excessive dead time in DC-DC converter and bring power consumption penalty, improve DC-DC
The overall conversion efficiency of converter.
Embodiment two
The principle of the present invention and implementation are described in detail below with reference to specific application circuit.
Specifically, referring to Fig. 6, Fig. 6 is a kind of local circuit structure of DC-DC converter provided in an embodiment of the present invention
Schematic diagram；It further include to be controlled including the detection sub-circuit as described in embodiment one and delay sub-circuit in the circuit structure
System circuit and logic controller；
Specifically, sub-circuit to be controlled includes: inductance L, the 4th PMOS tube PM4, third NMOS tube NM3, the first driver
DRIVE1, the second driver DRIVE2, the 4th capacitor C4, the 4th resistance R4, the 5th resistance R5 and load resistance Rout；Wherein,
The inductance L, the 4th PMOS tube PM4 and load resistance Rout be sequentially connected in series in the Input voltage terminal Vin with connect
Between ground terminal GND；
The third NMOS tube NM3 is electrically connected between the source electrode and ground terminal GND of the 4th PMOS tube PM4；
4th capacitor C4 is electrically connected between the drain electrode and ground terminal GND of the 4th PMOS tube PM4；
4th resistance R4 and the 5th resistance R5 are serially connected between the drain electrode and ground terminal GND of the 4th PMOS tube PM4；
The source electrode of 4th PMOS tube PM4 is connected with the source electrode of the first PMOS tube PM1 in detection sub-circuit；4th PMOS tube
The grid of PM4 is electrically connected the output end of the 5th phase inverter INV5 through the second driver DRIVE2；
The grid of third NMOS tube NM3 is electrically connected the output end of the 8th phase inverter INV8 through the first driver DRIVE1.
The first input end of logic controller is electrically connected to the 4th resistance R4 and concatenates at the node to be formed with the 5th resistance R5,
Second input terminal of logic controller is electrically connected reference voltage end Vref, the first output end of logic controller, second output terminal,
Third output end is respectively as first control signal end Vctrl1, second control signal end Vctrl2, modulated signal end PWM；Its
In, the first input end of modulated signal end PWM AND OR NOT gate NOR1 and the first input end of the second NAND gate NAND2 are electrically connected
It connects.
The principle of the present invention and implementation are illustrated below with reference to Fig. 6.It is specific as follows:
Logic controller generates modulated signal PWM according to the voltage of the 5th resistance R5.Modulated signal PWM can be input to delay
In sub-circuit.The the first delay unit DELAY1 and the second delay unit DELAY2 being delayed in sub-circuit generate two fixations
Delay, and generate delay it is longer, in any condition, can to avoid the 4th PMOS tube PM4 in sub-circuit to be controlled with
Third NMOS tube NM3 is simultaneously turned on.Detection sub-circuit can be beaten in advance in the delay caused by the second delay unit DELAY2
The 4th PMOS tube PM4 is opened, to realize adaptive dead time.
When the modulated signal of modulated signal end PWM output is from high to low, second clock signal N_DRIVE becomes low, then
Third NMOS tube NM3 is closed.If it is high level, the first clock signal P_DRIVE that third controls signal Vctrl3 always
It needs just become low potential after the constant time lag that the second delay unit DELAY2 is generated, at this time the 4th PMOS tube
PM4 is opened.But when too long dead time occurs, then end SW to be detected (source electrode of the 4th PMOS tube PM4) current potential will
It increases, after an output voltage Vout high diode voltage of the SW voltage in end to be detected than load resistance Rout, detects son electricity
The first PMOS tube PM1 conducting in road, then the voltage on first capacitor C1 can increase, while the output of the second phase inverter INV2
Holding the voltage of SW_D also can and then increase.When the voltage signal rising edge of the output end SW_D of the second phase inverter INV2 acts on D
When the input end of clock CLK of trigger, the output signal of the Q output of d type flip flop will become low from height, i.e., the described third control
Vctrl3 signal processed becomes low, then the first clock signal P_DRIVE directly becomes low, and the 4th PMOS tube PM4 is not necessarily at this time
It is opened in advance by the constant time lag that the second delay unit DELAY2 is generated.When this process realizes adaptive dead zone
Between.
Fig. 7 is referred to, when Fig. 7 is input voltage vin=0.9V, load current Iload=1mA in the embodiment of the present invention
Simulation waveform.It will be apparent from this figure that dead time is when input voltage vin=0.9V, load current Iload=1mA
5.2ns。
Fig. 8 is referred to, when Fig. 8 is input voltage vin=1.6V, load current Iload=100mA in the embodiment of the present invention
Simulation waveform.It will be apparent from this figure that when input voltage vin=1.6V, load current Iload=100mA, when dead zone
Between be 1.4ns.
Fig. 9 is referred to, Fig. 9 is self-adaptive dead-time control circuit provided by the invention and fixed Power MOSFET electricity
Transfer efficiency simulation curve figure when road is applied to BOOST converter under different loads electric current.It will be apparent from this figure that In
Under different load currents, when self-adaptive dead-time control circuit is applied to BOOST converter, the transfer efficiency of converter
Obviously substantially it is higher than transfer efficiency when constant dead-time control circuit to be applied to BOOST converter.
To sum up, specific case used herein is expounded structure and embodiment of the invention, the above implementation
The explanation of example is merely used to help understand method and its core concept of the invention；Meanwhile for the general technology people of this field
Member, according to the thought of the present invention, there will be changes in the specific implementation manner and application range, to sum up, in this specification
Appearance should not be construed as limiting the invention, and protection scope of the present invention should be subject to the attached claims.
Claims (4)
1. a kind of self-adaptive dead-time control circuit (10) for DC-DC converter characterized by comprising
It detects sub-circuit (11), for generating control signal according to the voltage at end to be detected in sub-circuit to be controlled；
It is delayed sub-circuit (12), is electrically connected the detection sub-circuit (11), for being produced according to the control signal and modulated signal
The raw non-overlapping clock signal adaptive with the dead time of the power tube in the sub-circuit to be controlled；Wherein,
The detection sub-circuit (11) includes: d type flip flop (D_TRIGER), the first phase inverter (INV1), the second phase inverter
(INV2), third phase inverter (INV3), first resistor (R1), first capacitor (C1), the first PMOS tube (PM1), the second PMOS tube
(PM2) and the first NMOS tube (NM1)；Wherein,
First PMOS tube (PM1) and the first capacitor (C1) are sequentially connected in series in end to be detected (SW) and ground terminal (GND)
Between；
First NMOS tube (NM1) and the first resistor (R1) are sequentially connected in series in the drain electrode of first PMOS tube (PM1)
Between the ground terminal (GND)；
The grid of first PMOS tube (PM1) is electrically connected the output end (Vout) of the DC-DC converter, the first PMOS
The substrate of pipe (PM1) is connected with the source electrode of second PMOS tube (PM2) and substrate；
The drain electrode of second PMOS tube (PM2) is connected with the grid of first PMOS tube (PM1), second PMOS tube
(PM2) grid is electrically connected first control signal end (Vctrl1)；
The grid of first NMOS tube (NM1) is electrically connected second control signal end (Vctrl2)；
First phase inverter (INV1) and second phase inverter (INV2) are sequentially connected in series in first PMOS tube (PM1)
Between drain electrode and the input end of clock of the d type flip flop (D_TRIGER)；
The third phase inverter (INV3) is electrically connected to modulated signal end (PWM) and the SD of the d type flip flop (D_TRIGER) is defeated
Enter between end；
The RD input terminal of the d type flip flop (D_TRIGER) is electrically connected the output end (Vout) of the DC-DC converter, the D
The D input terminal of trigger (D_TRIGER) is electrically connected the ground terminal (GND)；
Output end of the Q output of the d type flip flop (D_TRIGER) as detection sub-circuit (11).
2. control circuit (10) according to claim 1, which is characterized in that the delay sub-circuit (12) includes: the 4th
Phase inverter (INV4), the 5th phase inverter (INV5), hex inverter (INV6), the 7th phase inverter (INV7), the 8th phase inverter
(INV8), the first delay unit (DELAY1), the second delay unit (DELAY2), the first NAND gate (NAND1), the second NAND gate
(NAND2) and nor gate (NOR1)；Wherein,
The nor gate (NOR1), the 4th phase inverter (INV4), first NAND gate (NAND1) and the 5th reverse phase
Device (INV5) successively serial electrical connection, the second input terminal of first NAND gate (NAND1) are electrically connected the d type flip flop (D_
TRIGER Q output)；
Second NAND gate (NAND2), the hex inverter (INV6), the 7th phase inverter (INV7) and the described 8th
Phase inverter (INV8) successively serial electrical connection；
The first input end of the nor gate (NOR1) is electrically connected institute with the first input end of second NAND gate (NAND2)
State modulated signal end (PWM)；
Second input terminal of the nor gate (NOR1) is electrically connected the 8th reverse phase through second delay unit (DELAY2)
The output end of device (INV8)；
Second input terminal of second NAND gate (NAND2) is through first delay unit (DELAY1) electrical connection the described 5th
The output end of phase inverter (INV5)；
The output end of 5th phase inverter (INV5) and the output end of the 8th phase inverter (INV8) prolong respectively as described
When sub-circuit (12) the first output end and second output terminal.
3. control circuit (10) according to claim 2, which is characterized in that the first delay unit (DELAY1) packet
It includes: third PMOS tube (PM3), the 9th phase inverter (INV9), the tenth phase inverter (INV10), the 11st phase inverter (INV11),
12 phase inverters (INV12), the 13rd phase inverter (INV13), second resistance (R2) and the second capacitor (C2)；Wherein,
9th phase inverter (INV9), the tenth phase inverter (INV10), the second resistance (R2), the described 11st are instead
The successively serial electrical connection of phase device (INV11), the 12nd phase inverter (INV12) and the 13rd phase inverter (INV13), institute
The input terminal for stating the 9th phase inverter (INV9) is electrically connected the ground terminal (GND)；
The third PMOS tube (PM3) and second capacitor (C2) are sequentially connected in series in the output end of the DC-DC converter
(Vout) between the ground terminal (GND)；
The grid of the third PMOS tube (PM3) is electrically connected the output end of the 5th phase inverter (INV5), the 3rd PMOS
The drain electrode for managing (PM3) is electrically connected the input terminal of the 11st phase inverter (INV11)；
Output end of the output end of 13rd phase inverter (INV13) as first delay unit (DELAY1).
4. control circuit (10) according to claim 2, which is characterized in that the second delay unit (DELAY2) packet
It includes: the second NMOS tube (NM2), the 14th phase inverter (INV14), the 15th phase inverter (INV15), the tenth hex inverter
(INV16), the 17th phase inverter (INV17), eighteen incompatibilities phase device (INV18), the 19th phase inverter (INV19), 3rd resistor
(R3) and third capacitor (C3)；Wherein,
14th phase inverter (INV14), the 15th phase inverter (INV15), the tenth hex inverter (INV16),
The 3rd resistor (R3), the 17th phase inverter (INV17), the eighteen incompatibilities phase device (INV18) and the 19th reverse phase
Device (INV19) successively serial electrical connection, the input terminal of the 14th phase inverter (INV14) are electrically connected the ground terminal (GND)；
Second NMOS tube (NM2) and the third capacitor (C3) are electrically connected to the 17th phase inverter (INV17)
Between input terminal and the ground terminal (GND)；
The grid of second NMOS tube (NM2) is electrically connected the output end of the 8th phase inverter (INV8)；
Output end of the output end of 19th phase inverter (INV19) as second delay unit (DELAY2).
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| CN111293862B (en) * | 2020-02-27 | 2021-07-02 | 电子科技大学 | High-reliability self-adaptive dead time grid driving circuit |
| CN111541364B (en) * | 2020-03-31 | 2023-02-10 | 西安电子科技大学 | Dead time control circuit and control method for DC-DC converter |
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| CN102801317A (en) * | 2012-08-16 | 2012-11-28 | 电子科技大学 | Adaptive sectional driving DC-DC converter |
| CN106374745A (en) * | 2016-09-21 | 2017-02-01 | 西安电子科技大学 | Single-inductor dual-path output DC-DC boosting converter based on voltage intermodulation suppression |
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| CN102170228B (en) * | 2011-04-29 | 2013-06-12 | 电子科技大学 | Dead time control circuit used in a DC-DC converter |
| CN103368394B (en) * | 2013-07-26 | 2016-05-11 | 武汉大学 | A kind of efficient voltage reducing type DC-DC converter |
| CN104578777B (en) * | 2015-01-30 | 2017-03-15 | 西安电子科技大学 | The dead-time control circuit being applied in voltage-dropping type DC DC transducers |
| CN104901541B (en) * | 2015-06-03 | 2017-04-19 | 东南大学 | Switching power supply power tube driven dead band time adaptive control circuit and method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102801317A (en) * | 2012-08-16 | 2012-11-28 | 电子科技大学 | Adaptive sectional driving DC-DC converter |
| CN106374745A (en) * | 2016-09-21 | 2017-02-01 | 西安电子科技大学 | Single-inductor dual-path output DC-DC boosting converter based on voltage intermodulation suppression |
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