CN107993924B - The method of residual defects after removal photoresist developing - Google Patents
The method of residual defects after removal photoresist developing Download PDFInfo
- Publication number
- CN107993924B CN107993924B CN201711178203.XA CN201711178203A CN107993924B CN 107993924 B CN107993924 B CN 107993924B CN 201711178203 A CN201711178203 A CN 201711178203A CN 107993924 B CN107993924 B CN 107993924B
- Authority
- CN
- China
- Prior art keywords
- photoresist
- size
- offset plate
- photoetching offset
- photoetching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67242—Apparatus for monitoring, sorting or marking
- H01L21/67253—Process monitoring, e.g. flow or thickness monitoring
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Photosensitive Polymer And Photoresist Processing (AREA)
Abstract
The invention discloses it is a kind of removal photoresist developing after residual defects method, include the following: Step 1: on wafer formed photoresist and carry out exposure and imaging formed photoetching offset plate figure, by exposure the size of photoetching offset plate figure is pre-defined；Step 2: carrying out photoresist pretreating process completely removes photoetching glue residua existing for developed region, photoresist pretreating process makes the size reduction of photoetching offset plate figure simultaneously, makes the final size of photoetching offset plate figure reach target size in conjunction with the size of size predetermined and diminution.The present invention is able to achieve the residual after removal photoresist developing, to eliminate the dielectric layer residual after subsequent dielectric layers etching.
Description
Technical field
The present invention relates to a kind of semiconductor integrated circuit manufacture method, in particular to remained after a kind of removal photoresist developing
The method of defect.
Background technique
In device production process, litho developing process is often used, reuses wet etching after photoetching development
Except the dielectric layer of developing regional.But development capability of the photoetching in bulk region is insufficient, namely when developing regional area is larger
When, it may appear that a small amount of photoetching glue residua.Dielectric layer is removed by wet etching again under the conditions of remaining with photoresist
When, due to cannot achieve the abundant of solution and dielectric layer above the dielectric layer in the region that needs to be etched with photoetching glue residua
Contact, eventually results in the residual defects of dielectric layer.As shown in Figure 1, being situated between using after the definition of existing photoetching development method
Photo after matter layer etching；As can be seen that distributed defect shown in many labels 101 in Fig. 1.
Summary of the invention
Technical problem to be solved by the invention is to provide a kind of methods of residual defects after removal photoresist developing, can be real
The residual after photoresist developing is now removed, to eliminate the dielectric layer residual after subsequent dielectric layers etching.
In order to solve the above technical problems, the method for residual defects includes such as after removal photoresist developing provided by the invention
Under:
Step 1: forming photoresist on wafer, the photoresist is exposed and development forms photoetching offset plate figure, led to
It crosses the exposure to pre-define the size of the photoetching offset plate figure, in developed region, there are photoetching glue residuas.
Step 2: carrying out photoresist pretreating process, completely removed by the photoresist pretreating process developed
Photoetching glue residua existing for region, while the photoresist pretreating process makes the size reduction of the photoetching offset plate figure, passes through
The size of the photoetching offset plate figure predetermined subtracts the size reduction for making the photoetching offset plate figure in step 2 in step 1
The final size for measuring the photoetching offset plate figure and so that the final size of the photoetching offset plate figure is reached target size.
A further improvement is that the wafer is the wafer that semiconductor substrate is formed.
A further improvement is that being formed with dielectric layer in the crystal column surface, the photoetching offset plate figure is described for defining
The graphic structure of dielectric layer.
A further improvement is that being carried out using the photoetching offset plate figure as mask to the dielectric layer after step 2 completion
Etching, by removing photoresist residual eliminating existing for developed region in step 2 in the region that is etched of the dielectric layer
Form residual defects.
A further improvement is that removing the photoresist figure by degumming process after dielectric layer etching is completed
Shape.
A further improvement is that the temperature of the photoresist pretreating process in step 2 is lower than the degumming process
Temperature.
A further improvement is that the photoresist pretreating process in step 2 in the equipment of the degumming process into
Row.
A further improvement is that including board heating element in the equipment of the degumming process, in the degumming process
The wafer is directly placed on the board heating element.
A further improvement is that in the photoresist pretreating process in step 2, by thimble by the wafer top
The bottom surface for making the wafer and the board heating element standoff distance are acted, bottom surface and the board by the adjusting wafer
The distance of heating element adjusts the temperature of the photoresist pretreating process.
A further improvement is that the wafer is directly placed at institute in the photoresist pretreating process in step 2
It states on board heating element, the heating parameters by adjusting the board heating element adjust the photoresist pretreating process
Temperature.
A further improvement is that, it is characterised in that:
The temperature of photoresist pretreating process described in step 2 is lower, and Ash Rate is slower, is more conducive to the light
Photoresist pretreating process controls the reduction volume of the size of the photoetching offset plate figure, exists meeting the region that be developed
Photoresist residue removal under the premise of the reduction volume of the size of the photoetching offset plate figure is adjusted such that the photoetching offset plate figure
Final size reach target size.
It requires to guarantee rear a further improvement is that carrying out size predetermined to the photoetching offset plate figure in step 1
The surplus size of the photoetching offset plate figure is greater than etc. when photoresist residue removal existing for the region that be developed in continuous step 2
In target size, increase the photoresist pretreating process when the surplus size of the photoetching offset plate figure is greater than target size
Time makes the final size of the photoetching offset plate figure be equal to target size.
A further improvement is that Ash Rate of the photoresist pretreating process described in pre-production at corresponding temperature is bent
Line carries out according to the Ash Rate curve being previously obtained the control of the reduction amount of the size to the photoetching offset plate figure in step 2
System.
A further improvement is that the semiconductor substrate is silicon substrate.
A further improvement is that the dielectric layer includes: oxide layer or nitration case.
The size of photoetching offset plate figure is pre-defined before photoresist developing of the present invention, after photoresist developing
The remaining photoresist pretreating process of removal photoresist has been carried out, it is residual due to eliminating photoresist by photoresist pretreating process
It stays, therefore subsequent dielectric layers can be made normally to be etched, so as to eliminate dielectric layer residual defects.
Meanwhile the present invention before development pre-defines the size of photoetching offset plate figure, can just compensate at photoresist
Influence of the science and engineering skill to the reduction of the size of photoetching offset plate figure, so that the final size of photoetching offset plate figure reaches target size, and
The definition to the etch areas of dielectric layer is finally made to reach target size, so the present invention, which is able to achieve, is not influencing dielectric layer
Medium layer defect residual is eliminated under conditions of dimension of picture.
Detailed description of the invention
The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:
Fig. 1 is that the photo after dielectric layer etching is carried out after defining using existing photoetching development method；
Fig. 2 be the embodiment of the present invention removal photoresist developing after residual defects method flow chart；
Fig. 3 A- Fig. 3 B is the device junction composition in each step of present invention method；
Fig. 4 is the structure chart of the equipment of degumming process；
Fig. 5 is Ash Rate curve；
Fig. 6 is that the photo after dielectric layer etching is carried out after defining using photoetching development of embodiment of the present invention method.
Specific embodiment
As shown in Fig. 2, be the embodiment of the present invention removal photoresist developing after residual defects method flow chart；Such as Fig. 3 A
To shown in Fig. 3 B, being device junction composition in each step of present invention method；The embodiment of the present invention removes photoresist developing
The method of residual defects includes the following: afterwards
Step 1: as shown in Figure 3A, forming photoresist on wafer 1, the photoresist is exposed and formation of developing
Photoetching offset plate figure 2 pre-defines the size of the photoetching offset plate figure 2 by the exposure, deposits in developed region
In photoetching glue residua 3.In Fig. 3 A, d1 is the size of the photoetching offset plate figure 2 predetermined.
Step 2: as shown in Figure 3B, carrying out photoresist pretreating process, being gone completely by the photoresist pretreating process
Except photoetching glue residua 3 existing for developed region, while the photoresist pretreating process makes the ruler of the photoetching offset plate figure 2
Very little diminution, being subtracted by the size of the photoetching offset plate figure 2 predetermined in step 1 makes the photoresist figure in step 2
The final size for measuring the photoetching offset plate figure 2 of the size reduction of shape 2 simultaneously reaches the final size of the photoetching offset plate figure 2
To target size.In Fig. 3 B, d2 is the final size of the photoetching offset plate figure 2, and d2 is less than d1, and d1-d2 is that photoresist is located in advance
Science and engineering skill makes the amount of the size reduction of the photoetching offset plate figure 2.
In the embodiment of the present invention, the wafer 1 is the wafer 1 that semiconductor substrate is formed.It is formed on 1 surface of wafer
Dielectric layer, the photoetching offset plate figure 2 are used to define the graphic structure of the dielectric layer.Preferably, the semiconductor substrate is silicon
Substrate.The dielectric layer includes: oxide layer or nitration case.
The dielectric layer is performed etching for mask with the photoetching offset plate figure 2 after step 2 completion, passes through step
The region formation residual that is etched that the elimination of photoetching glue residua 3 existing for developed region is removed in two in the dielectric layer lacks
It falls into.
After dielectric layer etching is completed, the photoetching offset plate figure 2 is removed by degumming process.
The temperature of the photoresist pretreating process in step 2 is lower than the temperature of the degumming process.
The photoresist pretreating process in step 2 carries out in the equipment of the degumming process.As shown in figure 4, institute
Stating includes board heating element 201 in the equipment of degumming process, and the wafer 1 described in the degumming process is directly placed at described
On board heating element 201.In the photoresist pretreating process in step 2, the wafer 1 is jacked up by thimble 202
The 201 standoff distance d3 of bottom surface and the board heating element for making the wafer 1, by the bottom surface and the institute that adjust the wafer 1
The distance d3 for stating board heating element 201 adjusts the temperature of the photoresist pretreating process.Alternatively, the light in step 2
In photoresist pretreating process, the wafer 1 is directly placed on the board heating element 201, is added by adjusting the board
The heating parameters of thermal part 201 adjust the temperature of the photoresist pretreating process.
The temperature of photoresist pretreating process described in step 2 is lower, and Ash Rate is slower, is more conducive to the light
Photoresist pretreating process controls the reduction volume of the size of the photoetching offset plate figure 2, deposits meeting the region that be developed
Photoetching glue residua 3 remove under the premise of the reduction volume of the size of the photoetching offset plate figure 2 is adjusted such that the photoresist
The final size of figure 2 reaches target size.
In the embodiment of the present invention, size d1 predetermined is carried out to the photoetching offset plate figure 2 in step 1 and requires to guarantee
The surplus size of the photoetching offset plate figure 2 when removing of photoetching glue residua 3 existing for the region that be developed in subsequent step two
More than or equal to target size, increases the photoresist when the surplus size of the photoetching offset plate figure 2 is greater than target size and locate in advance
The time of science and engineering skill makes the final size d2 of the photoetching offset plate figure 2 be equal to target size.
Preferably, Ash Rate curve of the photoresist pretreating process at corresponding temperature described in energy pre-production, step
The Ash Rate curve that basis is previously obtained in rapid two carries out the control of the reduction amount of the size to the photoetching offset plate figure 2.Such as
It is Ash Rate curve shown in Fig. 5, it can be seen that 301 linear arrangement of curve, at once with the photoresist pretreating process
The increase of time is lost, photoetching offset plate figure size can be gradually reduced, and the etch period of curve 301 is every to be increased by 1 second, the photoresist figure
The size of shape 2 can reduce 10 angstroms.It is easy to control the size of the photoetching offset plate figure 2 according to curve 301.
The embodiment of the present invention pre-defines the size of photoetching offset plate figure 2 before photoresist developing, in photoetching
The photoresist pretreating process that removal photoetching glue residua 3 has been carried out after glue development, due to being gone by photoresist pretreating process
In addition to photoetching glue residua 3, therefore subsequent dielectric layers can be made normally to be etched, so as to eliminate dielectric layer residual defects.
Meanwhile the embodiment of the present invention before development pre-defines the size of photoetching offset plate figure 2, can just compensate light
Influence of the photoresist treatment process to the reduction of the size of photoetching offset plate figure 2, so that the final size of photoetching offset plate figure 2 reaches target
Size, and the definition to the etch areas of dielectric layer is finally made to reach target size, so the embodiment of the present invention is able to achieve
It does not influence to eliminate medium layer defect residual under conditions of the dimension of picture of dielectric layer.
As shown in fig. 6, be that the photo after dielectric layer etching is carried out after defining using photoetching development of embodiment of the present invention method,
Compare with Fig. 1 it is found that the embodiment of the present invention eliminates the defect residual of dielectric layer really.
The present invention has been described in detail through specific embodiments, but these are not constituted to limit of the invention
System.Without departing from the principles of the present invention, those skilled in the art can also make many modification and improvement, these are also answered
It is considered as protection scope of the present invention.
Claims (14)
1. a kind of method of residual defects after removal photoresist developing, which is characterized in that include the following:
Step 1: forming photoresist on wafer, the photoresist is exposed and development forms photoetching offset plate figure, passes through institute
It states exposure to pre-define the size of the photoetching offset plate figure, in developed region, there are photoetching glue residuas；
Step 2: carrying out photoresist pretreating process, developed region is completely removed by the photoresist pretreating process
Existing photoetching glue residua, while the photoresist pretreating process makes the size reduction of the photoetching offset plate figure, passes through step
The size of the photoetching offset plate figure predetermined subtracts the amount for making the size reduction of the photoetching offset plate figure in step 2 in one
It obtains the final size of the photoetching offset plate figure and the final size of the photoetching offset plate figure is made to reach target size；
The temperature of the photoresist pretreating process is lower, and Ash Rate is slower, is more conducive to pre-process work to the photoresist
Skill controls the reduction volume of the size of the photoetching offset plate figure, the photoetching glue residua existing for the region that satisfaction to be developed
The reduction volume of the size of the photoetching offset plate figure is adjusted such that the final size of the photoetching offset plate figure reaches under the premise of removal
To target size.
2. removing the method for residual defects after photoresist developing as described in claim 1, it is characterised in that: the wafer is half
The wafer that conductor substrate is formed.
3. removing the method for residual defects after photoresist developing as claimed in claim 2, it is characterised in that: in the wafer table
Face is formed with dielectric layer, and the photoetching offset plate figure is used to define the graphic structure of the dielectric layer.
4. removing the method for residual defects after photoresist developing as claimed in claim 3, it is characterised in that: completed in step 2
The dielectric layer is performed etching using the photoetching offset plate figure as mask later, is deposited by the region for removing developed in step 2
Photoresist residual eliminating the dielectric layer be etched region formed residual defects.
5. removing the method for residual defects after photoresist developing as claimed in claim 4, it is characterised in that: in the dielectric layer
After etching is completed, the photoetching offset plate figure is removed by degumming process.
6. removing the method for residual defects after photoresist developing as claimed in claim 5, it is characterised in that: the institute in step 2
The temperature for stating photoresist pretreating process is lower than the temperature of the degumming process.
7. removing the method for residual defects after photoresist developing as claimed in claim 6, it is characterised in that: the institute in step 2
Photoresist pretreating process is stated to carry out in the equipment of the degumming process.
8. removing the method for residual defects after photoresist developing as claimed in claim 7, it is characterised in that: the degumming process
Equipment in include board heating element, the wafer described in the degumming process is directly placed at the board heating element
On.
9. removing the method for residual defects after photoresist developing as claimed in claim 8, it is characterised in that: the institute in step 2
It states in photoresist pretreating process, the wafer is jacked up by the bottom surface for making the wafer and the board heating element by thimble
Standoff distance, the distance adjusting photoresist pretreatment work of bottom surface and the board heating element by adjusting the wafer
The temperature of skill.
10. removing the method for residual defects after photoresist developing as claimed in claim 8, it is characterised in that: in step 2
In the photoresist pretreating process, the wafer is directly placed on the board heating element, by adjusting the board
The heating parameters of heating element adjust the temperature of the photoresist pretreating process.
11. removing the method for residual defects after photoresist developing as described in claim 1, it is characterised in that:
Size predetermined is carried out to the photoetching offset plate figure in step 1 to require to guarantee to be developed in subsequent step two
Region existing for photoresist residue removal when the photoetching offset plate figure surplus size be more than or equal to target size, when the light
The surplus size of photoresist figure increases photoresist pretreating process time when being greater than target size makes the photoresist figure
The final size of shape is equal to target size.
12. removing the method for residual defects after photoresist developing as described in claim 1, it is characterised in that: pre-production institute
State Ash Rate curve of the photoresist pretreating process at corresponding temperature, the Ash Rate that basis is previously obtained in step 2
Curve carries out the control of the reduction amount of the size to the photoetching offset plate figure.
13. removing the method for residual defects after photoresist developing as claimed in claim 2, it is characterised in that: the semiconductor
Substrate is silicon substrate.
14. removing the method for residual defects after photoresist developing as claimed in claim 3, it is characterised in that: the dielectric layer
It include: oxide layer or nitration case.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711178203.XA CN107993924B (en) | 2017-11-23 | 2017-11-23 | The method of residual defects after removal photoresist developing |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711178203.XA CN107993924B (en) | 2017-11-23 | 2017-11-23 | The method of residual defects after removal photoresist developing |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107993924A CN107993924A (en) | 2018-05-04 |
| CN107993924B true CN107993924B (en) | 2019-11-19 |
Family
ID=62032722
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201711178203.XA Active CN107993924B (en) | 2017-11-23 | 2017-11-23 | The method of residual defects after removal photoresist developing |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107993924B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109273353A (en) * | 2018-08-29 | 2019-01-25 | 上海华力集成电路制造有限公司 | Improve the method for residual defects after wafer photolithography glue develops |
| CN113053766A (en) * | 2021-03-08 | 2021-06-29 | 京东方科技集团股份有限公司 | Photoresist residue detection method, panel, manufacturing method and display device |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2639372B2 (en) * | 1995-02-21 | 1997-08-13 | 日本電気株式会社 | Method for manufacturing semiconductor device |
| CN101446765A (en) * | 2007-11-27 | 2009-06-03 | 上海华虹Nec电子有限公司 | Photoetching development method |
| CN102201336B (en) * | 2010-03-26 | 2013-03-06 | 中芯国际集成电路制造(上海)有限公司 | Method for removing residue of etched oxide layer on semiconductor device layer |
| CN102539448A (en) * | 2010-12-08 | 2012-07-04 | 无锡华润上华科技有限公司 | Development residue detecting method |
-
2017
- 2017-11-23 CN CN201711178203.XA patent/CN107993924B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN107993924A (en) | 2018-05-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105892221B (en) | The production method of half-tone mask plate and TFT substrate | |
| CN107993924B (en) | The method of residual defects after removal photoresist developing | |
| TWI386982B (en) | Method for the selective doping of silicon as well as silicon substrate treated therewith | |
| CN105589131A (en) | Etching method of silicon chip grooves for optical waveguide | |
| JP2010123757A (en) | Method of forming pattern and program | |
| CN107104044A (en) | A kind of preparation method of method for making its electrode and array base palte | |
| CN102683184B (en) | A kind of manufacture method of ion implantation barrier layer | |
| US8962494B2 (en) | Method of manufacturing dual gate oxide devices | |
| CN104898378B (en) | A kind of optimization method of exposing wafer order | |
| DE102008054072A1 (en) | Self-correcting substrate holding system for focus control in exposure systems | |
| CN104157590A (en) | Electron beam defect scanning apparatus and method | |
| CN103943569A (en) | Method for eliminating hillock-shaped defects on surface of metal film | |
| CN104681417A (en) | Forming method of semiconductor device and grid electrode | |
| CN101840882B (en) | Shallow slot isolation method | |
| CN106783565A (en) | The method for improving active area pit corrosion defect | |
| CN109300781B (en) | Method for manufacturing ONO film layer | |
| TW200534435A (en) | A method for manufacturing high density flash memory and high performance logic on a single die | |
| CN101852994A (en) | Method for removing photoresist | |
| CN102890402B (en) | Method for removing defects of photosensitive developable bottom anti-reflective coatings (PS-DBARC) | |
| TWI407264B (en) | Microcomputer and its application | |
| CN109270785A (en) | Well layer lithography layout, its forming method and its Optical Proximity Correction processing method | |
| CN103887160A (en) | Method for etching control grid | |
| CN106024758A (en) | Advanced control method of polysilicon gate critical dimension | |
| TW444272B (en) | Method of effective electron beam background intensity compensation for photomask manufacturing | |
| KR900004967B1 (en) | Etching method of semiconductor |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |