CN101446765A

CN101446765A - Photoetching development method

Info

Publication number: CN101446765A
Application number: CNA200710094285XA
Authority: CN
Inventors: 陈华伦; 罗啸; 陈雄斌; 熊涛; 陈瑜
Original assignee: Shanghai Hua Hong NEC Electronics Co Ltd
Current assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date: 2007-11-27
Filing date: 2007-11-27
Publication date: 2009-06-03

Abstract

The invention discloses a photoetching development method, comprising the steps of exposing and hard curing; the characteristic sizes of exposed photoresist patterns are less than target value; the hard curing temperature in the hard curing process is increased, so that the characteristic sizes of the gaps of hard-cured photoresist patterns are controlled in the target value range. The method effectively prevents the photoresist remaining in the gaps of the photoresist patterns to form photoresist residuals interconnection in the development process; the hard curing temperature in the hard curing process is increased, and the photoresist is softened, so that the characteristic sizes of the hard-cured photoresist patterns are larger, and the characteristic sizes of the gaps of photoresist patterns are controlled in the target value range. The invention can be widely used for the manufacturing of semiconductor devices.

Description

The method of photoetching development

Technical field

The present invention relates to a kind of method of photoetching development.

Background technology

Photoetching development technology is an important techniques during semiconductor is made.In the photoetching, silicon chip has experienced a series of processing step in gluing/developing machine.Upper surface gluing, the whirl coating of pre-service silicon chip, cure (often claiming soft baking).The automatic conveyor of device interior shifts silicon chip between each operative position.Another set of conveyer will be sent into aligning and exposure system through the each a slice of silicon chip ground that gluing is handled.Litho machine with the direct mint-mark of specific mask patterns on the silicon chip of gluing.After silicon chip after the exposure is transferred to the silicon chip rail system from exposure system, need carry out the post exposure bake (dry by the fire the normal back that claims) of short time, with adhesiveness and the less standing wave that photoresist is provided.Then silicon chip comes back in gluing/developing machine, and when being sprayed onto on the silicon chip with developer solution, figure displays (see figure 1).Silicon chip after the development cures (normal claim hard baking, hard baking can not change the live width after the development substantially in the prior art) once more, then measures, and whether the live width that detects the mint-mark figure is proper, if any significant deficiency, silicon chip can be removed photoresist and do over again then.In lithographic process, exposure energy is the most important amount of decision live width size.Hard roasting purpose is in order further to remove the solvent in the photoresist.Two sizes are arranged: the characteristic dimension D2 of the characteristic dimension D1 of photoresist figure and photoresist inter-pattern space in the litho pattern, behind the bigger figure photoetching development of the ratio of D1/D2, in the photoresist inter-pattern space,, influence follow-up etching technics than the phenomenon that is easier to occur the residual interconnection of photoresist (scum).

Summary of the invention

The technical problem to be solved in the present invention provides a kind of method of photoetching development, and there is the residual interconnection of photoresist in its back of effectively avoiding developing in the photoresist inter-pattern space.

For solving the problems of the technologies described above, the method for photoetching development of the present invention is included in exposure and hard baking, and the characteristic dimension of exposure back photoresist figure is littler than predetermined target value; The roasting firmly temperature of the raising in described hard when baking makes the characteristic dimension of the photoresist inter-pattern space after the hard baking in target range.

Photoetching development method of the present invention, the characteristic dimension of utilization suitable minimizing photoresist figure when exposure, photoresist when having avoided developing remains in and forms the residual interconnection of photoresist in the photoresist inter-pattern space, and when hard baking, improving hard roasting temperature, photoresist is softening to make the characteristic dimension of the photoresist figure after the hard baking become big and the characteristic dimension of photoresist inter-pattern space is controlled in the target range.

Description of drawings

The present invention is further detailed explanation below in conjunction with accompanying drawing and embodiment:

Fig. 1 is a photoresist pattern synoptic diagram;

Fig. 2 is the residual interconnection synoptic diagram of photoresist in the prior art;

Fig. 3 is a hard roasting photoresist pattern synoptic diagram afterwards in the method for the present invention.

Embodiment

Common photoetching development method is included in gluing on the silicon chip, soft baking, exposure, back baking, develops, the measurement of baking and photoresist figure firmly, in preparation method of the present invention, characteristic dimension D1 with the photoresist figure when exposure is set at littler than desired value, be generally littler by about 1%～30% than desired value, be equivalent to make the characteristic dimension D2 of photoresist inter-pattern space bigger like this than desired value, so both ratio D1/D2 diminish, the back of therefore can avoiding developing forms the residual interconnection of photoresist in the photoresist inter-pattern space; And the needs when hard baking improve hard roasting temperature, because the raising of temperature makes in the hard baking process photoresist softening a little, the characteristic dimension of the photoresist inter-pattern space after finally being dried by the fire firmly is in target range, in this step because of the kind difference of the concrete photoresist that uses, so the hard roasting temperature that provides is also different, the hard roasting temperature in concrete the use can obtain by the test of limited number of time.In a specific embodiment, the photoresist that uses is GPR5315, the characteristic dimension of the photoresist figure after the exposure is littler by 8% than desired value, dries by the fire temperature firmly and be set to than about high 20 degree of normal hard baking temperature when hard baking, thereby pattern character size is reached in the target range.

Claims

1, a kind of method of photoetching development is included in exposure and hard baking, it is characterized in that: the characteristic dimension of described exposure back photoresist figure is littler than desired value; During described hard baking, roasting firmly temperature is increased to makes the characteristic dimension of the photoresist inter-pattern space after the hard baking in target range.

2, in accordance with the method for claim 1, it is characterized in that: the characteristic dimension of described exposure back photoresist figure is littler by 1%～30% than desired value.