CN107959502A - A kind of LDPC coding methods - Google Patents
A kind of LDPC coding methods Download PDFInfo
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- CN107959502A CN107959502A CN201610905209.1A CN201610905209A CN107959502A CN 107959502 A CN107959502 A CN 107959502A CN 201610905209 A CN201610905209 A CN 201610905209A CN 107959502 A CN107959502 A CN 107959502A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1148—Structural properties of the code parity-check or generator matrix
Abstract
The present invention provides a kind of LDPC coding methods, comprise the following steps：Designed for carrying out the LDPC encoder matrixs of LDPC codings；Coded stack RAM is initialized, the column matrix information of the information bit part of serial input and each row of encoder matrix is subjected to computing successively respectively, gained operation result is deposited at coded stack and is used for output verification bit section；Wherein, the quantity of coded stack is determined by the maximum column weight N with encoder matrix, designs LDPC encoder matrixs, including：Encoder matrix is arranged as unit using L, is divided into some sub- column matrix；First row matrix information is provided by LDPC code table in sub- column matrix, follow-up adjacent column matrix information is drawn by first row matrix information by default reckoning mode, this method can make the memory space of LDPC encoder as small as possible, it is unlikely to make design difficulty too big again, moreover it is possible to take into account the versatility of different code words.
Description
Technical field
The invention belongs to channel coding technology field, more particularly to a kind of LDPC coding methods.
Background technology
LDPC (Low Density Parity Check Code, low density parity check code) coding techniques is to believe in recent years
The research hotspot of road coding field, is widely used to satellite communication, fiber optic communication, mobile communication, digital broadcast communications at present
Deng field.The advantages of LDPC code, is close to shannon limit, flexible structure, lower error floor；But shortcoming is hardware resource
Demand is larger, and especially longer code word could embody the advantage in performance, causes to encode more complicated, and the hardware resource of demand is more
Greatly；If merely from the angle design encoder of saving resource, and the control of encoder can be made to become complicated or bring excessive
Processing delay.
Exemplified by being encoded with (38880,25920) LDPC that a kind of digit broadcasting system uses at present, information bit is 38880 ratios
Spy, check bit are 25920 bits.When for example being realized using RTL (Resistor Transistor Logic) mode, if
By full parellel processing in the way of encode, it is necessary to storage unit be 38880*25920 bits matrix.So big storage is held
Miniaturization, low-power consumption of the amount demand for LDPC encoder are all very unfavorable；And in order to save memory space, can also be only with
The storage unit of 1*25920, but corresponding addressing operation can become considerably complicated, processing delay can also greatly increase, to reality
Existing fast and reliable LDPC coding-belts carry out very big difficulty.Further, since LDPC code word also has certain " non-rule " characteristic, i.e. phase
When the code word of part cannot be obtained by computing so that the close phase of structural texture for realizing structure and code word of LDPC encoder
Close, pushed back so as to replace code table and likely result in whole LDPC encoder design.
To sum up, it when carrying out LDPC codings, can use up the memory space of LDPC encoder if a kind of method can be found
May be small, and be unlikely to make design difficulty too big, moreover it is possible to take into account the versatility of different code words --- replace code word and be unlikely to make
Whole design is made a new start, then this method be can yet be regarded as a kind of LDPC encoder design method with marked improvement.
The content of the invention
The purpose of the present invention aims to provide a kind of LDPC coding methods, enables to memory space as small as possible, and unlikely
In making design difficulty too big, moreover it is possible to take into account the versatility of different code words.
According to above-mentioned purpose, implement a kind of LDPC coding methods of the present invention, comprise the following steps：Designed for carrying out
The LDPC encoder matrixs of LDPC codings；Coded stack RAM is initialized, by the information bit part of serial input and encoder matrix
The column matrix information of each row carry out computing successively respectively, gained operation result is deposited at coded stack and is used for output verification
Bit section；Wherein, the quantity of the coded stack is determined by the maximum column weight N with the encoder matrix, described in design
LDPC encoder matrixs, including：The encoder matrix is arranged as unit using L, is divided into some sub- column matrix；First row in sub- column matrix
Matrix information is provided by LDPC code table, and follow-up adjacent column matrix information is obtained by first row matrix information by default reckoning mode
Go out.
Further, LDPC coding methods according to the present invention, also have the feature that, wherein, design the LDPC
Code table, including：The LDPC code table is made of i row address informations, which provides LDPC encoder matrix (i-1) * L+1
1 location index in row.
Further, LDPC coding methods according to the present invention, also have the feature that, wherein, preset reckoning mode
For：
An is the 1st column matrix information read from code table；
Am is to calculate the column matrix information i.e. location index of " 1 " in the follow-up adjacent column drawn by An；
M is check bit partial-length；
L is the predetermined row length of size, that is, sub- column matrix of submatrix in the encoder matrix；
M is that row sequence number subtracts 1 in sub- column matrix, i.e. m=1 ..., L-1；
It can obtain：Am=(An+m*M/L) mod (M).
Further, LDPC coding methods according to the present invention, also have the feature that, wherein, information bit part
Computing mode is done with column matrix information for mould 2 to add.
Further, LDPC coding methods according to the present invention, also have the feature that, wherein, when full detail ratio
After special serial input, the output result for reading N number of check bit intermediate results of operations and modulo 2 adder does mould 2 plus computing, its
In, the initial results of modulo 2 adder are bit 0, so as to obtain M check bit part.
Further, LDPC coding methods according to the present invention, also have the feature that, wherein, the encoder matrix
The size L of middle submatrix is based on information bit partial-length K and check bit partial-length M and the encoder matrix
Size is come definite.
Further, LDPC coding methods according to the present invention, also have the feature that, wherein, the code storage
The storage depth of device is M, width 1, which is determined by the length M of the check bit part.
Further, LDPC coding methods according to the present invention, also have the feature that, LDPC encoder further includes,
The check bit part of output and information bit part are spliced and combined.
The function and effect of the present invention
The LDPC coding methods that the present invention uses have the following advantages that：Maximum column according to encoder matrix rationally determines again
The quantity of coded stack, can be while memory space be greatly reduced so that the addressing control complexity to memory space
It is greatly reduced；And encoder output delay is smaller, only needed after the completion of the input of full detail position bit a small amount of (less than or equal to ten
A clock cycle) clock cycle can output verification position bit；Change LDPC coding codewords will not make entirely design make a new start,
Only make the appropriate adjustments.
Brief description of the drawings
The step of Fig. 1 is a kind of LDPC coding methods of the present invention is schemed；
Fig. 2 is a kind of logic circuit schematic diagram of LDPC encoder of the present invention.
Embodiment
Technical scheme is further illustrated with reference to the accompanying drawings and examples.
The step of Fig. 1 is a kind of LDPC coding methods of the present invention is schemed；
A kind of LDPC coding methods are present embodiments provided, are comprised the following steps：
Step S1:Designed for carrying out the LDPC encoder matrixs of LDPC codings；
Step S2:Computing, gained operation result are carried out to the information bit part in coding codeword and LDPC encoder matrixs
It is deposited at coded stack and is used for output verification bit section；
Wherein, the quantity of coded stack is determined by the maximum column weight N with encoder matrix.
The coding result for making LDPC is c=(λ0,λ1,...,λK-1,p0,p1,...,pm,...,pM-1)；Wherein, (λ0,
λ1,...,λK-1) it is original information bit part, it is known { 1,0 } sequence.(p0,p1,p2,...,pM-1) it is check bit
Part, is bit to be calculated.
The concrete methods of realizing of the building method of LDPC encoder is as follows：
Step 1, the encoder matrix and LDPC code table for designing LDPC so that encoder matrix has the property that：
The row of encoder matrix can be divided into Q parts, i.e. Q column matrix part, arrange, that is, have comprising continuous L per part
Q*L=K, wherein K are the bit number of original information bits part, and L is size, that is, column matrix part of submatrix in encoder matrix
Predetermined row length.
Per in adjacent L column matrix, first row matrix information is provided that (code table is made of Q rows, and often row provides LDPC by code table
The location index of " 1 ", i=0,1,2 ..., Q-1 in the i-th * of encoder matrix L+1 row), L-1 column matrix information below can be by the
One row carry out reckoning by default reckoning mode and draw.
The RAM of step 2, the N number of 1*M depth of generation, wherein N are the maximum column weight (number of " 1 " in each column) of encoder matrix,
M is the length of check bit part.It is bit 0 to initialize all address dates of RAM.
Step 3, first information bit λ of encoder serial input0Respectively with the number of the An addresses read in n RAM
According to doing mould 2 plus computing, and result restored again in the reading address An of n RAM, i.e.,Wherein, An be from
The 1st column matrix information (i.e. the location index of " 1 " in row) that code table is read, n are the first row row weight of encoder matrix, and have n
≤N；This process is the parallel work-flow to n RAM.
Step 4, for encoder serial input behind L-1 information bit λm, m=1 ..., L-1, equally respectively with
The data of the Am addresses read in Rm RAM do mould 2 plus computing, and result are restored again in the reading address Am of Rm RAM,
I.e.Wherein, Am is the location index that " 1 " in the follow-up adjacent column drawn is calculated by An, full between Am and An
The default reckoning mode of foot；Rm is row weight of the encoder matrix in the row, and has Rm≤N；This process is also the parallel behaviour to Rm RAM
Make.
This presets reckoning mode：Am=(An+m*M/L) mod (M), L are size, that is, row square of submatrix in encoder matrix
The predetermined row length of battle array part；
M is that row sequence number subtracts 1 in sub- column matrix, i.e. m=1 ..., L-1.
Step 5, the i-th * L+1 information bits (i=1,2 ..., Q-1) similarly, for encoder serial input, point
Not according to described in step 3, the data with being read in respective column weight RAM do mould 2 plus computing parallel, and the address for reading RAM is from code
The location index that i+1 row is read in table；Then result is write back parallel in the former reading addresses of corresponding RAM.
Step 6, for encoder serial input the i-th * L+j information bits (i=1,2 ..., Q-1, j=2,3 ...,
L-1), respectively according to described in step 4, parallel to read row weight RAM, it is the reckoning address according to rule to read address, with information bit
Mould 2 plus computing are done, then results back into the former of corresponding RAM and reads in address.
Step 7, after full detail bit serial inputs, among the check bit that is stored in the RAM of N number of 1*M depth
As a result it is denoted as：
(p1,0, p1,1, p1,2..., p1, M-1, p2,0, p2,1, p2,2..., p2, M-1..., pN, 0, pN, 1, pN, 2...,
pN, M-1), the RAM (read address increase successively according to order from low to high) of N number of 1*M depth is read parallel, and by N number of RAM's
Output data and the output result of modulo 2 adder do mould 2 plus computing, wherein, the initial results of modulo 2 adder are bit " 0 ", from
And obtain M check bit (p0,p1,p2,...,pM-1), it is shown below：
p0=p0
Fig. 2 is a kind of logic circuit schematic diagram of LDPC encoder of the present invention.
A kind of the present embodiment, there is provided a preferred logic practical circuit for being used for realization LDPC encoder.
In logic circuits, RAM_1 to RAM_N is the random access memory ram that N number of depth is 1*M, wherein, N is coding square
The maximum column weight of battle array, M are the length of check bit part.
RAM Controler are the read-write controllers of N number of RAM, can do read operation or write operation to N number of RAM parallel.
Code table ROM for storing LDPC code table is used for the location index for storing " 1 " in the i-th * L+1 row in encoder matrix, i
=0,1,2, Q-1；Circular adder represents 2 bit nodulo-2 additions, and square adder represents N-bit nodulo-2 addition；Delay postpones mould
Block represents the necessary delay done to the information bit of input, can continuously be exported with information bit so as to the check bit of generation；
Combine concatenation modules are serial for information bit part to be combined into 1 circuit-switched data with the check bit part that calculation process is drawn
Output.
Illustrate the LDPC coding methods of the present invention below by way of design parameter example.
Embodiment 1：
Using a kind of digit of information bit bit section as 38880 bits, the digit of check bit part is 25920 bits
Exemplified by LDPC codings, implementation method according to the present invention：
Step 1：A LDPC encoder matrix and LDPC code table are designed, has the property that encoder matrix：
1) matrix column can be divided into 108 parts, i.e. 108 column matrix parts, be arranged per part comprising continuous 360,
There are 108*360=38880 row；
Wherein, the size L of submatrix is to be based on information bit partial-length K and check bit partial-length in encoder matrix
M, and the size of encoder matrix is come definite, and with regard to value 360 in the present embodiment, the size of submatrix is 360*360.
2) the LDPC encoder matrixs are designed, including：Encoder matrix is divided for several column matrix portions with predetermined row length 360
Point；First row matrix information is provided by LDPC code table in column matrix part, and follow-up adjacent column matrix information is believed by the first column matrix
Breath is drawn by default reckoning mode.
For design parameter, per in 360 adjacent column matrix, first row matrix information is gone out that (code table is by 108 row groups by LDPC
Provide the location index of " 1 " in LDPC encoder matrix (i-1) * 360+1 row into, the i-th row, i=1,2,3 ..., 108), behind
The matrix informations of 359 row can in the following way be calculated and draw by the column matrix information of first row：Am=(An+m*
25930/360) mod (25920), t=1 ..., 359, m be that row sequence number subtracts 1 in sub- column matrix, i.e. m=1 ..., L-1.
3) LDPC code table is designed, design method includes：LDPC code table is made of i row address informations, which provides
1 location index in LDPC encoder matrix (i-1) * L+1 row.
In the present embodiment, designed LDPC code table is as follows：
Step 2：The RAM of N number of 1*M depth is generated, wherein N is the maximum column weight (number of " 1 " in each column) of encoder matrix,
N=19 herein is understood by above-mentioned code table；M is the length of check bit part, is 25920.Initializing all address dates of RAM is
Bit 0.
Step 3：First information bit λ of encoder serial input0Respectively with the number of the An addresses read in 19 RAM
According to doing mould 2 plus computing, and result restored again in the reading address An of 19 RAM, i.e.,Wherein, An is
The 1st column matrix information (i.e. the location index of " 1 " in row) read from code table, is herein the line1 in LDPC code table：113
1557 3316 5680 6241 10407 13404 13947 14040 14353 15522 15698 16079 17363
19374 19543 20530 22833 24339。
Step 4：For 359 information bit λ behind encoder serial inputm, m=1 ..., 359, equally respectively with
The data of the Am addresses read in 19 RAM do mould 2 plus computing, and result are restored again in the reading address Am of 19 RAM,
I.e.Wherein, Am is the position for calculating " 1 " in the row drawn by An according to the reckoning relation of encoder matrix
Index, presetting reckoning mode herein is：
Am=(An+m*25920/360) mod (25920), wherein m=1 ..., 359.
Step 5：The the i-th * 360+1 information bits (i=1,2 ..., 107) inputted similarly, for encoder serial,
Respectively according to described in step 3, the data with being read in respective column weight RAM do mould 2 plus computing parallel, the address for reading RAM be from
The location index that i+1 row is read in code table；Then result is write back parallel in the former reading addresses of corresponding RAM.
Step 6：For encoder serial input the i-th * 360+j information bits (i=1,2 ..., 107, j=2,
3 ..., 359), respectively according to described in step 4, parallel to read row weight RAM, it is according to Am=(An+t*25920/ to read address
360) mod (25920), wherein t=1 ..., 359 reckoning address, mould 2 plus computing are done with information bit, then result back into correspondence
The former of RAM is read in address.
Step 7：After full detail bit serial inputs, the check bit that is stored in the RAM of 19 1*25920 depth
Intermediate result is denoted as：
(p1,0, p1,1, p1,2..., p1,25919, p2,0, p2,1, p2,2..., p2,25919..., p19,0, p19,1,
p19,2..., p19,25919),
, this 19 RAM (read address increases successively according to order from low to high) is read parallel, by the output of 19 RAM
Data do nodulo-2 addition, and the output result of modulo 2 adder and 19 RAM outputs result of next time are done nodulo-2 addition again, so that
25920 check bits are obtained, are shown below：
It is to complete the generation of LDPC coding checkout codes by above-mentioned 7 steps.
From the point of view of summarizing, using in the present embodiment LDPC coding methods, by by the quantity of coded stack be arranged to by with
The maximum column of encoder matrix weighs N to determine, is 19 RAM, using building method of the present invention and other two schemes
The RAM resources and the comparison result of computing relay consumed is as shown in table 1：
1 result deck watch of table
From the comparing result of table 1, the maximum column according to encoder matrix rationally determines the quantity of coded stack again,
Consumption RAM resources can be greatly reduced；And encoder output delay is smaller, in addition, change LDPC coding codewords will not make
Whole design is made a new start, and is only made the appropriate adjustments.
It will be understood to one skilled in the art that the specification of the above is only one kind in the numerous embodiments of the present invention
Or several embodiments, and not use limitation of the invention.Any equivalent change for embodiment described above, modification with
And the technical solution such as equivalent substitute, as long as meeting the spirit of the present invention, will all fall in claims of the present invention
In the range of protecting.
Claims (8)
1. a kind of LDPC coding methods, comprise the following steps：
Designed for carrying out the LDPC encoder matrixs of LDPC codings；
Coded stack RAM is initialized, the column matrix of the information bit part of serial input and each row of encoder matrix is believed
Breath carries out computing successively respectively, and gained operation result is deposited at coded stack and is used for output verification bit section；
Wherein, the quantity of the coded stack is determined by the maximum column weight N with the encoder matrix,
The LDPC encoder matrixs are designed, including：
The encoder matrix is arranged as unit using L, is divided into some sub- column matrix；
First row matrix information is provided by LDPC code table in sub- column matrix, and follow-up adjacent column matrix information is by first row matrix information
Drawn by default reckoning mode.
2. LDPC coding methods as claimed in claim 1, it is characterized in that,
Wherein, the LDPC code table is designed, including：
The LDPC code table is made of i row address informations, which provides 1 in LDPC encoder matrix (i-1) * L+1 row
Location index.
3. LDPC coding methods as claimed in claim 1, it is characterized in that,
Wherein, presetting reckoning mode is：
An is the 1st column matrix information read from code table；
Am is to calculate the column matrix information i.e. location index of " 1 " in the follow-up adjacent column drawn by An；
M is check bit partial-length；
L is the predetermined row length of size, that is, sub- column matrix of submatrix in the encoder matrix；
M is that row sequence number subtracts 1 in sub- column matrix, i.e. m=1 ..., L-1；
It can obtain：Am=(An+m*M/L) mod (M).
4. LDPC coding methods as claimed in claim 1, it is characterized in that,
Wherein, information bit sequence of partial sums matrix information does computing mode and adds for mould 2.
5. LDPC coding methods as claimed in claim 1, it is characterized in that,
Wherein, after full detail bit serial inputs, N number of check bit intermediate results of operations and modulo 2 adder are read
Output result does mould 2 plus computing, wherein, the initial results of modulo 2 adder are bit 0, so as to obtain M check bit part.
6. the LDPC coding methods as described in claim 1 or 2 or 3, it is characterized in that,
Wherein, the size L of submatrix is to be based on information bit partial-length K and check bit partial-length in the encoder matrix
M, and the encoder matrix size come it is definite.
7. LDPC coding methods as claimed in claim 1, it is characterized in that,
Wherein, the storage depth of the coded stack is M, width 1, the storage depth by the check bit part length
Degree M is determined.
8. LDPC coding methods as claimed in claim 1, it is characterized in that,
LDPC encoder further includes, and the check bit part of output and information bit part are spliced and combined.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114157307A (en) * | 2021-12-06 | 2022-03-08 | 江苏正赫通信息科技有限公司 | Hardware implementation method and device for quasi-cyclic LDPC coding |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101192833A (en) * | 2006-11-28 | 2008-06-04 | 华为技术有限公司 | A device and method for low-density checksum LDPC parallel coding |
| CN101335592A (en) * | 2008-08-04 | 2008-12-31 | 北京理工大学 | High speed LDPC decoder implementing method based on matrix block |
| CN101800627A (en) * | 2010-03-16 | 2010-08-11 | 北京海格神舟通信科技有限公司 | Hardware implementation of multiple-code-rate-compatible high-speed low-density parity-check code encoder |
| CN101951264A (en) * | 2010-08-31 | 2011-01-19 | 宁波大学 | Multiple-rate, quasi-cycling and low density decoder for parity check codes |
| CN102377437A (en) * | 2010-08-27 | 2012-03-14 | 中兴通讯股份有限公司 | Method and device for coding quasi-cyclic low density parity check codes |
| EP2667512A1 (en) * | 2011-01-21 | 2013-11-27 | Panasonic Corporation | Encoding method, and decoding method |
| CN104821831A (en) * | 2015-03-24 | 2015-08-05 | 东南大学 | Dual cycle construction method suitable for high code rate quasi cyclic-low density parity check (QC-LDPC) code |
| WO2016137253A1 (en) * | 2015-02-27 | 2016-09-01 | 한국전자통신연구원 | Parity puncturing device for fixed-length signaling information encoding, and parity puncturing method using same |
-
2016
- 2016-10-17 CN CN201610905209.1A patent/CN107959502B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101192833A (en) * | 2006-11-28 | 2008-06-04 | 华为技术有限公司 | A device and method for low-density checksum LDPC parallel coding |
| CN101335592A (en) * | 2008-08-04 | 2008-12-31 | 北京理工大学 | High speed LDPC decoder implementing method based on matrix block |
| CN101800627A (en) * | 2010-03-16 | 2010-08-11 | 北京海格神舟通信科技有限公司 | Hardware implementation of multiple-code-rate-compatible high-speed low-density parity-check code encoder |
| CN102377437A (en) * | 2010-08-27 | 2012-03-14 | 中兴通讯股份有限公司 | Method and device for coding quasi-cyclic low density parity check codes |
| CN101951264A (en) * | 2010-08-31 | 2011-01-19 | 宁波大学 | Multiple-rate, quasi-cycling and low density decoder for parity check codes |
| EP2667512A1 (en) * | 2011-01-21 | 2013-11-27 | Panasonic Corporation | Encoding method, and decoding method |
| WO2016137253A1 (en) * | 2015-02-27 | 2016-09-01 | 한국전자통신연구원 | Parity puncturing device for fixed-length signaling information encoding, and parity puncturing method using same |
| CN104821831A (en) * | 2015-03-24 | 2015-08-05 | 东南大学 | Dual cycle construction method suitable for high code rate quasi cyclic-low density parity check (QC-LDPC) code |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114157307A (en) * | 2021-12-06 | 2022-03-08 | 江苏正赫通信息科技有限公司 | Hardware implementation method and device for quasi-cyclic LDPC coding |
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