CN102315899A - Quasi-cyclic decoding method for low-density parity check code - Google Patents

Abstract

The invention discloses a quasi-cyclic decoding method for a low-density parity check code, which comprises the following steps: transposing the determinant position of a check array, converting a check array based on an irregular repeated accumulation low-intensity parity check code into a quasi-cyclic check array based on a quasi-cyclic low-intensity parity check code, and then converting the irregular repeated accumulation low-intensity parity check code in a second generation digital television broadcasting system into the quasi-cyclic low-intensity parity check code based on a cyclic shift matrix, so as to achieve the configurable hardware decoding of a semi-parallel quasi-cyclic structure. By utilizing the method, the irregular repeated accumulation low-intensity parity check code in the second generation digital television broadcasting system is converted into the quasi-cyclic low-intensity parity check code based on the cyclic shift matrix, so as to achieve the decoding of the quasi-cyclic structure of the parity check code, and the configurable decoding of various code-rate codes in the second digital television broadcasting system is achieved.

Description

A kind of accurate circulation interpretation method of low density parity check code

Technical field

The present invention relates to the channel coding/decoding technical field, relate in particular to a kind of in second generation digital television broadcasting system the accurate circulation interpretation method of low density parity check code.

Background technology

Channel coding technology is as the basic fundamental that guarantees the communication system reliable transmission; Obtaining develop rapidly over past ten years; With Turbo code, low density parity check code (LDPC sign indicating number) is that chnnel coding that large quantities of performances of representative can the approximation theory limit comes to light in succession and obtains further investigation, and wherein the LDPC sign indicating number had especially obtained concern in recent years, in the formulation of each item communication standard; It is extensively thought to replace Turbo code, becomes the main channel coding schemes of next generation communication system.

But the LDPC sign indicating number with it near the excellent properties of shannon limit and the decoding architecture of parallel decoding; Obtained extensive favor; Become the chnnel coding of selecting for use of second generation digital television broadcasting (DVB-S2), CMMB (CMMB) and DTTB communication standards such as (DTMB), and more and more widely used in the communications field.

In these standards, (Quasi-cyclic LDPC, QC-LDPC) sign indicating number becomes one of at present most popular chnnel coding with its decoding threshold and parallel decoding architecture that approaches shannon limit to quasi-cyclic LDPC.QC-LDPC code check matrix H has following structure:

Wherein, I (q _{I, j}) be cyclic shift matrices or the full null matrix of p * p, 0≤i＜m, 0≤j＜n.Cyclic shift matrices I (q _{I, j}) by all elements ring shift right q among the unit matrix I _{I, j}(0≤q _{I, j}＜p) position constitutes.This low-density accurate cyclic check matrix makes chnnel coding have accurate preferably loop structure, is easy to hardware and realizes.

In order to adapt to the general requirement of future communications system, design an a kind of focus that is applicable to that simultaneously various Different L DPC sign indicating number decoders for decoding become research and realize.Because the normal structure of QC-LDPC sign indicating number makes various QC-LDPC sign indicating number to decipher with general decoder.This decoder has simple decoding architecture, can realize the general decoding of two-forty and low consumption of resources, makes the common application of QC-LDPC obtain significant progress.

Yet, the DVB-S2 standard of extensive use at present, the chnnel coding LDPC sign indicating number that it adopts is a kind of non-rule repeat to add up LDPC (irregular repeat-accumulate LDPC, IRA-LDPC) sign indicating number.In the M of this type IRA-LDPC sign indicating number * N verification battle array, M=mp, N=np, its structure is following:

H＝[A ₀，A ₁，…，A _n-m-1，B]

The right matrix B of wherein verification battle array is the dual diagonal matrix of a M * M; Left side matrix A _i(0≤i＜m) is the matrix of M * p, and its 1st row confirm with certain algorithm, thereafter p-1 be listed as by the 1st row one by one circulation to move down the M/p position definite.

This IRA-LDPC sign indicating number does not have quasi-cyclic structure, can't decipher with traditional shared a kind of decoding architecture of QC-LDPC sign indicating number while, and this has just brought difficulty for the General design of ldpc code decoder.

Summary of the invention

The technical problem that (one) will solve

In view of this, in order to overcome the deficiency of prior art, main purpose of the present invention is to provide a kind of accurate circulation interpretation method of IRA-LDPC sign indicating number of DVB-S2 standard.

(2) technical scheme

For achieving the above object; The invention provides a kind of accurate circulation interpretation method of low density parity check code; This method comprises: transposing verification battle array ranks position; To be transformed to accurate cyclic check battle array based on non-rule repeat the to add up verification battle array of low density parity check code based on quasi-cyclic low-density parity check codes; Then according to this accurate cyclic check battle array, convert the low density parity check code that repeats to add up of the non-rule in the second generation digital television broadcasting system to quasi-cyclic low-density parity check codes based on cyclic shift matrices, realize the hardware decoding of configurable half parallel accurate loop structure.

In the such scheme; Said transposing verification battle array ranks position; To be transformed to accurate cyclic check battle array based on non-rule repeat the to add up verification battle array of low density parity check code, specifically comprise: at first change the column position that former non-rule repeats right-hand double diagonal line battle array of total check battle array, change the line position of whole verification battle array then based on quasi-cyclic low-density parity check codes; Make the accurate circulationization of verification battle array, with the verification battle array conversion cyclic check battle array that is as the criterion.

In the such scheme; The former non-rule of said transposing repeats the column position of right-hand double diagonal line battle array of total check battle array; Before transposing,, change the 0th row rightmost 0 of the dual diagonal matrix B of this verification battle array into 1, obtain the Matrix C of M * M size for the LDPC code check battle array H of second generation digital television broadcasting system standard; Wherein each row of C move down a formation by the previous column circulation, and M is the line number of verification battle array H.

In the such scheme; Matrix C to M * M; According to the 0th, M/p, 2M/p ..., (p-1) M/p, 1, M/p+1,2M/p+1 ..., (p-1) M/p+1 ..., M/p-1, M/p+ (M/p-1), 2M/p+ (M/p-1) ..., the order of (p-1) M/p+ (M/p-1) row carries out rearrangement, obtains the matrix D of a new M * M; The every p of this matrix D classifies 1 group as, and its 1st row confirm with certain algorithm, thereafter p-1 classify these p row as the 1st row one by one circulation move down the M/p position and confirm, be i.e. matrix D=[A _N-m, A _N-m+1..., A _N-1], A wherein _i(n-m≤i＜n) is the matrix of M * p, and its 1st row confirm with certain algorithm, thereafter p-1 be listed as by the 1st row one by one circulation to move down the M/p position definite.

In the such scheme, the former non-rule of said transposing repeats the column position of right-hand double diagonal line battle array of total check battle array, after transposing, obtains new verification battle array H ₁=[A ₀, A ₁..., A _N-m-1, D]=[A ₀, A ₁..., A _N-1], A wherein _i(0≤i＜n) is the matrix of M * p, and its 1st row confirm with certain algorithm, thereafter p-1 be listed as by the 1st row one by one circulation to move down the M/p position definite.

In the such scheme, with matrix H ₁According to the 0th, M/p, 2M/p ..., (p-1) M/p, 1, M/p+1,2M/p+1 ..., (p-1) M/p+1 ..., M/p-1, M/p+ (M/p-1), 2M/p+ (M/p-1) ..., the order of (p-1) M/p+ (M/p-1) row carries out rearrangement, obtains verification battle array H ₂This verification battle array H ₂Be made up of cyclic shift matrices piece one by one, the size of each cyclic shift matrices piece is p * p, and each provisional capital is to be made up of one of previous row ring shift right in the piece; It is check matrix H ₂Structure following:

Wherein, Z _{I, j}(0≤i＜m, 0≤j＜n) are cyclic shift matrices or the full null matrix of p * p, cyclic shift matrices Z _{I, j}In each provisional capital be to constitute by one of previous row ring shift right.

In the such scheme, the line position of the whole verification battle array of said transposing, the matrix after the transposing is cyclic shift matrices Z _{I, j}(0≤i＜m, 0≤j＜n), this cyclic shift matrices Z _{I, j}In 1 position use side-play amount p _{I, j}(0≤i＜m, 0≤j＜n) represent, wherein p _{I, j}Be Z _{I, j}In 1 position of first row.

In the such scheme, said accurate cyclic check battle array is H ₂, its half parallel decoder device comprises channel information input module, channel information memory module, external information memory module, decode results memory module, decode results output module, decoding information configuration ROM module, rotary module and and long-pending operation group module.

In the such scheme, said channel information input module is with the channel information U=[u of input ₀, u ₁..., u _N-m-1, s] and be arranged in U again ₂=[u ₀, u ₁..., u _N-1], the channel information of decoding input is designated as U=[u ₀, u ₁..., u _N-m-1, s], u wherein _i(0≤i＜m) is ip～[(i+1) p-1] individual input channel information, and s is the individual input channel information of (n-m) p～(np-1); With channel information s according to the 0th, M/p, 2M/p ..., (p-1) M/p, 1, M/p+1,2M/p+1 ..., (p-1) M/p+1 ..., M/p-1, M/p+ (M/p-1), 2M/p+ (M/p-1) ..., the individual order of (p-1) M/p+ (M/p-1) carries out rearrangement, obtains the matrix t of 1 a new * M; The every p of matrix t classifies 1 group as, i.e. matrix t=[u _N-m, u _N-m+1..., u _N-1], then obtain the channel information U that resets ₂=[u ₀, u ₁..., u _N-1], u wherein _i(0≤i＜n) is a p input channel information of i sub-block; This decoder device is according to the channel information U that resets ₂Decipher.

In the such scheme, said channel information memory module is with channel information U ₂By sub-piece u _i(0≤i＜n) preserve, the channel information of each sub-block is kept in the same address.

In the such scheme, said external information memory module is preserved the external information of decoding computing output, and p external information preserved in each address, and this p external information is corresponding to same cyclic shift matrices; For a cyclic shift matrices block size is the general verification battle array of p * p, and all there is its corresponding p cyclic shift sample elements in any one 1 element in the loop blocks; Every p relevant cyclic shift sample lined up 1 row from small to large by row-coordinate (row coordinate), make as a whole 1 memory cell that takies, having constituted with p relevant cyclic shift sample is the external information storage organization of basic unit of storage; All basic stored information unit according to the position of piece in the verification battle array, place from left to right, from top to bottom serial number, put into the memory cell of appropriate address by its numbering; The data of external information storage are according to every capable piece block-by-block, the sequential storage of piece line by line: the p of each memory cell relevant cyclic shift sample arranged according to row-coordinate from small to large; The data of different memory cell are according to every capable piece block-by-block, the sequence arrangement of piece line by line.

In the such scheme, said decode results memory module is preserved the decoding decision bit, and the decoding decision bit of each sub-block is kept in the same address.

In the such scheme, said decode results output module will be deciphered the preceding N-M bit output of decision bit, as the decode results of decoder.

In the such scheme, the side-play amount p of said decoding information configuration ROM module stores cyclic shift matrices _{I, j}And positional information, supply decoding configuration to use.

In the such scheme; Said positional information is the addressing address of cyclic shift matrices; The construction method of this addressing address is following: with all basic stored information unit according to the position of piece in the verification battle array, place from top to bottom, from left to right serial number, by its position in information memory cell outside of its numbering addressing, this position is address number; Then these address numbers are lined up one by one, be its addressing information.

In the such scheme, said rotary module is according to p the external information [v of the offset information r among the ROM with input _{K, 0}, v _{K, 1}..., v _{K, p-1}] cyclic shift is [v _{K, r}, v _{K, r+1}..., v _{K, p-1}, v _{K, 0}, v _{K, 1}..., v _{K, r-1}], the value of r is p during wherein with computing _{I, j}, the value of r is p-1-p when amassing computing _{I, j}

In the such scheme, said and long-pending operation group module comprises p and long-pending arithmetic unit unit, realizes the parallel and long-pending computing in p road, wherein carries out the long-pending computing of serial and computing and serial respectively with long-pending arithmetic unit unit; When carrying out serial and computing with long-pending arithmetic element, serial input channel information u _0iWith external information v _Ki, obtain itself and the external information of computing, the external information v that parallel series output is upgraded _IjWith decoding hard decision d _iWhen amassing computing with the execution serial of long-pending arithmetic unit unit, serial input external information v _Kj, obtain the external information of its long-pending computing, the external information external information v that parallel series output is upgraded _Ji

(3) beneficial effect

Can find out that from technique scheme the present invention has following beneficial effect:

1, the present invention converts the non-accurate loop structure IRA-LDPC sign indicating number in the second generation digital television broadcasting system to a kind of QC-LDPC sign indicating number based on cyclic shift matrices, thereby has realized the decoding of its accurate loop structure.

2, the Card read/write form of external information storage organization of the present invention only by the decision of the information in the decoding information configuration ROM, does not need extra addressing route controlling mechanism.For different QC-LDPC code check matrixes; As long as effective cyclic shift matrices piece number of its verification battle array and the maximum set value that cyclic shift matrices size parameter p is not more than hardware just can be accomplished the replacing of sign indicating number through indirect addressing address among the change ROM and cycle offset; In the replacing process, other memory cell and addressing routing interface all remain unchanged.The decoding architecture that this external information memory cell and addressing routing interface are fixing has constituted the core based on the general decoder of cyclic shift matrices.

3, arithmetic element of the present invention and long-pending realizes the serial process to data, makes arithmetic unit to all being suitable for node and long-pending node of various different dimensions, so constituted general and long-pending arithmetic element.In the actual hardware, generally realization is the minimum-sum algorithm of revising, and only need get final product at the pretreatment unit of adding that inputs or outputs that amasss arithmetic element this moment, so this arithmetic unit still is suitable under correction algorithm.

4, decoding architecture of the present invention, its characteristic only are decided by loop blocks size parameter p, and be irrelevant with parameter such as code length code check; Different verification battle arrays only is embodied in the different of indirect addressing address and cyclic shift amount information in the decoding information configuration ROM table, so this structure is common to various LDPC sign indicating numbers with same loop block size.Through the indirect addressing address information and the cyclic shift amount information of the various different code rate LDPC codes of ROM table storage, can realize the hardware designs of various different code rate LDPC codes.

Description of drawings

Fig. 1 is a decoder architecture;

Fig. 2 is the accurate cyclical-transformation instance of IRA-LDPC code check battle array;

Fig. 3 is general external information memory cell examples;

Fig. 4 is a ROM configuration information instance;

Fig. 5 is serial and long-pending arithmetic unit unit instance.

Embodiment

For making the object of the invention, technical scheme and advantage clearer, below in conjunction with specific embodiment, and with reference to accompanying drawing, to further explain of the present invention.

Basic ideas of the present invention are; Transposing verification battle array ranks position; To be transformed to accurate cyclic check battle array based on non-rule repeat the to add up verification battle array of low density parity check code based on quasi-cyclic low-density parity check codes; Then according to this accurate cyclic check battle array, convert the low density parity check code that repeats to add up of the non-rule in the second generation digital television broadcasting system to quasi-cyclic low-density parity check codes based on cyclic shift matrices, realize the hardware decoding of configurable half parallel accurate loop structure.

To combine accompanying drawing and embodiment to describe the present invention below.

Embodiment one: the accurate circulationization of check matrix

Fig. 2 is 1 representative instance of IRA-LDPC sign indicating number, and M=12 wherein, N=24, p=4, the 0th, 4,8 row of H confirm at random, 1-3,5-7,9-11 row be respectively the 0th, 4,8 row one by one circulation move down 3 formations.

Change the 0th row rightmost 0 of the dual diagonal matrix B of former verification battle array into 1, constitute Matrix C, then each row of C move down a formation by the previous column circulation.To Matrix C according to the 0th, 3,6,9,1,4,7,10,2,5,8,11 row order carry out rearrangement, obtain a new M * N verification battle array D.Per 4 row of this verification battle array constitute 1 group, back 3 row in 4 row by the 1st row of these 4 row one by one circulation move down 3 and constitute.

Matrix D is replaced the matrix B in the matrix H, then constitute matrix H ₁Matrix H ₁Order according to the 0th, 3,6,9,1,4,7,10,2,5,8,11 row carries out rearrangement, then new verification battle array H ₂Be made up of cyclic shift matrices piece one by one, the size of each cyclic shift matrices piece is 4 * 4, and each provisional capital is to be made up of one of previous row ring shift right in the piece.

Embodiment two: the external information storage format

Check matrix with Fig. 2 is an example, establish (x, y) external information of 1 correspondence that x is capable, y is listed as of verification battle array is stored in expression, and then the external information storage format of the verification battle array of Fig. 2 is as shown in Figure 3.

The data of storing among Fig. 3 are according to every capable piece block-by-block, the sequential storage of piece line by line: the p of each memory cell relevant cyclic shift sample arranged according to row-coordinate from small to large; The data of different memory cell are according to every capable piece block-by-block, the sequence arrangement of piece line by line.

Be example when amassing computing with Fig. 3, carry out external information according to the storage format of Fig. 3 and upgrade.0～No. 5 memory cell of series read-out at first, and p=4 external information of each memory cell be input to respectively in the long-pending arithmetic element of p serial.After No. 5 memory cell of input, p the long-pending arithmetic element of serial traveled through Fig. 2 check equations H respectively ₂All external informations of 0～(p-1) row, so can accomplish these capable long-pending computings.After p the long-pending arithmetic element of serial accomplished computing, the external information of upgrading according to input order serial output, is written to memory cell respectively the 0th～No. 5, promptly accomplishes the external information of 0～No. 5 memory cell of form 1 and upgrade.In like manner, can accomplish the external information of 6～No. 19 memory cell of form 1 successively and upgrade, promptly accomplish 1 long-pending computing of all check equations.In like manner, when carrying out, can carry out reading and writing data, can accomplish the external information of 0～No. 19 memory cell successively and upgrade, promptly accomplish 1 time and computing of check matrix according to the indirect addressing address in the decoding information configuration ROM with computing.

Embodiment three: the configuration information of decoding information configuration ROM

Carry out the external information read-write according to Fig. 3 during actual decoding, when then amassing computing, reading and writing data is according to address increment in sequence; And when carrying out with computing; Then need according to every row piece block-by-block, by the sequential addressing of row piece; So with all basic stored information unit according to the position of piece in the verification battle array, place from top to bottom, from left to right serial number; By its position (address number) in information memory cell outside of its numbering addressing, these address numbers are lined up one by one, be its addressing information.The indirect addressing address and the cycle offset that provide wherein carry out reading and writing data.These indirect addressing addresses and cycle offset can use a ROM to preserve.Side-play amount p wherein _{I, j}Be Z _{I, j}In 1 position of first row.External information stored ROM configuration information such as Fig. 4 of Fig. 3.

Embodiment four: the decoder instance

According to the channel information U that resets ₂With accurate cyclic check battle array H ₂, decoder architecture such as Fig. 1 that it is partly parallel.Decoder comprises channel information input module, channel information memory module, external information memory module, decode results memory module, decode results output module, decoding information configuration ROM module, rotary module and decoding and long-pending operation group module.

Wherein the channel information input module is with the channel information U=[u of input ₀, u ₁..., u _N-m-1, s] and be arranged in U again according to step 6 ₂=[u ₀, u ₁..., u _N-1].The channel information memory module is with channel information U ₂By sub-piece u _i(0≤i＜n) preserve, the channel information of each sub-block is kept in the same address.The external information memory module is preserved the external information of decoding computing output, and p external information preserved in each address, and this p external information is corresponding to same cyclic shift matrices.The decode results memory module is preserved the decoding decision bit, and the decoding decision bit of each sub-block is kept in the same address.The decode results output module will be deciphered the preceding N-M bit output of decision bit, as the decode results of decoder.The side-play amount p of the cyclic shift matrices of decoding information configuration ROM module stores step 5 _{I, j}And positional information (being its addressing address), supply decoding configuration to use.Rotary module is according to p the external information [v of the offset information r in the decoding information configuration ROM with input _{K, 0}, v _{K, 1}..., v _{K, p-1}] cyclic shift is [v _{K, r}, v _{K, r+1}..., v _{K, p-1}, v _{K, 0}, v _{K, 1}..., v _{K, r-1}], wherein and during computing (VNU), the value of r is p _{I, j}, when amassing computing (CNU), the value of r is p-1-p _{I, j}Comprise p and long-pending operator block with long-pending operation group module, realize the parallel and long-pending computing in p road.

In the decode procedure, when carrying out with computing, decoding information configuration ROM order is by shooting exported indirect addressing address and cycle offset.The external information memory cell is read a data set [v according to the addressing address among the ROM _{K, 0}, v _{K, 1}..., v _{K, p-1}].Rotary module rotates to the external information of the p in these data the form of the ascending arrangement of row coordinate according to the cycle offset of ROM output.P channel information of this p external information and channel information block output after this carries out and computing through p serial and arithmetic element VNU.After completion and the computing, p external information is written to the address when reading, and p decoding hard decision di writes decode results storage RAM module simultaneously; So analogize,, promptly accomplish once and decoding up to the renewal of the external information of accomplishing all addresses.Equally; When amassing computing; Rotary module according to address order output from small to large, and rotates to the form of the ascending arrangement of capable coordinate according to the corresponding cycle offset in current address with p external information of external information module output, amasss computing via the long-pending arithmetic element CNU completion of p serial.Like this and long-pending arithmetic element iterates, and can accomplish decoding.

Embodiment five: with long-pending arithmetic unit unit instance

With the unit execution of long-pending arithmetic unit and computing and long-pending computing

$v_{\mathrm{ij}}=(u_{0i}+\underset{k=1}{\overset{d_i^v}{\mathrm{\Σ}}}{v}_{\mathrm{ki}})-v_{\mathrm{ji}}=\mathrm{sum}-v_{\mathrm{ji}},$ $v_{\mathrm{ji}}=[\underset{k=1}{\overset{d_j^c}{\mathrm{\Π}}}\mathrm{sgn}\left(v_{\mathrm{kj}}\right)\·\mathrm{sgn}\left(v_{\mathrm{ij}}\right)]\underset{k=1,k\≠i}{\overset{d_j^c}{\min }}\left|v_{\mathrm{kj}}\right|$

Its structure is as shown in Figure 5.During with computing, it is input as channel information u _0iWith external information v _Ki, be output as the external information v of renewal _IjWith decoding hard decision d _iIn the arithmetic element, add up/comparator carries out accumulating operation, following formula is accomplished in serial and computing; Subtract/comparator execution subtraction the subtraction in the perfect; Buffer and FIFO accomplish respectively accumulation result sum and external information v _JiTemporary.Initial index signal realize to add up/comparator reset translation quantity signal scaling v _JiThe temporary time.When initial index signal is effective, the translation number signal effectively and the translation number signal equal d _i ^v, adding up/the comparator initialization, accumulation result sum is u _0iAnd v _KiWith, then add up/comparator is to remaining (d _i ^v-1) individual v _KiAdd up, effective up to the initial index signal of the next one; Meanwhile, external information is to move among the FIFO of translation quantity at depth value; When the initial index signal of the next one was effective, accumulation result sum deposited in the buffer, and FIFO begins output simultaneously; Subtract at this moment ,/comparator deducts the sum value of depositing in the buffer output v of FIFO _Ji, promptly obtain the external information v that upgrades _Ij, the symbol of sum is decode results d simultaneously _iWhen amassing computing, it is input as external information v _Kj, be output as the external information v of renewal _JiIn the arithmetic element, add up/comparator execution comparison operation output | v _Kj| minimum value and time minimum M in&SubMin and v _KjSymbol and SgnSum, and be deposited with in the buffer; FIFO keeps in external information v _KjAbsolute value and symbol, and export after the clock cycle in translation quantity by the mode of FIFO.Subtract/comparator with the output of minimum M in that deposits in the buffer and FIFO relatively, if Min equates v then with the output of FIFO _JiAbsolute value equal time minimum value SubMin, otherwise v _JiAbsolute value equal minimum M in, and v _JiSymbol by the output symbol s of the symbol in the buffer and SgnSum and FIFO _KjXOR obtains.Initial index signal realize to add up/comparator reset translation quantity signal scaling | v _Kj| and s _KjDeposit the time.

Above-described specific embodiment; The object of the invention, technical scheme and beneficial effect have been carried out further explain, and institute it should be understood that the above is merely specific embodiment of the present invention; Be not limited to the present invention; All within spirit of the present invention and principle, any modification of being made, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.

Claims (17)

1. the accurate circulation interpretation method of a low density parity check code; It is characterized in that; This method comprises: transposing verification battle array ranks position; To be transformed to accurate cyclic check battle array based on non-rule repeat the to add up verification battle array of low density parity check code based on quasi-cyclic low-density parity check codes; Then according to this accurate cyclic check battle array, convert the low density parity check code that repeats to add up of the non-rule in the second generation digital television broadcasting system to quasi-cyclic low-density parity check codes based on cyclic shift matrices, realize the hardware decoding of configurable half parallel accurate loop structure.

2. the accurate circulation interpretation method of low density parity check code according to claim 1; It is characterized in that; Said transposing verification battle array ranks position; To be transformed to accurate cyclic check battle array based on non-rule repeat the to add up verification battle array of low density parity check code, specifically comprise based on quasi-cyclic low-density parity check codes:

At first change the column position that former non-rule repeats right-hand double diagonal line battle array of total check battle array, change the line position of whole verification battle array then, make the accurate circulationization of verification battle array, with the verification battle array conversion cyclic check battle array that is as the criterion.

3. the accurate circulation interpretation method of low density parity check code according to claim 2; It is characterized in that the former non-rule of said transposing repeats the column position of right-hand double diagonal line battle array of total check battle array, before transposing for the LDPC code check battle array H of second generation digital television broadcasting system standard; Change the 0th row rightmost 0 of the dual diagonal matrix B of this verification battle array into 1; Obtain the Matrix C of M * M size, wherein each row of C move down a formation by the previous column circulation, and M is the line number of verification battle array H

4. the accurate circulation interpretation method of low density parity check code according to claim 3; It is characterized in that; Matrix C to M * M; According to the 0th, M/p, 2M/p ..., (p-1) M/p, 1, M/p+1,2M/p+1 ..., (p-1) M/p+1 ..., M/p-1, M/p+ (M/p-1), 2M/p+ (M/p-1) ..., the order of (p-1) M/p+ (M/p-1) row carries out rearrangement, obtains the matrix D of a new M * M; The every p of this matrix D classifies 1 group as, and its 1st row confirm with certain algorithm, thereafter p-1 classify these p row as the 1st row one by one circulation move down the M/p position and confirm, be i.e. matrix D=[A _N-m, A _N-m+1..., A _N-1], A wherein _i(n-m≤i＜n) is the matrix of M * p, and its 1st row confirm with certain algorithm, thereafter p-1 be listed as by the 1st row one by one circulation to move down the M/p position definite.

5. the accurate circulation interpretation method of low density parity check code according to claim 2 is characterized in that, the former non-rule of said transposing repeats the column position of right-hand double diagonal line battle array of total check battle array, after transposing, obtains new verification battle array H ₁=[A ₀, A ₁..., A _N-m-1, D]=[A ₀, A ₁..., A _N-1], A wherein _i(0≤i＜n) is the matrix of M * p, and its 1st row confirm with certain algorithm, thereafter p-1 be listed as by the 1st row one by one circulation to move down the M/p position definite.

6. the accurate circulation interpretation method of low density parity check code according to claim 5 is characterized in that, with matrix H ₁According to the 0th, M/p, 2M/p ..., (p-1) M/p, 1, M/p+1,2M/p+1 ..., (p-1) M/p+1 ..., M/p-1, M/p+ (M/p-1), 2M/p+ (M/p-1) ..., the order of (p-1) M/p+ (M/p-1) row carries out rearrangement, obtains verification battle array H ₂This verification battle array H ₂Be made up of cyclic shift matrices piece one by one, the size of each cyclic shift matrices piece is p * p, and each provisional capital is to be made up of one of previous row ring shift right in the piece; It is check matrix H ₂Structure following:

Wherein, Z _{I, j}(0≤i＜m, 0≤j＜n) are cyclic shift matrices or the full null matrix of p * p, cyclic shift matrices Z _{I, j}In each provisional capital be to constitute by one of previous row ring shift right.

7. the accurate circulation interpretation method of low density parity check code according to claim 2 is characterized in that, the line position of the whole verification battle array of said transposing, and the matrix after the transposing is cyclic shift matrices Z _{I, j}(0≤i＜m, 0≤j＜n), this cyclic shift matrices Z _{I, j}In 1 position use side-play amount p _{I, j}(0≤i＜m, 0≤j＜n) represent, wherein p _{I, j}Be Z _{I, j}In 1 position of first row.

8. the accurate circulation interpretation method of low density parity check code according to claim 2 is characterized in that, said accurate cyclic check battle array is H ₂, its half parallel decoder device comprises channel information input module, channel information memory module, external information memory module, decode results memory module, decode results output module, decoding information configuration ROM module, rotary module and and long-pending operation group module.

9. the accurate circulation interpretation method of low density parity check code according to claim 8 is characterized in that, said channel information input module is with the channel information U=[u of input ₀, u ₁..., u _N-m-1, s] and be arranged in U again ₂=[u ₀, u ₁..., u _N-1], the channel information of decoding input is designated as U=[u ₀, u ₁..., u _N-m-1, s], u wherein _i(0≤i＜m) is ip～[(i+1) p-1] individual input channel information, and s is the individual input channel information of (n-m) p～(np-1); With channel information s according to the 0th, M/p, 2M/p ..., (p-1) M/p, 1, M/p+1,2M/p+1 ..., (p-1) M/p+1 ..., M/p-1, M/p+ (M/p-1), 2M/p+ (M/p-1) ..., the individual order of (p-1) M/p+ (M/p-1) carries out rearrangement, obtains the matrix t of 1 a new * M; The every p of matrix t classifies 1 group as, i.e. matrix t=[u _N-m, u _N-m+1..., u _N-1], then obtain the channel information U that resets ₂=[u ₀, u ₁..., u _N-1], u wherein _i(0≤i＜n) is a p input channel information of i sub-block; This decoder device is according to the channel information U that resets ₂Decipher.

10. the accurate circulation interpretation method of low density parity check code according to claim 9 is characterized in that, said channel information memory module is with channel information U ₂By sub-piece u _i(0≤i＜n) preserve, the channel information of each sub-block is kept in the same address.

11. the accurate circulation interpretation method of low density parity check code according to claim 8; It is characterized in that; Said external information memory module is preserved the external information of decoding computing output, and p external information preserved in each address, and this p external information is corresponding to same cyclic shift matrices; For a cyclic shift matrices block size is the general verification battle array of p * p, and all there is its corresponding p cyclic shift sample elements in any one 1 element in the loop blocks; Every p relevant cyclic shift sample lined up 1 row from small to large by row-coordinate (row coordinate), make as a whole 1 memory cell that takies, having constituted with p relevant cyclic shift sample is the external information storage organization of basic unit of storage; All basic stored information unit according to the position of piece in the verification battle array, place from left to right, from top to bottom serial number, put into the memory cell of appropriate address by its numbering; The data of external information storage are according to every capable piece block-by-block, the sequential storage of piece line by line: the p of each memory cell relevant cyclic shift sample arranged according to row-coordinate from small to large; The data of different memory cell are according to every capable piece block-by-block, the sequence arrangement of piece line by line.

12. the accurate circulation interpretation method of low density parity check code according to claim 8 is characterized in that, said decode results memory module is preserved the decoding decision bit, and the decoding decision bit of each sub-block is kept in the same address.

13. the accurate circulation interpretation method of low density parity check code according to claim 8 is characterized in that, said decode results output module will be deciphered the preceding N-M bit output of decision bit, as the decode results of decoder.

14. the accurate circulation interpretation method of low density parity check code according to claim 8 is characterized in that, the side-play amount p of said decoding information configuration ROM module stores cyclic shift matrices _{I, j}And positional information, supply decoding configuration to use.

15. the accurate circulation interpretation method of low density parity check code according to claim 14; It is characterized in that; Said positional information is the addressing address of cyclic shift matrices; The construction method of this addressing address is following: with all basic stored information unit according to the position of piece in the verification battle array, place from top to bottom, from left to right serial number, by its position in information memory cell outside of its numbering addressing, this position is address number; Then these address numbers are lined up one by one, be its addressing information.

16. the accurate circulation interpretation method of low density parity check code according to claim 8 is characterized in that, said rotary module is according to p the external information [v of the offset information r among the ROM with input _{K, 0}, v _{K, 1}..., v _{K, p-1}] cyclic shift is [v _{K, r}, v _{K, r+1}..., v _{K, p-1}, v _{K, 0}, v _{K, 1}..., v _{K, r-1}], the value of r is p during wherein with computing _{I, j}, the value of r is p-1-p when amassing computing _{I, j}

17. the accurate circulation interpretation method of low density parity check code according to claim 8; It is characterized in that; Said and long-pending operation group module comprises p and long-pending arithmetic unit unit, realizes the parallel and long-pending computing in p road, wherein carries out the long-pending computing of serial and computing and serial respectively with long-pending arithmetic unit unit; When carrying out serial and computing with long-pending arithmetic element, serial input channel information u _0iWith external information v _Ki, obtain itself and the external information of computing, the external information v that parallel series output is upgraded _IjWith decoding hard decision d _iWhen amassing computing with the execution serial of long-pending arithmetic unit unit, serial input external information v _Kj, obtain the external information of its long-pending computing, the external information external information v that parallel series output is upgraded _Ji

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