CN111446971A - Self-adaptive low-density parity check code coding method based on shared submatrix - Google Patents
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- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1148—Structural properties of the code parity-check or generator matrix
- H03M13/1154—Low-density parity-check convolutional codes [LDPC-CC]
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Abstract
The invention discloses a coding method of an adaptive low-density parity check code based on a shared sub-matrix, which is characterized in that L DPC (binary parity check) error correcting codes with different code word lengths need to construct check matrixes with different sizes, and hardware cost and complexity are increased.
Description
Technical Field
The invention belongs to the technical field of solid-state disk storage, and particularly relates to a self-adaptive low-density parity check code encoding method based on a shared sub-matrix.
Background
Flash memory has the advantages of non-volatility, large capacity and the like and is widely used as storage equipment for computers, smart phones and the like. Especially for three-dimensional (3D) stacked flash memory, it has become the mainstream mass storage device at present.
In order to improve the data storage reliability, low-Density Parity Check (L ow Density Parity Check, L DPC for short) is widely used for a 3D stacked flash memory as a mainstream error correction code.
However, in the existing variable length L DPC encoding process, different check matrices are used for encoding, which increases the encoding complexity and hardware implementation overhead.
Disclosure of Invention
In view of the above drawbacks and needs of the prior art, the present invention provides a method for encoding adaptive low density parity check codes based on shared sub-matrices, which is to first construct a check matrix with an information length of 2KB according to the change of the programmable erasure cycle of a flash memory block, and then encode the check matrix with the constructed 2 KB. When the programmable erasing period of the flash memory block exceeds a certain threshold value, a check matrix with the information length of 4KB is constructed, and in the construction process, the check matrix with the information length of 2KB is used as a sub-matrix to carry out row and column expansion so as to construct the check matrix with the information length of 4 KB. The constructed 4KB check matrix contains a 2KB shared sub-matrix, and in the coding process, different check matrices can be adaptively selected for coding according to the change of the flash memory blocks, so that the hardware implementation complexity is reduced, the performance of the flash memory system is improved, and the hardware overhead brought by coding is saved. The specific technical scheme is as follows:
a self-adaptive low-density parity check code coding method based on a shared submatrix is applied to a flash memory system and comprises the following steps:
(1) randomly generating L DPC check matrix Q with information length of 2KB by adopting computer search algorithmm×n；
(2) The constructed L DPC check matrix with the information length of 2KB is used as a shared sub-matrix to construct a L DPC check matrix with the information length of 4KB, the specific construction rule is to expand the row and column of the shared sub-matrix, and the expansion rule is to randomly generate a sum sub-matrix QijMatrices of the same size containing only 0 or 1 elements;
(3) the upper host sends a sequential write command to the flash memory controller, and the controller judges whether the programmable erase-write cycle exceeds a threshold value according to the recorded number of the programmable erase-write cycle times of the flash memory block;
(4) if the programmable erasing cycle number is less than the threshold value;
(5) using the information length 2KB as an error correction unit, and selecting a check matrix with the information length 2KB to perform L DPC operation;
(6) if the programmable erasing cycle number is larger than the threshold value;
(7) the information length of 4KB is taken as an error correction unit, and a check matrix with the information length of 4KB is selected for carrying out L DPC operation.
Further, the check matrix form in the step (1) is:
wherein Q isij(i is more than or equal to 1 and less than or equal to m, j is more than or equal to 1 and less than or equal to n) is a quasi-cyclic check submatrix only containing 0 and 1 elements.
Further, the check matrix with the information length of 4KB constructed in the step (2) is:
further, in the step (3), the programmable erase/write cycle threshold of the flash block is 7000 times.
Further, the specific encoding rule in the step (5) is as follows:
wherein I2kRepresenting a bit stream having an information length of 2 KB.
Further, the specific encoding rule in the step (7) is as follows:
wherein I4kRepresenting a bit stream with an information length of 4 KB.
In general, compared with the prior art, the technical scheme provided by the invention can achieve the following beneficial effects:
(1) the method of the invention can reduce hardware overhead and complexity brought by L DPC coding.
(2) The invention can adaptively select different check matrixes to code according to the change of the programmable erasing period of the flash memory block, thereby maximally improving the performance of the flash memory system and reducing the space use expense.
(3) The matrix construction rule of the invention is simple and easy to realize by hardware.
Drawings
Fig. 1 is a structural diagram of a design of an adaptive ldpc coding method based on a shared submatrix according to the present invention.
FIG. 2 is a flowchart of an adaptive LDPC code encoding method based on a shared submatrix according to the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention. In addition, the technical features involved in the embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.
The design structure of the invention is shown in fig. 1, when the programmable erasing period of the flash memory block is less than the given threshold, firstly constructing the check matrix with the information length of 2KB, and then carrying out L DPC encoding operation by taking the information length of 2KB as the error correction unit, when the programmable erasing period of the flash memory block is greater than the given threshold, carrying out row-column expansion by taking the check matrix with the information length of 2KB as the shared sub-matrix, constructing the check matrix with the information length of 4KB, and carrying out encoding operation by taking 4KB as the error correction unit.
The invention can adaptively select proper information length as a correction unit according to the change of the programmable erasing period of the flash memory block, maximally save the storage space, improve the performance of the flash memory system and reduce the complexity and the expense of hardware realization.
As shown in fig. 2, the present invention relates to a method for encoding adaptive low density parity check codes based on a shared submatrix, which is applied in a flash memory system and includes the following steps:
(1) randomly generating L DPC check matrix Q with information length of 2KB by adopting computer search algorithmm×nSpecifically, the check matrix is in the form:
wherein Q isij(i is more than or equal to 1 and less than or equal to m, j is more than or equal to 1 and less than or equal to n) is a quasi-cyclic check submatrix only containing 0 and 1 elements.
The method has the advantages that: firstly, the check matrix with the information length of 2KB is constructed, so that the coding and decoding efficiency is improved and the space overhead is reduced when the flash memory has fewer programmable erasing periods.
(2) The constructed L DPC check matrix with the information length of 2KB is used as a shared sub-matrix to construct a L DPC check matrix with the information length of 4KB, the specific construction rule is to expand the row and column of the shared sub-matrix, and the expansion rule is to randomly generate a sum sub-matrix QijMatrices of the same size containing only 0 or 1 elements. Specifically, the constructed check matrix with the information length of 4KB is:
the advantage of this step is that the constructed information length is 2KB and 4KB to construct L DPC check matrix, which accords with the current flash memory error correction requirement, and 2KB and 4KB are widely used in each large flash memory system as the main stream error correction unit.
(3) The upper layer host sends a sequential write command to the flash memory controller, and the controller judges whether the programmable erase-write cycle exceeds a threshold value according to the recorded number of the programmable erase-write cycle times of the flash memory block. Specifically, the programmable erase cycle threshold of the flash block is 7000 times.
The method has the advantages that: according to the change of the programmable erasing cycle times of the flash memory, a proper error correction unit can be adaptively selected for coding.
(4) If the number of programmable erase cycles is less than the threshold 7000.
(5) Using information length 2KB as error correction unit, and selecting check matrix with information length 2KB to make L DPC coding operation.
Wherein I2kRepresenting a bit stream having an information length of 2 KB.
The method has the advantages that: when the programmable erasing cycle number is smaller than a certain threshold, 2KB is selected as an error correction unit, which is beneficial to saving the storage space and improving the coding efficiency and the system performance.
(6) If the number of programmable erase cycles is greater than the threshold 7000.
(7) Using information length 4KB as error correction unit, and selecting check matrix with information length 4KB to make L DPC coding operation.
Wherein I4kRepresenting a bit stream with an information length of 4 KB.
The method has the advantages that when the programmable erasing cycle number is larger than a certain threshold value, 4KB is selected as an error correction unit, the decoding error correction capability can be improved, the calling of L DPC soft decision decoding is reduced, and the use of a soft decision level and the decoding reading delay are favorably reduced.
It will be understood by those skilled in the art that the foregoing is only a preferred embodiment of the present invention, and is not intended to limit the invention, and that any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (6)
1. A method for coding adaptive low density parity check codes based on a shared submatrix, which is applied to a flash memory system, and is characterized by comprising the following steps:
(1) randomly generating L DPC check matrix Q with information length of 2KB by adopting computer search algorithmm×n；
(2) The constructed L DPC check matrix with the information length of 2KB is used as a shared sub-matrix to construct a L DPC check matrix with the information length of 4KB, the specific construction rule is to expand the row and column of the shared sub-matrix, and the expansion rule is to randomly generate a sum sub-matrix QijMatrices of the same size containing only 0 or 1 elements;
(3) the upper host sends a sequential write command to the flash memory controller, and the controller judges whether the programmable erase-write cycle exceeds a threshold value according to the recorded number of the programmable erase-write cycle times of the flash memory block;
(4) if the programmable erasing cycle number is less than the threshold value;
(5) using the information length 2KB as an error correction unit, and selecting a check matrix with the information length 2KB to perform L DPC operation;
(6) if the programmable erasing cycle number is larger than the threshold value;
(7) the information length of 4KB is taken as an error correction unit, and a check matrix with the information length of 4KB is selected for carrying out L DPC operation.
2. The method according to claim 1, wherein the check matrix in step (1) is in the form of:
wherein Q isij(i is more than or equal to 1 and less than or equal to m, j is more than or equal to 1 and less than or equal to n) is a quasi-cyclic check submatrix only containing 0 and 1 elements.
3. The method as claimed in claim 1, wherein the check matrix with information length of 4KB constructed in step (2) is:
4. the adaptive low density parity check code encoding method based on shared submatrix of claim 1, wherein in step (3), the programmable erasure cycle threshold of the flash memory block is set to 7000 times.
5. The method according to claim 1, wherein the specific encoding rule in step (5) is:
wherein I2kRepresenting a bit stream having an information length of 2 KB.
6. The method for encoding adaptive low density parity check code based on shared submatrix as claimed in claim 1, wherein the specific encoding rule in step (7) is:
wherein I4kRepresenting a bit stream with an information length of 4 KB.
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