CN107958841B - Method for processing wafer - Google Patents

Method for processing wafer Download PDF

Info

Publication number
CN107958841B
CN107958841B CN201710951990.0A CN201710951990A CN107958841B CN 107958841 B CN107958841 B CN 107958841B CN 201710951990 A CN201710951990 A CN 201710951990A CN 107958841 B CN107958841 B CN 107958841B
Authority
CN
China
Prior art keywords
wafer
unit
processing
back surface
grinding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201710951990.0A
Other languages
Chinese (zh)
Other versions
CN107958841A (en
Inventor
大山裕辅
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Disco Corp
Original Assignee
Disco Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Disco Corp filed Critical Disco Corp
Publication of CN107958841A publication Critical patent/CN107958841A/en
Application granted granted Critical
Publication of CN107958841B publication Critical patent/CN107958841B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67242—Apparatus for monitoring, sorting or marking
    • H01L21/67253—Process monitoring, e.g. flow or thickness monitoring
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Constituent Portions Of Griding Lathes, Driving, Sensing And Control (AREA)
  • Grinding Of Cylindrical And Plane Surfaces (AREA)

Abstract

A method for processing a wafer is provided, in which all electrode posts are reliably exposed on the back surface of the wafer. A method of processing a wafer having a device formed on a front surface thereof and a plurality of electrode posts embedded therein, the electrode posts extending in a thickness direction of the wafer and reaching a predetermined depth position from the front surface of the wafer, the method comprising the steps of: a holding step of holding the front surface side of the wafer by a holding table; a thinning step of thinning the wafer held by the holding table to a predetermined thickness by processing a back surface side of the wafer; and a determination step of, after the thinning step, taking an image of the back surface of the wafer to generate a taken image, determining whether or not there is an electrode column that is not exposed on the back surface based on the taken image, and if it is determined in the determination step that there is an electrode column that is not exposed on the back surface of the wafer, performing an additional processing step of further thinning the wafer.

Description

Method for processing wafer
Technical Field
The present invention relates to a method for processing a wafer made of a semiconductor or the like.
Background
A wafer having a substantially disk shape with a plurality of devices formed on the front surface thereof is divided into chips having devices such as ICs and LSIs. The plurality of devices are formed on the front surface of the wafer in a plurality of regions defined by the planned dividing lines arranged in a lattice shape. After the plurality of devices are formed, the wafer is processed by a grinding apparatus, a polishing apparatus, or the like from the back surface side to be thinned to a predetermined thickness. The thinned wafer is cut along the lines to be divided by a cutting device or the like and is divided into individual chips.
Chips having devices are widely mounted in various electronic devices such as mobile phones and personal computers. Demands for miniaturization and thinning of various electronic devices have been increasing, and along with this, there have been made studies on miniaturization and thinning of chips, reduction in area required for mounting chips, and the like.
In recent years, as a technique for improving the integration of devices, a technique for stacking and mounting a plurality of chips has been put into practical use. In order to save space for electrical connection between a plurality of stacked chips, a technique for electrically connecting the chips to each other via a through electrode (hereinafter, referred to as an electrode post) embedded in a hole penetrating the chips has been put into practical use. Patent documents 1 and 2 disclose techniques for electrically connecting stacked chips to each other using an electrode post.
The electrode column is formed by forming a hole having a predetermined depth from the front surface of the wafer before the division, for example, and embedding a conductive material in the hole. Then, when the wafer is processed from the back surface and thinned, the bottom of the hole is removed, and the electrode column embedded in the hole is exposed on the back surface side.
Patent document 1: japanese patent laid-open No. 2001-53218
Patent document 2: japanese patent laid-open publication No. 2005-136187
The holes in which the conductive material is embedded are formed to a depth approximately equal to the finished thickness of the finally formed chip, but the depth of each hole varies. Therefore, even if the wafer having a plurality of holes embedded with a conductive material is thinned to a design value by processing the back surface of the wafer by a processing device such as a grinding device, a polishing device, or a cutter cutting device, the bottoms of all the holes cannot be removed, and a part of the electrode posts are not exposed on the back surface side.
Therefore, it is necessary to confirm whether or not all the electrode posts are exposed on the back surface side of the wafer when the wafer is thinned. Conventionally, an operator visually checks the back surface of the wafer, but for this reason, the wafer must be moved from a location where thinning is performed, and further, when additional processing is required, the wafer must be returned to the original location, which complicates the work. Further, there is a problem that the unexposed electrode column is ignored.
Disclosure of Invention
The present invention has been made in view of the above problems, and an object of the present invention is to provide a wafer processing method capable of effectively determining whether or not all of a plurality of electrode columns are exposed on the back surface of a thinned wafer. Further, a wafer processing method is provided, which can reliably detect the presence of unexposed electrode posts and perform additional processing so that all the electrode posts are exposed on the back surface.
According to one aspect of the present invention, there is provided a method of processing a wafer having a device formed on a front surface thereof and a plurality of electrode posts embedded in the wafer, the electrode posts extending in a thickness direction of the wafer and reaching a predetermined depth position from the front surface of the wafer, the method comprising the steps of: a holding step of holding the front surface side of the wafer by using a holding table; a thinning step of thinning the wafer held by the holding table to a predetermined thickness by processing a back surface side of the wafer; and a determination step of, after the thinning step, taking an image of the back surface of the wafer to generate a taken image, determining whether or not there is an electrode column that is not exposed on the back surface based on the taken image, and if it is determined in the determination step that there is an electrode column that is not exposed on the back surface of the wafer, performing an additional processing step of further thinning the wafer.
In one embodiment of the present invention, the determining step may be performed in a state where the wafer is held on the holding table, and the additional processing step may be performed in a state where the wafer is held on the holding table.
According to the method for processing a wafer according to one aspect of the present invention, after the step of thinning the wafer to a predetermined thickness is performed, the back surface of the wafer to be processed can be photographed to generate a photographed image, and the presence or absence of an electrode column not exposed on the back surface can be determined from the photographed image. This determination is performed by, for example, comparing the generated captured image with a captured image in a case where all the electrode columns are exposed. Therefore, compared with the determination by visual observation, accurate determination can be performed in a short time.
Since it can be quickly determined whether or not all the electrode posts are exposed on the back surface side of the wafer, it is quickly determined that additional processing should be performed when the additional processing is necessary. Further, even when the presence or absence of the unexposed electrode column is determined again after the additional processing is performed, the time required for the determination can be shortened.
As a result of this determination, when it is confirmed that all of the electrode posts are exposed on the back surface of the wafer, no additional processing is required. Here, even when it is determined that additional processing is not necessary, it is quickly determined that additional processing is not to be performed, and therefore, the time required until the wafer is sent to the next step is shortened.
In addition, since the captured image captured by the imaging unit included in the processing apparatus is used for the determination, the determination can be made without moving the wafer from the position where the processing has been performed. When the wafer is visually observed, it is necessary to take out the wafer from the processing apparatus for this purpose, and when additional processing is performed, a task of rearranging the wafer is necessary. However, according to the present invention, such work is not required, and the efficiency of the processing process is improved.
As described above, according to one embodiment of the present invention, a wafer processing method is provided that can effectively determine whether or not all of a plurality of electrode columns are exposed on the back surface of a thinned wafer. Further, a wafer processing method is provided, which can reliably detect the presence of an unexposed electrode column and perform additional processing so that all the electrode columns are exposed on the back surface.
Drawings
Fig. 1 (a) is a schematic cross-sectional view showing a wafer in which a plurality of electrode columns are embedded, and fig. 1 (B) is a schematic cross-sectional view showing a case where a support wafer is disposed on the front surface of the wafer.
Fig. 2 is a perspective view schematically showing an example of the processing apparatus.
Fig. 3 (a) is a side view illustrating the holding step, and fig. 3 (B) is a side view illustrating an example of the thinning step.
Fig. 4 is a sectional view illustrating another example of the thinning step.
Fig. 5 (a) is a side view for explaining the determination step, fig. 5 (B) is a schematic diagram showing an example of a captured image, and fig. 5 (C) is a schematic diagram showing another example of a captured image.
Description of the reference symbols
1: a wafer; 1a: a front side; 1b: a back side; 3: an electrode column; 5: supporting the wafer; 7. 9: shooting an image; 2: a processing device; 4: a stage; 6: a column; 8,10: a track; 12: a rough grinding unit; 14: a rough grinding unit feed mechanism; 16: a finish grinding unit; 18: a finish grinding unit feed mechanism; 20: a unit housing; 22: a main shaft; 24: a wheel mount; 26: grinding the grinding wheel; 28: a grinding wheel base station; 30: grinding the grinding tool; 32: an electric motor; 34: rotating the workbench; 36: an arrow; 38: a holding table; 38a: a porous member; 38b: an aspiration path; 40. 40a: a grinding unit; 42: a main shaft; 44: a wheel mount; 46: grinding the grinding wheel; 48: a base station; 50: a polishing pad; 52: a polishing liquid supply path; 54: a shooting unit; 56: a controller (control unit); 58: a determination unit; 60: a standard image storage unit; 62. 64: a cartridge; 66: a wafer transfer robot; 68: temporarily placing a workbench; 70: a rotary cleaning unit; 72: a conveying unit.
Detailed Description
Embodiments of the present invention will be explained. First, a wafer as a workpiece in the wafer processing method according to the present embodiment will be described. Fig. 1 (a) is a schematic cross-sectional view showing a wafer 1 as a workpiece. The front surface 1a of the wafer 1 is divided into a plurality of regions by planned dividing lines (not shown) arranged in a lattice shape, and devices (not shown) such as ICs and LSIs are formed in each of the divided regions. The wafer 1 is finally divided along the lines to be divided to form a plurality of chips.
The wafer 1 is made of, for example, silicon, sapphire, glass, quartz, or the like, and is, for example, a substrate having a substantially circular plate shape. In the case of using a wafer composed of a semiconductor material, for example, a part of the wafer 1 is used to form a device. When the wafer 1 is not made of a semiconductor material, for example, a semiconductor layer is provided on the front surface 1a of the wafer 1, and the semiconductor layer is processed to form a device.
The wafer 1 is provided with a plurality of holes having a predetermined depth and opening on the front surface 1a side, and a conductive material is introduced into each of the holes to form a plurality of electrode posts 3 extending in the thickness direction of the wafer 1. The conductive material is introduced into the hole by plating, CVD, vapor deposition, or the like. Or a paste containing the conductive material may be introduced and cured. After the conductive material is introduced into the hole by these methods, the front surface 1a side of the wafer 1 is planarized by a CMP method or the like in order to remove an excess conductive material which is not received in the hole due to the excess supply.
For example, gold, silver, copper, aluminum, or the like is used as the conductive material. Since the electrode posts 3 are used for electrically connecting the stacked chips, a material having a low resistance can be used as the conductive material.
When the wafer 1 is processed from the rear surface 1b side and thinned to a predetermined thickness, the bottom of the hole into which the conductive material is introduced is removed to expose the electrode column 3 on the rear surface 1b side, and therefore the hole is formed deeper than the finished thickness of the wafer 1 after thinning.
In the processing method of the present embodiment, before the back surface 1B of the wafer 1 is processed, as shown in fig. 1 (B), a support wafer 5 for protecting the devices on the front surface 1a is bonded to the front surface 1 a. As the support wafer 5, for example, a silicon wafer is used. Instead of supporting the wafer 5, a protective tape may be pasted on the front surface 1a of the wafer 1.
Next, a processing apparatus suitable for carrying out the wafer processing method according to the present embodiment will be described. Fig. 2 is a perspective view showing an example of the machining device. The processing apparatus 2 is an apparatus capable of performing processing such as grinding processing and polishing processing on a wafer.
The processing apparatus 2 has a table 4 having a substantially rectangular parallelepiped shape. A substantially rectangular parallelepiped pillar 6 is provided upright near an end portion of the upper surface of the table 4. Two pairs of rails 8 and 10 extending in the up-down direction are provided on the front surface of the column 6 of the processing apparatus 2.
A rough grinding unit 12 is mounted on one pair of rails 8 so as to be movable in the vertical direction (Z-axis direction) by a rough grinding unit feed mechanism 14, and a finish grinding unit 16 is mounted on the other pair of rails 10 so as to be movable in the vertical direction by a finish grinding unit feed mechanism 18.
A detailed configuration of the rough grinding unit 12 will be described with reference to fig. 2 and 3 (B). The rough grinding unit 12 includes: a cylindrical unit case 20; and a motor 32 that rotationally drives the spindle 22, the spindle 22 being housed in the unit case 20 so as to be rotatable. The front end of the spindle 22 is exposed to the outside from the lower surface of the unit case 20.
The rough grinding unit 12 further includes: a disc-shaped wheel mounting seat 24 fixed to the front end of the main shaft 22; and a grinding wheel 26 detachably attached to the front end of the wheel mounting base 24. The grinding wheel 26 is composed of a disk-shaped grinding wheel base 28 and a plurality of grinding stones 30, the diameter of the grinding wheel base 28 is substantially equal to that of the wheel mounting seat 24, and the plurality of grinding stones 30 are annularly fixed to the outer periphery of the lower end surface of the grinding wheel base 28.
The finish grinding unit 16 is configured similarly to the rough grinding unit 12. However, in the grinding wheel provided in the finish grinding unit 16, a grinding wheel suitable for smoothly grinding the wafer compared to the grinding wheel provided in the rough grinding unit 12 is used.
As shown in fig. 2, the machining device 2 includes a rotary table 34 substantially parallel to the upper surface of the table 4 on the front side of the column 6. The rotary table 34 is rotated in a direction indicated by an arrow 36 by a not-shown rotation drive mechanism. On the rotating table 34, 4 holding tables 38 are arranged so as to be rotatable in a horizontal plane, the holding tables being separated from each other by 90 degrees in the circumferential direction.
A porous member 38a is disposed above the holding table 38, and the upper surface of the porous member 38a serves as a holding surface (see fig. 4). The holding table 38 has a suction path 38b therein, one end of which is connected to a suction source (not shown). The other end of the suction path 38b is connected to the porous member 38a (see fig. 4). The holding table 38 applies the negative pressure generated by the suction source to the wafer 1 placed on the holding surface through the porous member 38a, thereby sucking and holding the wafer 1.
The 4 holding tables 38 disposed on the turn table 34 are sequentially moved to the wafer carrying-in/out area a, the rough grinding processing area B, the finish grinding processing area C, and the polishing processing area D by appropriate rotation of the turn table 34. Each holding table 38 is rotatable about an axis perpendicular to the holding surface, and rotates to rotate the wafer 1 when the wafer 1 is ground or the like.
The polishing processing region D is provided with the 1 st polishing unit 40. The 1 st polishing unit 40 includes: a stationary block (not shown) fixed to the table 4; an X-axis moving block (not shown) attached to the stationary block and movable in the X-axis direction by an X-axis moving mechanism (not shown); and a Z-axis moving block (not shown) attached to the X-axis moving block and movable in the Z-axis direction by a Z-axis moving mechanism (not shown).
A cylindrical unit case (not shown) is disposed on the Z-axis moving block, and as shown in fig. 4, the main shaft 42 is rotatably housed in the unit case. The front end of the spindle 42 is exposed to the outside from the lower surface of the unit case. A disc-shaped wheel mounting base 44 is fixed to a tip end of the spindle 42, and a grinding wheel 46 is detachably mounted on the wheel mounting base 44 with respect to the wheel mounting base 44.
The grinding wheel 46 includes a disk-shaped base 48 having a diameter substantially equal to that of the wheel mounting base 44, and a grinding pad 50 attached to the base 48. The grinding wheel 46 is attached to the wheel mounting base 44 on the base 48 side. The polishing pad 50 is formed of a felt material in which abrasive grains are dispersed in polyurethane or felt and fixed with a binder, for example. A polishing liquid supply path 52 is formed in the center of the base 48 and the polishing pad 50. A plurality of grooves (not shown) for holding the polishing liquid are formed on the polishing surface (lower surface) of the polishing pad 50.
A2 nd polishing unit 40a is disposed between the wafer carrying-in/out area A and the polishing area D. The 2 nd polishing unit 40a is configured in the same manner as the 1 st polishing unit 40.
A 1 st cassette 62 for storing, for example, wafers before processing and a 2 nd cassette 64 for storing, for example, wafers after processing are detachably attached to the side of the table 4 of the processing apparatus 2 opposite to the column 6.
The wafer transfer robot 66 carries out the wafer stored in the 1 st cassette 62 onto the temporary stage 68. The processed wafers cleaned by the spin cleaning unit 70 are then transferred to the 2 nd cassette 64.
The transfer unit 72 transfers the wafer from the temporary placement table 68 onto the holding table 38 located in the wafer transfer-in/out area a. The processed wafer is sucked and transferred from the holding table 38 to the spin cleaning unit 70. The transfer unit 70 can move the wafer in the X-axis direction, the Y-axis direction, and the Z-axis direction.
At least one of the rough grinding unit 12, the finish grinding unit 16, the 1 st grinding unit 40, and the 2 nd grinding unit 40a of the processing device 2 further includes an imaging unit, and the imaging unit is used when confirming the state or the processing position of the object to be processed. The imaging means is also used in the determination step of the machining method according to the present embodiment. The imaging unit is formed of, for example, a line sensor having a plurality of imaging elements arranged linearly in a strip-shaped housing.
As shown in fig. 5 (a), the imaging unit 54 is located above the end of the wafer 1 so that the long axis of the strip-shaped case is parallel to the wafer 1. The imaging unit 54 images the processed wafer 1 while moving in a horizontal plane in a direction perpendicular to the long axis of the housing (the direction of the arrow in fig. 5 a) to generate an imaged image, and transmits the imaged image to the controller (control unit) 56 of the processing apparatus 2.
As shown in fig. 2, the processing apparatus 2 includes a controller (control unit) 56 connected to the table 4. The controller (control unit) 56 has a function of controlling each component of the machining apparatus 2. In a determination step described later, the controller (control unit) 56 receives the captured image from the imaging unit 54, and determines whether or not all of the electrode posts 3 are exposed on the back surface 1b side of the wafer 1 based on the captured image. The configuration and function of the controller (control unit) 56 may be implemented as software on a PC.
The controller (control unit) 56 includes a determination unit 58 and a standard image storage unit 60. The standard image storage unit 60 stores the correctly processed image of the back surface 1b of the wafer 1 as a standard image. In a determination step described later, the determination unit 58 compares the standard image read from the standard image storage unit 60 with the captured image transmitted from the imaging unit 54, and determines whether or not the electrode column 3 not exposed on the back surface is present.
When the determination unit 58 determines that there is no unexposed electrode column 3, the controller (control unit) 56 sends the wafer 1 to the next step. When the determination unit 58 determines that there is an unexposed electrode column 3, the wafer is processed again by the processing unit (grinding unit or polishing unit) to which the imaging unit 54 is attached. After the wafer is processed again, the imaging unit 54 may generate an imaging image again and perform determination.
Next, a method of processing a wafer according to the present embodiment will be described. First, as shown in fig. 3 (a), a holding step is performed to hold the wafer 1 having a plurality of devices formed on the front surface 1a by the holding table 38 located in the wafer carrying-in/out area a of the processing apparatus 2. A front surface protection member such as the support wafer 5 is bonded to the front surface 1a of the wafer 1 in advance, and the wafer 1 is placed on the holding table 38 with the front surface 1a side facing the holding surface of the holding table 38 and is sucked and held.
Next, a thinning step is performed to thin the wafer 1 by processing the back surface 1b side of the wafer 1 held by the holding table 38. In the thinning step, the wafer 1 is thinned, and the bottom of the hole in the wafer 1, in which the electrode column 3 is embedded, is removed to expose the electrode column 3 on the back surface 1b side of the wafer 1.
For example, the thinning step of exposing the electrode posts 3 is performed using the rough grinding unit 12, the finish grinding unit 16, the 1 st grinding unit 40, the 2 nd grinding unit 40a, and the like of the processing apparatus 2. The processing of the wafer 1 in each unit will be described below.
First, the holding table 38 is transferred to the rough grinding process area B by rotating the rotating table 34, and the wafer 1 is moved. Then, the back surface 1b of the wafer 1 is roughly ground by the rough grinding unit 12. Fig. 3 (B) is a side view illustrating rough grinding.
In the rough grinding, first, the holding table 38 and the grinding wheel 26 are rotated in the directions of the arrows shown in fig. 3 (B), respectively. Then, the rough grinding unit feed mechanism is operated with both rotated, and the grinding wheel 26 is fed in the downward direction. When the grinding wheel 30 held by the grinding wheel 26 is brought into contact with the wafer 1, the back surface 1b side of the wafer 1 is roughly ground. If the wafer 1 is roughly ground to a prescribed thickness, the rough grinding is finished.
Next, the turning table 34 of the processing apparatus 2 is rotated to feed the holding table 38 to the finish grinding processing region C. Then, the wafer 1 is finish-ground by the finish-grinding unit 16. Further, the finish grinding by the finish grinding unit 16 is performed in the same manner as the rough grinding by the rough grinding unit 12.
Finish grinding is performed at a machining feed speed slower than that of rough grinding, and finish grinding is performed on the ground surface so as to smooth the ground surface. The back surface 1b of the wafer 1 is thinned to a thickness around the finished thickness of the chip by rough grinding and finish grinding.
After the finish grinding, the rotating table 34 is rotated to send the holding table 38 to the grinding area D. Then, the back surface 1b side of the wafer 1 is polished by the first polishing unit 1 40. Fig. 4 is a cross-sectional view schematically showing polishing of the back surface 1b side of the wafer 1 by the 1 st polishing unit 40.
While supplying the polishing liquid to the wafer 1 held on the holding table 38 through the polishing liquid supply path 52, the holding table 38 and the polishing pad 50 are rotated in the directions of the arrows shown in fig. 4. Then, the Z-axis movement mechanism is operated to bring the polishing pad 50 into contact with the back surface 1b of the wafer 1, and in this state, the polishing pad 50 is pressed against the back surface 1b of the wafer 1 to perform polishing.
Subsequently, the holding table 38 is transported to the wafer loading/unloading area a by rotating the rotary table 34. Then, the wafer 1 is further ground by the 2 nd grinding unit 40a. The polishing by the 2 nd polishing unit 40a is performed in the same manner as the polishing by the 1 st polishing unit 40. When the back surface 1b of the wafer 1 is further thinned by polishing performed by the 1 st polishing unit 40 and the 2 nd polishing unit 40a, the grinding strain of the back surface 1b of the wafer 1 is removed.
Here, the bottom of the hole in which the electrode column 3 is embedded is removed in any of grinding by the rough grinding unit 12, grinding by the finish grinding unit 16, grinding by the 1 st grinding unit 40, and grinding by the 2 nd grinding unit 40a. Then, the electrode posts 3 are exposed on the back surface 1b side of the wafer 1. However, the depth of the hole formed in the wafer 1 varies, and even if the processing is performed under predetermined conditions, the plurality of electrode posts 3 may not be entirely exposed on the back surface 1b side of the wafer 1.
If the electrode posts 3 are not exposed on the back surface 1b side of the wafer 1, when a plurality of chips divided from the wafer 1 are stacked to produce a laminate, the chips cannot be appropriately connected by the electrode posts 3, and therefore the laminate cannot function properly. Therefore, it is necessary to expose all of the electrode posts 3 formed on the wafer 1 on the back surface 1b of the wafer 1.
Therefore, in the wafer processing method of the present embodiment, the determination step is performed after the thinning step of exposing the electrode posts 3 on the rear surface 1b side is performed. In the determination step, the rear surface 1b of the wafer 1 is photographed to generate a photographed image, and the presence or absence of the electrode column 3 not exposed on the rear surface 1b is determined based on the photographed image.
As described above, the photographing unit 54 is mounted in the rough grinding unit 12, the finish grinding unit 16, the 1 st grinding unit 40, or the 2 nd grinding unit 40a. The imaging unit 54 images the back surface 1b side of the processed wafer 1 to generate an imaging image. Fig. 5 (a) is a side view showing that the imaging unit 54 is used to take an image of the back surface 1b side of the wafer 1. After the thinning step, the photographing step is performed while maintaining the state in which the wafer 1 is held on the holding table 38.
In the determination step, first, the strip-shaped housing of the imaging unit 54 is turned so that the long axis thereof is parallel to the wafer 1 and positioned above the end of the wafer 1. Then, the imaging unit 54 images the processed wafer 1 while moving in a direction perpendicular to the long axis of the housing in a horizontal plane (the direction of an arrow shown in fig. 5 a) to generate an imaged image, and transmits the imaged image to a controller (control unit) of the processing apparatus 2.
Fig. 5 (B) and 5 (C) show examples of the captured images captured by the imaging unit 54. Fig. 5 (B) is a photographed image 7 showing a case where a part of the plurality of electrode columns 3 formed on the wafer 1 is not exposed on the back surface 1B side of the wafer 1, and fig. 5 (C) is a photographed image 9 showing a case where all the electrode columns 3 are exposed on the back surface 1B side of the wafer 1.
The captured image 9 shown in fig. 5 (C) is stored in advance in the standard image storage unit 60 of the controller (control unit) 56 of the processing apparatus 2 as a standard image showing a state in which the thinning step is normally performed.
The determination unit 58 of the controller (control unit) 56 that receives the captured image from the imaging unit 54 is connected to the standard image storage unit 60, and when the captured image is received from the imaging unit 54, the standard image shown in fig. 5 (C) is read from the standard image storage unit 60. Then, the photographed image and the standard image are compared to determine whether all the electrode posts 3 are exposed on the back surface of the wafer 1.
This determination is performed, for example, by matching two images. When the two images are judged to match by the comparison, the judgment section judges that the electrode column 3 not exposed on the back surface 1b side of the wafer 1 is not present. On the other hand, when the two images are determined not to coincide with each other, the determination unit determines that the electrode posts 3 not exposed on the back surface 1b side of the wafer 1 are present. In contrast between the two images, the two images may not completely coincide with each other, and for example, a positional shift may be allowed within a range of an error in the formation position of each electrode column 3.
When the determination unit 58 determines that there is no electrode column 3 not exposed on the back surface 1b side of the wafer 1, the processing apparatus 2 performs the subsequent step of the thinning step on the wafer 1. In this way, even when the thinning step is normally performed without requiring additional processing, since the wafer processing method of the present embodiment can quickly determine that additional processing is not required, the processing method of the present embodiment can speed up the process.
When the determination unit 58 determines that there is an electrode post 3 not exposed on the back surface 1b side of the wafer 1, additional processing is performed on the wafer 1 held on the holding table 38. The additional processing is performed to expose all the electrode posts 3 on the back surface 1b side of the wafer 1. In this state, additional processing is performed using the processing unit used in the thinning step.
In the wafer processing method of the present embodiment, the additional processing can be quickly performed on the wafer 1 without moving the holding table 38, the wafer 1, or the like when the determination or the additional processing is performed. As for the additional processing, for example, the same processing as that performed in the thinning step is performed by shortening the processing time or the like. After the additional machining is performed, the above-described determination step is performed again, and after the determination that all the electrode columns 3 are exposed is obtained, the next step is performed.
In the wafer processing method according to the present embodiment, the imaging unit 54 images the back surface 1b of the wafer 1 to generate an image, and the presence or absence of the electrode column 3 not exposed on the back surface 1b is determined based on the image. Therefore, the determination can be performed quickly and reliably as compared with a case where the wafer 1 is peeled off from the holding table 38 and the operator visually determines the wafer 1. Further, since the determination can be made without moving the holding table 38, the additional processing can be performed on the wafer 1 at the original position even when the additional processing is necessary.
The present invention is not limited to the above embodiments, and various modifications can be made. For example, when the additional processing is performed in response to the determination by the determination unit 58, the ratio of the electrode posts 3 exposed to the rear surface 1b side among the plurality of electrode posts 3 may be derived in order to determine the degree of the additional processing performed. When considering the general distribution of the depths of the holes in which the electrode columns 3 are buried, the lower the ratio, the greater the distance from the bottom of the shallowest hole to the back surface 1 b. Therefore, the content of the additional processing can be determined in consideration of the correlation between the ratio and the required strength of the additional processing.
For example, the number of electrode posts 3 appearing in the standard image and the number of electrode posts 3 appearing in the captured image generated by the capturing unit are detected. Then, the ratio of the exposed electrode column 3 in the whole is derived. If the ratio of the exposed electrode posts 3 is relatively low, additional processing with high strength may be performed to expose all the electrode posts 3. On the other hand, when the ratio of the exposed electrode columns 3 is relatively high, additional processing with low strength may be performed.
When the content of the additional processing can be specified using the captured image in this manner, the minimum additional processing required to expose the unexposed electrode posts 3 can be performed, and therefore, the additional processing time and the cost in terms of money can be reduced.
In one embodiment of the present invention, the determination step and the rework may be performed at a different place from the thinning step. For example, when finish grinding is performed as the thinning step, the determination step may be performed after grinding, and further, rework may be performed from the rough grinding.
The structure, method, and the like of the above embodiments can be modified as appropriate without departing from the object of the present invention.

Claims (2)

1. A method of processing a wafer having a device formed on a front surface thereof and a plurality of electrode posts embedded in the wafer, the electrode posts extending in a thickness direction of the wafer and reaching a predetermined depth from the front surface of the wafer,
the processing method of the wafer comprises the following steps:
a holding step of holding the front surface side of the wafer by a holding table;
a thinning step of thinning the wafer held by the holding table to a predetermined thickness by processing the back side of the wafer by a grinding unit or a polishing unit; and
a determination step of taking an image of the back surface of the wafer after the thinning step, generating a taken image, determining whether or not there is an electrode column not exposed on the back surface based on the taken image,
if it is determined by this determination step that there is an electrode column that is not exposed on the back surface of the wafer, an additional processing step is performed in which the wafer is further thinned by a grinding unit or a polishing unit.
2. The method of processing a wafer according to claim 1,
the determination step is performed in a state where the wafer is held on the holding table,
the additional processing step is performed in a state where the wafer is held on the holding table.
CN201710951990.0A 2016-10-14 2017-10-13 Method for processing wafer Active CN107958841B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2016-203068 2016-10-14
JP2016203068A JP6707291B2 (en) 2016-10-14 2016-10-14 Wafer processing method

Publications (2)

Publication Number Publication Date
CN107958841A CN107958841A (en) 2018-04-24
CN107958841B true CN107958841B (en) 2023-04-18

Family

ID=61954624

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201710951990.0A Active CN107958841B (en) 2016-10-14 2017-10-13 Method for processing wafer

Country Status (4)

Country Link
JP (1) JP6707291B2 (en)
KR (1) KR102325715B1 (en)
CN (1) CN107958841B (en)
TW (1) TWI737810B (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI805823B (en) * 2018-10-31 2023-06-21 日商三星鑽石工業股份有限公司 Substrate supply system and substrate processing device
JP7325913B2 (en) * 2019-11-22 2023-08-15 株式会社ディスコ Wafer processing equipment

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002273653A (en) * 2001-03-16 2002-09-25 Dainippon Screen Mfg Co Ltd Polishing end point detection for substrate
JP2003197855A (en) * 2001-12-27 2003-07-11 Toshiba Corp Semiconductor device and method of manufacturing the same
JP2011125987A (en) * 2009-12-21 2011-06-30 Disco Abrasive Syst Ltd Grinding device
EP2469586A1 (en) * 2010-12-24 2012-06-27 Mitsuboshi Diamond Industrial Co., Ltd. Patterning device
JP2014053354A (en) * 2012-09-05 2014-03-20 Disco Abrasive Syst Ltd Wafer processing method
TW201606896A (en) * 2014-04-29 2016-02-16 蘭姆研究公司 Systems and methods for detecting endpoint for through silicon-via reveal applications
KR20160026691A (en) * 2014-08-29 2016-03-09 가부시기가이샤 디스코 Wafer inspection method and grinding and polishing equipment
JP2016064459A (en) * 2014-09-24 2016-04-28 株式会社ディスコ Method of grinding workpiece

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3792954B2 (en) 1999-08-10 2006-07-05 株式会社東芝 Manufacturing method of semiconductor device
JP4340517B2 (en) 2003-10-30 2009-10-07 Ｏｋｉセミコンダクタ株式会社 Semiconductor device and manufacturing method thereof
JP2008071839A (en) * 2006-09-12 2008-03-27 Canon Inc Method for detecting place of surface, exposure apparatus and device manufacturing method
JP2012164801A (en) * 2011-02-07 2012-08-30 Lasertec Corp Inspection apparatus and inspection method
US9960088B2 (en) * 2011-11-07 2018-05-01 Taiwan Semiconductor Manufacturing Company, Ltd. End point detection in grinding
JP5770677B2 (en) * 2012-05-08 2015-08-26 株式会社ディスコ Wafer processing method
JP2014053353A (en) * 2012-09-05 2014-03-20 Disco Abrasive Syst Ltd Wafer processing method
JP6385131B2 (en) * 2014-05-13 2018-09-05 株式会社ディスコ Wafer processing method
JP6366383B2 (en) * 2014-06-27 2018-08-01 株式会社ディスコ Processing equipment

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002273653A (en) * 2001-03-16 2002-09-25 Dainippon Screen Mfg Co Ltd Polishing end point detection for substrate
JP2003197855A (en) * 2001-12-27 2003-07-11 Toshiba Corp Semiconductor device and method of manufacturing the same
JP2011125987A (en) * 2009-12-21 2011-06-30 Disco Abrasive Syst Ltd Grinding device
EP2469586A1 (en) * 2010-12-24 2012-06-27 Mitsuboshi Diamond Industrial Co., Ltd. Patterning device
JP2014053354A (en) * 2012-09-05 2014-03-20 Disco Abrasive Syst Ltd Wafer processing method
TW201606896A (en) * 2014-04-29 2016-02-16 蘭姆研究公司 Systems and methods for detecting endpoint for through silicon-via reveal applications
KR20160026691A (en) * 2014-08-29 2016-03-09 가부시기가이샤 디스코 Wafer inspection method and grinding and polishing equipment
JP2016064459A (en) * 2014-09-24 2016-04-28 株式会社ディスコ Method of grinding workpiece

Also Published As

Publication number Publication date
JP6707291B2 (en) 2020-06-10
CN107958841A (en) 2018-04-24
KR102325715B1 (en) 2021-11-11
TWI737810B (en) 2021-09-01
KR20180041585A (en) 2018-04-24
JP2018064076A (en) 2018-04-19
TW201816872A (en) 2018-05-01

Similar Documents

Publication Publication Date Title
JP6906859B2 (en) Processing equipment
JP2009004406A (en) Working method for substrate
JP2007305835A (en) Treatment method of wafer
JP2004207606A (en) Wafer support plate
JP2010199227A (en) Grinding device
KR20170030035A (en) Wafer machining method
CN110571147B (en) Wafer processing method and grinding device
KR101840478B1 (en) Method for machining wafer
JP2019220632A (en) Processing method for work piece
JP5117686B2 (en) Grinding equipment
CN107958841B (en) Method for processing wafer
JP7430108B2 (en) Processing method and holding table
JP2011040511A (en) Method of grinding wafer
JP4861061B2 (en) Method and apparatus for confirming annular reinforcing portion formed on outer periphery of wafer
JP5554601B2 (en) Grinding equipment
JP2014038929A (en) Inline system
JP2010147134A (en) Alignment mechanism, grinder, aligning method, and grinding method
JP2007165802A (en) Grinding machine and method for substrate
JP2009302369A (en) Method and apparatus for processing plate-like object
JP7025249B2 (en) Grinding method for workpieces.
JP2014053357A (en) Wafer processing method
JP2019111634A (en) Method for grinding work-piece
JP5975839B2 (en) Grinding equipment
CN115621198A (en) Method for processing wafer
JP2022083700A (en) Wafer processing method

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant