CN107958681A

CN107958681A - A kind of MRAM chip

Info

Publication number: CN107958681A
Application number: CN201610905519.3A
Authority: CN
Inventors: 戴瑾; 俞华樑; 叶力; 郭民; 郭一民; 陈峻
Original assignee: Shanghai Ciyu Information Technologies Co Ltd
Current assignee: Shanghai Ciyu Information Technologies Co Ltd
Priority date: 2016-10-17
Filing date: 2016-10-17
Publication date: 2018-04-24

Abstract

The present invention provides a kind of MRAM chip, including multiple arrays being made of mram memory cell, and each array is using the vertical layout of bit line and source electrode line, and the bit in each word is respectively stored in different arrays, each array stores a bit.Bit line is vertical with source electrode line, each bit in each word is respectively stored in multiple arrays, since an array only writes a bit every time, it is no longer necessary to high voltage or negative voltage, so that Array Design is simple and energy consumption reduces, solves the problems, such as source electrode line electricity shortage；All bit lines in array with a line share sense amplifier, and an array only needs a sense amplifier, reduces the cost of MRAM chip；When using ECC error correction, since adjacent position is not present in the different bits of same word, the probability continuously to malfunction is reduced, ensure that ECC can correctly correct mistake, improve the reliability of MRAM chip.

Description

A kind of MRAM chip

Technical field

The invention belongs to semiconductor chip field, and in particular to a kind of MRAM chip.

Background technology

On MRAM：

The background of the present invention is the maturation of MRAM technology.MRAM is a kind of new memory and memory technology, can be as SRAM/ The equally quick random read-writes of DRAM, can also as Flash flash memories permanent retention data after a loss of power.

It is local good that its economy is thought, the silicon area that unit capacity takes has very big advantage than SRAM, than such The NOR Flash being commonly used in chip are also advantageous, the advantage bigger than embedded NOR Flash.Its performance is also suitable Good, read-write time delay is then best in various memories and memory technology close to best SRAM, power consumption.And MRAM unlike DRAM and Flash is incompatible with standard CMOS semiconductor technique like that.MRAM can be integrated into logic circuit in a chip.

The principle of MRAM：

The principle of MRAM, is to be based on a knot for being called magnetic tunnel junction (Magnetic Tunnel Junction, MTJ) Structure.It clips what one layer very thin of non-ferric magnetic dielectric formed by two layers of ferrimagnet.Such as figure：

One layer of following ferromagnetic material is the reference layer for having fixed magnetisation direction, and ferromagnetic material above is variable magnetization The memory layer in direction, its direction of magnetization can be in the same direction or reverse with fixed magnetization layer.Due to the effect of quantum physics, electric current can To pass through middle tunnel barrier layer, but the resistance of MTJ is related with the direction of magnetization of variable magnetization layer.The direction of magnetization can be with Fixed magnetization layer is low resistance state in the same direction, as shown in Figure 1；The direction of magnetization can be reversed high-resistance state with fixed magnetization layer, such as Shown in Fig. 2.

The process for reading MRAM is exactly that the resistance of MTJ is measured.Using newer STT-MRAM technologies, MRAM is write Also it is fairly simple：Using than reading stronger electric current write operation is carried out through MTJ.One electric current from bottom to top is variable magnetization layer It is set in the same direction with fixed bed, top-down circuit is set to it reversely.

The framework of MRAM

The mnemon of each MRAM is made of MTJ and metal-oxide-semiconductor, and the grid (gate) of metal-oxide-semiconductor is connected to core The wordline (Word Line, WL) of piece is responsible for switching on or off this unit, and MTJ and metal-oxide-semiconductor are serially connected in the bit line (Bit of chip Line, BL) on, read-write operation carries out on bit line, as shown in Figure 3.

One MRAM chip is made of the array of one or more mram memory cells, and each array has some external electricals Road, such as：

● row-address decoder：Received address is become the selection of wordline

● column address decoder：Received address is become the selection of bit line

● read-write controller：Operation is write and (adds electric current) in reading (measurement) in control bit line

● input and output control：Data are exchanged with outside

MRAM array is laid out

The core of MRAM chip is memory cell array, and array has different layout methods：

(1) bit line and source electrode line (Source Line, SL) parallel arrangement

Wordline and bit line in one array must be vertical, as shown in figure 5, wherein WL is wordline, SL is source electrode line, BL is bit line.Bit line is parallel with source electrode line, and write operation is easier, and wordline, which is drawn high, opens a line storage unit, then according to every One unit writes 0 or 1 demand, increases current potential on bit line or source electrode line respectively.

Although this method is simple, fabric swatch generally takes up bigger area, and chip cost is high.

(2) bit line and source electrode line vertical arrangement

As shown in fig. 6, bit line and the vertical layout of source electrode line, are conducive to reduce the chip face shared by each storage unit Product, reduces cost.Operation is slightly complicated during write-in：The current potential of one wordline is drawn high and opens this line, and the source electrode of this line Line is placed in an intermediate potential.Then 0 or 1 demand is write according to each unit, adds high or low electricity on bit line respectively Position.Low potential is likely to be negative voltage.

Although bit line can reduce cost with source electrode line vertical arrangement scheme, there are following two problems：

Because require have a fixed voltage drop, this required high potential of method in storage unit during write-in It is with the voltage difference of low potential, chip requirement cannot be provided using outside bit line and source electrode line parallel arrangement scheme twice High voltage or negative voltage, portion's design circuit produces different voltage including both of these case is required for, and voltage conversion can be brought The reduction of power consumption efficiency and extra cost；

The whole required electric current of a line, all flows into from same root bit line, in the design usually due to source during write-in Line widths not enough bring difficulty.

The content of the invention

In view of problems of the prior art, the object of the present invention is to provide a kind of MRAM chip, bit line and source electrode line Vertically, each bit in each word is respectively stored in multiple arrays, since an array only writes a bit every time, no longer Need high voltage or negative voltage so that Array Design is simple and energy consumption reduces, and solves the problems, such as source electrode line electricity shortage.

The present invention provides a kind of MRAM chip, including multiple arrays being made of mram memory cell, and each array uses Bit line and the vertical layout of source electrode line, the bit in each word are respectively stored in different arrays, each array storage one A bit.

Further, each array includes a sense amplifier, and all bit lines in array with a line are shared reading and put Big device.

Further, two rows adjacent in array share a root polar curve.

Further, each word includes ECC error correction bit, and each ECC error correction bit is respectively stored in different arrays.

Further, during write storage unit, corresponding wordline is put into high potential and opens corresponding row in array, by correspondence Source electrode line set low, the bit line of storage unit is put into height, remaining bit line is set low.

Further, during write storage unit, corresponding wordline is put into high potential and opens corresponding row in array, by correspondence Source electrode line put height, the bit line of storage unit is set low, remaining bit line is put into height.

Compared with prior art, MRAM chip provided by the invention, has the advantages that：

(1) since an array only writes a bit every time, it is no longer necessary to high voltage or negative voltage so that Array Design letter List and energy consumption reduction, solve the problems, such as source electrode line electricity shortage；

(2) all bit lines in array with a line share sense amplifier, and an array only needs a sense amplifier, drop The low cost of MRAM chip；

(3) when using ECC error correction, since adjacent position is not present in the different bits of same word, reduce continuous The probability of error, ensure that ECC can correctly correct mistake, improves the reliability of MRAM chip.

Brief description of the drawings

Fig. 1 is the low resistance state schematic diagram of magnetic tunnel junction；

Fig. 2 is the high-resistance state schematic diagram of magnetic tunnel junction；

Fig. 3 is mram memory cell；

Fig. 4 is the structure diagram of MRAM chip in the prior art；

Fig. 5 is a kind of array layout schematic diagram of MRAM chip in the prior art；

Fig. 6 is another array layout schematic diagram of MRAM chip in the prior art；

Fig. 7 is the array layout schematic diagram of the MRAM chip of one embodiment of the present of invention；

A kind of view when Fig. 8 is array one bit of write-in of the MRAM chip shown in Fig. 7；

Another view when Fig. 9 is array one bit of write-in of the MRAM chip shown in Fig. 7.

Embodiment

The MRAM chip of one embodiment of the present of invention, including multiple arrays being made of mram memory cell, Mei Gezhen Using bit line and the vertical layout of source electrode line, each bit in each word is respectively stored in different arrays row, each Array stores a bit.

Since an array only writes a bit every time, it is no longer necessary to high voltage or negative voltage so that Array Design is simple And energy consumption reduces, and solves the problems, such as source electrode line electricity shortage.

Each array includes a sense amplifier, since an array only writes a bit every time, same a line in array All bit lines share sense amplifier, reduce further the cost of MRAM chip.

Two adjacent rows share a root polar curve in array, as shown in fig. 7, further reduce the area that fabric swatch takes, drop The low cost of MRAM chip.

Each word can also include ECC error correction bit, improve the reliability of MRAM chip.

A kind of state when the array of MRAM chip in the present embodiment writes a bit is as shown in figure 8, write storage During unit, corresponding wordline is put into high potential and opens corresponding row in array, corresponding source electrode line is put into height, by storage unit Bit line is set low, remaining bit line is put height.

Other storage units so with a line do not have electric current, so as to ensure that an array only writes a ratio every time It is special, it is no longer necessary to high voltage or negative voltage so that Array Design is simple and energy consumption reduces, and solves asking for source electrode line electricity shortage Topic.

Another state when the array of MRAM chip in the present embodiment writes a bit is as shown in figure 9, write-in is deposited During storage unit, corresponding wordline is put into high potential and opens corresponding row in array, corresponding source electrode line is set low, by storage unit Bit line put height, remaining bit line is set low, so other storage units with a line do not have electric current.

Preferred embodiment of the invention described in detail above.It should be appreciated that those of ordinary skill in the art without Need creative work to conceive according to the present invention and make many modifications and variations.Therefore, all technologies in the art Personnel are available by logical analysis, reasoning, or a limited experiment on the basis of existing technology under this invention's idea Technical solution, all should be in the protection domain being defined in the patent claims.

Claims

1. a kind of MRAM chip, including multiple arrays being made of mram memory cell, it is characterised in that each array uses position Line and the vertical layout of source electrode line, the bit in each word are respectively stored in different arrays, each array stores one Bit.

2. MRAM chip as claimed in claim 1, it is characterised in that each array includes a sense amplifier, in array All bit lines with a line share the sense amplifier.

3. MRAM chip as claimed in claim 1, it is characterised in that two adjacent rows share a root polar curve in array.

4. MRAM chip as claimed in claim 1, it is characterised in that each word includes ECC error correction bit.

5. MRAM chip as claimed in claim 1, it is characterised in that each ECC error correction bit is respectively stored in different battle arrays In row.

6. MRAM chip as claimed in claim 1, it is characterised in that during write storage unit, corresponding wordline is put into high electricity Corresponding row in array is opened in position, and corresponding source electrode line is set low, the bit line of the storage unit is put height, remaining bit line is put It is low.

7. MRAM chip as claimed in claim 1, it is characterised in that during write storage unit, corresponding wordline is put into high electricity Corresponding row in array is opened in position, and corresponding source electrode line is put height, the bit line of the storage unit is set low, remaining bit line is put It is high.