CN107516545A - A kind of MRAM chip and its self-test method - Google Patents
A kind of MRAM chip and its self-test method Download PDFInfo
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- CN107516545A CN107516545A CN201610423370.5A CN201610423370A CN107516545A CN 107516545 A CN107516545 A CN 107516545A CN 201610423370 A CN201610423370 A CN 201610423370A CN 107516545 A CN107516545 A CN 107516545A
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- memory cell
- mram
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- row
- test
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
- G11C29/30—Accessing single arrays
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/38—Response verification devices
- G11C29/42—Response verification devices using error correcting codes [ECC] or parity check
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
- G11C2029/1802—Address decoder
Abstract
The present invention provides a kind of MRAM chip, including one or more arrays, array includes the storage line being made up of mram memory cell, each array is connected with control circuit, control circuit includes row-address decoder, column address decoder, read-write controller and input and output and controlled, control circuit also includes self test controller, and each array includes multiple spare rows, and spare row is used for the row for replacing the mram memory cell with damage.The present invention also provides a kind of self-test method of MRAM chip.MRAM chip and its self-test method provided by the invention, by self-test, the data Cun Chudao of the storage line of the mram memory cell with damage detected is replaced in spare row, improves the data reliability and service life of MRAM chip.
Description
Technical field
The present invention relates to semiconductor chip field, and in particular to a kind of MRAM chip and its self-test method.
Background technology
On MRAM：
The background of the present invention is the maturation of MRAM technology.MRAM is a kind of new internal memory and memory technology, can be as SRAM/
The equally quick random read-writes of DRAM, can also as Flash flash memories permanent retention data after a loss of power.
It is local good that its economy is thought, the silicon area that unit capacity takes has very big advantage than SRAM, than such
The NOR Flash being commonly used in chip are also advantageous, bigger than embedded NOR Flash advantage.Its performance is also suitable
Good, read-write time delay is then best in various internal memories and memory technology close to best SRAM, power consumption.And MRAM unlike DRAM and
Flash is incompatible with standard CMOS semiconductor technique like that.MRAM can be integrated into logic circuit in a chip.
MRAM principle：
MRAM principle, it is to be based on a structure for being called MTJ (MTJ).It is pressed from both sides by two layers of ferrimagnet
One layer very thin of non-ferric magnetic dielectric composition, as shown in Figure 1 and Figure 2：
One layer of following ferromagnetic material is the reference layer for having fixed magnetisation direction, and ferromagnetic material above is variable magnetization
The memory layer in direction, its direction of magnetization can be in the same direction or reverse with fixed magnetization layer.Due to the effect of quantum physics, electric current can
So that through the tunnel barrier layer of centre, but MTJ resistance is relevant with the direction of magnetization of variable magnetization layer.The previous case resistance
It is low, as shown in Figure 1；Latter event resistance is high, as shown in Figure 2.
The process for reading MRAM is exactly that MTJ resistance is measured.Using newer STT-MRAM technologies, MRAM is write
Also it is fairly simple：Using than reading stronger electric current write operation is carried out through MTJ.One electric current from bottom to top is variable magnetization layer
It is set in the same direction with fixed bed, top-down circuit is set to it reversely.
MRAM framework
Each MRAM mnemon is made up of MTJ and metal-oxide-semiconductor.The door of metal-oxide-semiconductor is connected to the wordline of chip
It is responsible for switching on or off this unit, MTJ and metal-oxide-semiconductor are serially connected on the bit line of chip.Read-write operation is carried out on bit line, is such as schemed
Shown in 3：
One MRAM chip is made up of the array of one or more mram memory cells, and each array has some external electricals
Road, as shown in Figure 4：
Row-address decoder：The address received is become the selection of wordline
Column address decoder：The address received is become the selection of bit line
Read-write controller：Operation is write and (adds electric current) in reading (measurement) in control bit line
Input and output control：Data are exchanged with outside
It is seldom a part of due to imperfect made of technique although MRAM chip in principle can be erasable infinitely
Unit (typically smaller than a ten thousandth) can fail after the write operation of (several hundred million times) by many times.Although the ratio of failure
It is very low, but the amount of calculation in modern day computing systems is a lot, and the operational load that RAM chip is born is very heavy, so extremely low damage
Bad rate still can seriously reduce the service life of chip.
The content of the invention
In view of problems of the prior art,, will by Autonomous test it is an object of the invention to provide a kind of MRAM chip
What is detected has in the data Cun Chudao replacement spare rows of the storage line of the mram memory cell of damage, improves MRAM chip
Data reliability and service life.
The present invention also provides a kind of self-test method of MRAM chip.
The present invention provides a kind of MRAM chip, including one or more arrays, and array includes being made up of mram memory cell
Storage line, each array is connected with control circuit, and control circuit includes row-address decoder, column address decoder, read-write control
Device processed controls with input and output, and control circuit also includes self test controller, and each array includes multiple spare rows, and spare row is used
In the row for replacing the mram memory cell with damage.
Further, every a line of array includes ECC positions.
Further, each spare row includes row address register, for storing the MRAM with damage replaced
The address of the row of memory cell.
The present invention also provides a kind of self-test method of above-mentioned MRAM chip, comprises the following steps：
(1) when starting shooting, bus free when or the setting self-test time then, to storage line in array and used
Spare row carries out self-test.
Further, self test controller comprises the following steps to the storage line progress self-test in array in step (1)：
(11) by the data read-out of storage line, idle spare row is write；
(12) test is written and read to storage line；
(13) if storage line has the mram memory cell of damage, the address of storage line is write to the row address of spare row
Register；Otherwise the data of spare row are write back into storage line.
Further, self test controller includes to the spare row used the progress self-test in array in step (1)
Following steps：
(14) by the data read-out of the spare row used, idle spare row is write；
(15) test is written and read to the spare row used；
(16) if the spare row used has the mram memory cell of damage, the address of the spare row used is write
Enter the row address register of the spare row of free time；Otherwise the data of the spare row of free time are write back to the spare row used.
Further, step (12) or (15) readwrite tests comprise the following steps：
(21) write circuit of read-write controller is utilized, a mram memory cell is placed in high resistance state；
(22) mram memory cell is read；
(23) if mram memory cell is low resistance state, mram memory cell damage.
Further, step (12) or (15) readwrite tests comprise the following steps：
(24) write circuit of read-write controller is utilized, a mram memory cell is placed in high resistance state；
(25) mram memory cell is read；
(26) if mram memory cell is low resistance state, the write circuit of read-write controller is reused, by MRAM
Memory cell is placed in high resistance state；
(27) if mram memory cell is still low resistance state, mram memory cell damage.
Compared with prior art, MRAM chip and its self-test method provided by the invention, have the advantages that：It is logical
Self-test is crossed, the data Cun Chudao of the storage line of the mram memory cell with damage detected is replaced in spare row, carried
The high data reliability and service life of MRAM chip.
Brief description of the drawings
Fig. 1 is the low resistance state schematic diagram of MTJ；
Fig. 2 is the high-resistance state schematic diagram of MTJ；
Fig. 3 is mram memory cell；
Fig. 4 is the structural representation of MRAM chip；
Fig. 5 is the schematic diagram of the MRAM chip of one embodiment of the present of invention；
Fig. 6 is the self-test schematic diagram of the MRAM chip shown in Fig. 5.
Embodiment
As shown in figure 5, the MRAM chip of one embodiment of the present of invention, including one or more arrays, array include by
The storage line of mram memory cell composition, each array are connected with control circuit, and control circuit includes row-address decoder, row ground
Location decoder, read-write controller and input and output control, and control circuit also includes self test controller, for controlling self-test to grasp
Make；Each array includes multiple spare rows, and spare row is used for the row for replacing the mram memory cell with damage.
Self test controller is connected with address acquisition circuit, row-address decoder and read-write controller.
Each spare row includes row address register, for storing the mram memory cell with damage replaced
Capable address.
The specific implementation of spare row circuit：
An erasable non-volatile row address register is configured for each spare row, for storing replaced tool
There is the address of the row of the mram memory cell of damage, the register can use a specific MRAM storage area, during startup
It is read into general register, for example, if the standard row of each array is 1024 rows, then this register needs 10 ratios
It is special；
It is used for replacing a certain storage line if the spare row is selected, the address of storage line is stored in the row of the spare row
In address register；If the spare row is not used, a default illegal address can be write, if the spare row has damage
Bad mram memory cell, another default illegal address can be write.
MRAM chip also issues all spare rows in use, row address while row-address decoder is issued, standby
With the row, bad row 1, bad row 2 etc. for housing the mram memory cell with damage in row respectively, each spare row is the row received
Address is compared with the address in the row address register of oneself, if coincide, selects the spare row, while forbid row address
The output of decoder, as shown in Figure 6.
The self-test method of the MRAM chip of the present embodiment, comprises the following steps：
(1) when starting shooting, bus free when or the setting self-test time then, to storage line in array and used
Spare row carries out self-test.
Self-test has following several methods of operation：
To MRAM chip self-test after start, system waits self-test to reuse the MRAM chip after being fully completed；
System starts immediately after start, the instruction in self test controller detection bus, right during bus free
MRAM chip self-test；
In system operation, start every the fixed cycle to MRAM chip self-test.
Self test controller comprises the following steps to the storage line progress self-test in array in step (1)：
(11) by the data read-out of storage line, idle spare row is write；
(12) test is written and read to storage line；
(13) if storage line has the mram memory cell of damage, the address of storage line is write to the row address of spare row
Register；Otherwise the data of spare row are write back into storage line.
Self test controller comprises the following steps to the spare row used the progress self-test in array in step (1)：
(14) by the data read-out of the spare row used, idle spare row is write；
(15) test is written and read to the spare row used；
(16) if the spare row used has the mram memory cell of damage, the address of the spare row used is write
Enter the row address register of the spare row of free time；Otherwise the data of the spare row of free time are write back to the spare row used.
Step (12) or (15) readwrite tests comprise the following steps：
(21) write circuit of read-write controller is utilized, a mram memory cell is placed in high resistance state；
(22) mram memory cell is read；
(23) if mram memory cell is low resistance state, mram memory cell damage.
A readwrite tests is carried out for mram memory cell, may be caused to read as low resistance shape due to a variety of causes
State, so if when reading low resistance state, test is written and read again, to improve the accuracy of readwrite tests, step (12)
Or (15) readwrite tests comprises the following steps：
(24) write circuit of read-write controller is utilized, a mram memory cell is placed in high resistance state；
(25) mram memory cell is read；
(26) if mram memory cell is low resistance state, the write circuit of read-write controller is reused, by MRAM
Memory cell is placed in high resistance state；
(27) if mram memory cell is still low resistance state, mram memory cell damage.
In another embodiment, every a line of array includes ECC positions, that is, each storage line of array with it is each standby
All include ECC positions with row.
When the data read-out of the spare row for storage line/used, the spare row of free time is write, corresponding ECC positions is checked, is
It is no error in data to be present, if it does, before the spare row for storage line/used is write back, it is wrong that data are corrected according to ECC positions
By mistake.
Preferred embodiment of the invention described in detail above.It should be appreciated that one of ordinary skill in the art without
Creative work can is needed to make many modifications and variations according to the design of the present invention.Therefore, all technologies in the art
Personnel are available by logical analysis, reasoning, or a limited experiment on the basis of existing technology under this invention's idea
Technical scheme, all should be in the protection domain being defined in the patent claims.
Claims (8)
1. a kind of MRAM chip, including one or more arrays, array includes the storage line being made up of mram memory cell, each
Array is connected with control circuit, and the control circuit includes row-address decoder, column address decoder, read-write controller and input
Output control, it is characterised in that the control circuit also includes self test controller, and each array includes multiple standby
OK, the spare row is used for the row for replacing the mram memory cell with damage.
2. MRAM chip as claimed in claim 1, it is characterised in that every a line of the array includes ECC positions.
3. MRAM chip as claimed in claim 1, it is characterised in that each spare row includes row address register, is used for
Store the address of the row for the mram memory cell with damage replaced.
A kind of 4. self-test method of MRAM chip as described in claim any one of 1-3, it is characterised in that the self-test
Method comprises the following steps：
(1) start shooting when, bus free when or setting the self-test time then, to the storage line in array and used standby
Row carries out self-test.
5. the self-test method of MRAM chip as claimed in claim 4, it is characterised in that self test controller in step (1)
Self-test is carried out to the storage line in array to comprise the following steps：
(11) by the data read-out of the storage line, idle spare row is write；
(12) test is written and read to the storage line；
(13) if the storage line has the mram memory cell of damage, the address of the storage line is write into the spare row
Row address register；Otherwise the data of the spare row are write back into the storage line.
6. the self-test method of MRAM chip as claimed in claim 4, it is characterised in that self test controller in step (1)
Self-test is carried out to the spare row used in array to comprise the following steps：
(14) by the data read-out of the spare row used, idle spare row is write；
(15) test is written and read to the spare row used；
(16) if the spare row used has the mram memory cell of damage, by the ground of the spare row used
Location writes the row address register of the idle spare row；Otherwise the data of the idle spare row are write back into described made
Spare row.
7. the self-test method of the MRAM chip as described in claim 5 or 6, it is characterised in that step (12) or (15) read-write
Test comprises the following steps：
(21) write circuit of read-write controller is utilized, a mram memory cell is placed in high resistance state；
(22) mram memory cell is read；
(23) if the mram memory cell is low resistance state, the mram memory cell damage.
8. the self-test method of the MRAM chip as described in claim 5 or 6, it is characterised in that step (12) or (15) read-write
Test comprises the following steps：
(24) write circuit of read-write controller is utilized, a mram memory cell is placed in high resistance state；
(25) mram memory cell is read；
(26) if the mram memory cell is low resistance state, the write circuit of read-write controller is reused, by MRAM
Memory cell is placed in high resistance state；
(27) if the mram memory cell is still low resistance state, the mram memory cell damage.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610423370.5A CN107516545A (en) | 2016-06-15 | 2016-06-15 | A kind of MRAM chip and its self-test method |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201610423370.5A CN107516545A (en) | 2016-06-15 | 2016-06-15 | A kind of MRAM chip and its self-test method |
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| CN201610423370.5A Pending CN107516545A (en) | 2016-06-15 | 2016-06-15 | A kind of MRAM chip and its self-test method |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111899783A (en) * | 2019-05-06 | 2020-11-06 | 上海磁宇信息科技有限公司 | High-speed MRAM chip using write detection and data read-write method thereof |
| CN111951876A (en) * | 2019-05-15 | 2020-11-17 | 上海磁宇信息科技有限公司 | MRAM chip with writing detection function and dynamic redundancy and data reading and writing method thereof |
| CN112349321A (en) * | 2019-08-06 | 2021-02-09 | 上海磁宇信息科技有限公司 | Magnetic random access memory chip architecture using common reference voltage |
| CN115525482A (en) * | 2022-11-29 | 2022-12-27 | 深圳市航顺芯片技术研发有限公司 | Microcontroller chip start control method, device, chip and storage medium |
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| CN1278647A (en) * | 1999-06-18 | 2001-01-03 | 三菱电机株式会社 | Semiconductor device with test circuit capable of inhibiting enlargement of circuit scale and test apparatus for semiconductor device |
| CN1601652A (en) * | 2003-09-25 | 2005-03-30 | 株式会社东芝 | Semiconductor memory device and method of testing the device |
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- 2016-06-15 CN CN201610423370.5A patent/CN107516545A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1278647A (en) * | 1999-06-18 | 2001-01-03 | 三菱电机株式会社 | Semiconductor device with test circuit capable of inhibiting enlargement of circuit scale and test apparatus for semiconductor device |
| CN1601652A (en) * | 2003-09-25 | 2005-03-30 | 株式会社东芝 | Semiconductor memory device and method of testing the device |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111899783A (en) * | 2019-05-06 | 2020-11-06 | 上海磁宇信息科技有限公司 | High-speed MRAM chip using write detection and data read-write method thereof |
| CN111899783B (en) * | 2019-05-06 | 2022-06-03 | 上海磁宇信息科技有限公司 | High-speed MRAM chip using write detection and data read-write method thereof |
| CN111951876A (en) * | 2019-05-15 | 2020-11-17 | 上海磁宇信息科技有限公司 | MRAM chip with writing detection function and dynamic redundancy and data reading and writing method thereof |
| CN111951876B (en) * | 2019-05-15 | 2022-06-03 | 上海磁宇信息科技有限公司 | MRAM chip with writing detection function and dynamic redundancy and data reading and writing method thereof |
| CN112349321A (en) * | 2019-08-06 | 2021-02-09 | 上海磁宇信息科技有限公司 | Magnetic random access memory chip architecture using common reference voltage |
| CN112349321B (en) * | 2019-08-06 | 2024-03-12 | 上海磁宇信息科技有限公司 | Magnetic random access memory chip architecture using common reference voltage |
| CN115525482A (en) * | 2022-11-29 | 2022-12-27 | 深圳市航顺芯片技术研发有限公司 | Microcontroller chip start control method, device, chip and storage medium |
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Application publication date: 20171226 |