CN112349321B - Magnetic random access memory chip architecture using common reference voltage - Google Patents
Magnetic random access memory chip architecture using common reference voltage Download PDFInfo
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- CN112349321B CN112349321B CN201910722138.5A CN201910722138A CN112349321B CN 112349321 B CN112349321 B CN 112349321B CN 201910722138 A CN201910722138 A CN 201910722138A CN 112349321 B CN112349321 B CN 112349321B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1697—Power supply circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1673—Reading or sensing circuits or methods
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Abstract
The application provides a magnetic random access memory chip architecture using a common reference voltage, which comprises a plurality of memory arrays and at least one read reference system, wherein the read reference system can generate the common read reference voltage, the read reference system is used in a read circuit of the memory arrays, the resistance characteristics of magnetic tunnel junctions are prevented from producing wide variation, the resistance of the memory cell arrays is converted into voltage signals to be output through a plurality of voltage detectors of the memory arrays and source lines and bit lines of selected memory cells connected through control of row and column decoders, and the reference voltage generated by the reference cells is stored on a capacitor.
Description
Technical Field
The present invention relates to the field of memory technology, and more particularly, to a magnetic random access memory chip architecture using a common reference voltage.
Background
The read circuit of the MRAM (Magnetic random access memory, MRAM) needs to detect the resistance of the MRAM memory cell, and since the resistance of the magnetic tunnel junction (MTJ; magnetic Tunnel Junction) drifts with temperature, the general method is to use the memory cell on the chip that has been written to a high resistance state or a low resistance state as a reference cell, and then use a Sense Amplifier (Sense Amplifier) to compare the resistances of the memory cell and the reference cell. Because the resistances of the memory cells at different positions in the magnetic random access memory cell array are slightly different due to different lengths of the connecting wires, the memory cells in the same row are compared with the reference cells, and the difference of the resistances of the wires is mostly counteracted, but the reference cells occupy a part of the area of the array after all, so that the usable area of the memory cells is reduced, the reference cells and the memory cells must be simultaneously electrified during the reading operation, the power consumption of a chip is increased, the reference cells consist of a plurality of columns, namely, the number of bit columns read each time must be enough to ensure the control of statistical deviation, but the larger the number of the bit columns read, the larger the area of the reference cells and the power consumption are increased.
U.S. patent No. Pat.7321507 discloses a technique for MRAM reference cell deployment in subarrays. Wherein the MRAM reference cell sub-array provides a midpoint reference current to the sense amplifier. MRAM cells of the MRAM reference cell sub-array are arranged in rows and columns. A bit line is associated with each column of the subarray. Bit lines that are coupled in pairs of columns are disposed proximate to the sense amplifiers. The MRAM cells of the first pair of pillars are programmed to a first magnetoresistive state and the MRAM cells of the second pair of pillars are programmed to a second magnetoresistive state. When a row of data MRAM cells is selected for reading, a row of paired MRAM reference cells are placed in parallel to generate a midpoint reference current for sensing.
U.S. Pat. No. 8693273 discloses a Sense Amplifier (Sense Amplifier) that includes a voltage detector or a current detector. The sense amplifier generates reference currents from programmed and non-programmed reference cells for reading signals from a Magnetic Random Access Memory (MRAM) including Magnetic Tunnel Junction (MTJ) cells. The average current is determined by one sense amplifier and a reference cell of the n sense amplifiers, which acts as the average current between the programmed reference cell and the non-programmed reference cell, approximately midway between the two states. That is, when the MRAM performs data reading, a plurality of P-state and AP-state reference cells are simultaneously powered on in this way, and the reference voltages are obtained on average. The sense amplifier may be a fully differential or non-differential sense amplifier.
Disclosure of Invention
In order to solve the above-mentioned problems, an object of the present invention is to provide a magnetic random access memory chip architecture using a common reference voltage, which is based on the fact that a reference cell is independent from a magnetic random access memory cell array and forms an independent read reference system, and includes a controller and a voltage detector, wherein the reference cell generates the reference voltage, and stores the reference voltage on a capacitor, and the reference voltage is converted into a voltage signal and outputted as the common reference voltage.
The aim and the technical problems of the application are achieved by adopting the following technical scheme.
According to the magnetic random access memory chip architecture using the common reference voltage, the magnetic random access memory chip architecture comprises a plurality of memory arrays and at least one read reference system, wherein a readout circuit of each memory array comprises a plurality of voltage detectors, and the resistors of the magnetic random access memory cell arrays are converted into voltage signals to be output through the control connection of a row decoder and a column decoder to source lines and bit lines of the selected magnetic random access memory cell arrays; the comparator is positioned in the memory array, one end of the comparator is connected with the voltage detector to receive the voltage signal output in the read-out circuit of the memory cell array of the magnetic random access memory, the other end of the comparator receives the common reference voltage output by the read reference system, the common reference voltage is generated by the reference cell group, the reference voltage is output to a capacitor through a switch and is stored on the capacitor, the reference voltage is converted into a voltage signal again, the voltage signal is output to be the common reference voltage, and the comparator compares the voltage signal of the memory cell array of the magnetic random access memory with the common reference voltage; the read reference system can be selectively designed in the memory array or independent of the memory array, comprises a controller and a voltage detector, converts the average resistance of a group of reference units into a voltage signal, outputs the voltage signal into a common reference voltage, and uses the generated common reference voltage in a read circuit of the memory array so as to avoid the wide variation of the resistance characteristic of a magnetic tunnel junction; .
The technical problem of the application can be further solved by adopting the following technical measures.
In one embodiment of the present application, the voltage of the read reference system is output to a capacitor through a switch for storage.
In an embodiment of the present application, the mram chip architecture using a common reference voltage is characterized in that the reference cell group of the read reference system may be performed in parallel.
In an embodiment of the present application, the mram chip architecture using a common reference voltage is characterized in that the controller of the read reference system periodically measures the resistance of the reference cell group for outputting a voltage to the capacitor and recharging, and then turns off the switch to keep the capacitor in a voltage state.
In an embodiment of the present application, the mram chip architecture using a common reference voltage is characterized in that an output of each of the voltage detectors of the memory array is connected to a comparator.
In an embodiment of the present application, the mram chip architecture using a common reference voltage is characterized in that the comparator of the memory array is responsible for comparing the output of the voltage detector with the common reference voltage and outputting the read data.
In an embodiment of the present application, the mram chip architecture using a common reference voltage is characterized in that the memory array is configured with a buffer regulator, and the buffer regulator may receive an output from the row decoder and compensate for a deviation due to a wire resistance according to an address of a row.
In an embodiment of the application, the magnetic random access memory chip architecture using the common reference voltage is characterized in that when the buffer adjuster compensates for the deviation caused by the wire resistance, the common reference voltage is increased and compensated, then the column address is output according to the column address of the column decoder, the column address can be obtained, the adjustable resistance is further adjusted, the adjusted reference voltage is obtained, and then the voltage is output.
The present application provides a magnetic random access memory chip architecture using a common reference voltage, which is based on the fact that a reference unit is independent from a magnetic random access memory cell array and forms an independent read reference system, and the magnetic random access memory chip architecture comprises a controller and a voltage detector, wherein the reference unit generates the reference voltage, the reference voltage is stored on a capacitor, and is converted into a voltage signal to be output into the common reference voltage.
Drawings
FIG. 1 is a schematic diagram of a conventional reference cell according to an embodiment of the present application;
FIG. 2 is a schematic diagram of a MRAM chip architecture using a common reference voltage according to an embodiment of the present application;
FIG. 3 is a schematic diagram of a buffer regulator architecture of a MRAM chip using a common reference voltage according to an embodiment of the present application;
FIG. 4 is a schematic diagram of a buffer regulator common reference voltage compensation architecture of a MRAM chip using a common reference voltage according to an embodiment of the present application.
Symbol description
01 Bit line (Bit line); 02, a reference unit; 03 column address decoder; 04 a Magnetic Random Access Memory (MRAM) memory cell array; 05, read-write control; 06, input and output control; 07 Word line; 08 row address interface; 09, address acquisition; 10, address; 11, other signals; 12, data; a row decoder; a column decoder 14; 15, a voltage detector; a comparator; 17 a storage array; 18, a common reference voltage; 19, reading a reference system; 20, a switch; a controller; a voltage detector 22; 23, parallel reference unit group; 24, a capacitor; 25, a buffer adjuster; 26, an adjustable resistor; 27, a current source; 28, adjusting voltage output; 29 row decoder output;
Detailed Description
The following description of the embodiments refers to the accompanying drawings, which illustrate specific embodiments in which the invention may be practiced. The terms of directions used in the present invention, such as "up", "down", "front", "back", "left", "right", "inside", "outside", "side", etc., refer only to the directions of the attached drawings. Accordingly, directional terminology is used to describe and understand the invention and is not limiting of the invention.
The drawings and description are to be regarded as illustrative in nature, and not as restrictive. In the drawings, like structural elements are denoted by like reference numerals. In addition, for the sake of understanding and convenience of description, the size and thickness of each component shown in the drawings are arbitrarily shown, but the present invention is not limited thereto.
In the drawings, the scope of the arrangement of devices, systems, components, circuits, etc. is exaggerated for clarity, understanding, and convenience of description. It will be understood that when an element is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present.
In addition, in the description, unless explicitly described to the contrary, the word "comprising" will be understood to mean comprising the recited component, but not excluding any other components. Further, in the specification, "above" means above or below the target assembly, and does not mean necessarily on top based on the direction of gravity.
In order to further describe the technical means and effects of the present invention for achieving the predetermined purposes, the following description refers to a magnetic random access memory chip architecture using a common reference voltage according to the present invention, and its specific embodiments, structures, features and effects are described in detail below.
Fig. 1 is a schematic diagram of a conventional reference unit according to an embodiment of the present application, and please be understood together. In general, since the resistance of the magnetic tunnel junction becomes unstable with the rise and fall of temperature, the memory cell having been written in a high-resistance state or a low-resistance state on the chip is generally used as the reference cell 02, and therefore, a block of area is allocated to the reference cell 02 in the mram cell array 04, and the resistance of the memory cell and the reference cell 02 is compared by a sense amplifier. Since the lengths of the connected wires are different in the memory cells of different positions in the mram memory cell array 04, the resistances are slightly different, the memory cells of the same row are compared with the reference cells 02, and the difference of the resistances of the wires of the memory cells and the reference cells 02 is mostly counteracted, but the reference cells 02 occupy a part of the area of the array, so that the usable area of the memory cells is reduced.
FIG. 2 is a schematic diagram of a magnetic random access memory chip architecture using a common reference voltage according to an embodiment of the present application, including a plurality of memory arrays 17 and at least one read reference system 19, wherein the read circuit of the memory arrays 17 further includes a plurality of voltage detectors 15, and the voltage detectors 15 are connected to the source lines and bit lines of the selected magnetic random access memory cell array 04 through the control of the row decoder 13 and the column decoder 14 to convert the resistance of the magnetic random access memory cell array 04 into a voltage signal for outputting; a plurality of comparators 16, located in the memory array 17, one end of the comparator 16 is connected to the voltage detector 15 to receive the voltage signal output from the read circuit of the magnetic random access memory cell array 04, and the other end receives the common reference voltage 18 output from the read reference system 19, the common reference voltage 18 is generated by the parallel reference cell group 23 to generate a reference voltage, the reference voltage is output to a capacitor 24 through a switch 20 via the voltage detector 22 and stored in the capacitor 24, the reference voltage is converted into a voltage signal again, and the voltage signal is output as the common reference voltage 18, and in addition, the comparator 16 in the memory array 17 compares the voltage signal of the magnetic random access memory cell array 04 with the common reference voltage 18 and then outputs; the read reference system 19, which can be selectively designed in the memory array 17 or independent of the memory array 17, the read reference system 19 further includes a controller 21 and a voltage detector 22, the voltage detector 22 is configured to measure the average resistance of a group of reference cells, if the reference cells in the group of reference cells are connected in parallel to form the parallel reference cell group 23, the voltage detector 22 is configured to convert the voltage of the parallel reference cell group 23 into a voltage signal, and further output the voltage signal as the common reference voltage 18, and the generated common reference voltage 18 is supplied to the readout circuit of the memory array 17 to avoid a wide variation of the magnetic tunnel junction resistance characteristics.
FIG. 3 is a schematic diagram of a buffer regulator architecture of a MRAM chip using a common reference voltage according to an embodiment of the present application. The buffer regulator 25 in the memory array 17 is present for compensating for the deviation of the wire resistance, and since the buffer regulator 25 receives the output from the row decoder 13, the deviation due to the wire resistance is compensated for according to the position of the row and then outputted, as shown in fig. 2, the output thereof is compared with the output of the voltage detector 15 via the comparator 16, and finally the read data is outputted.
Fig. 4 is a schematic diagram of a buffer regulator common reference voltage compensation architecture of a mram chip using a common reference voltage according to the embodiment of the present application, in which a buffer regulator 25 is configured in each of the memory arrays 17 of the mram memory cell array 04, the buffer regulator 25 can receive an output from the column decoder 13, and compensates for a deviation due to a wire resistance according to an address of a column, and when the buffer regulator 25 compensates for a deviation due to a wire resistance, the buffer regulator 25 increases the input common reference voltage 18 and compensates, and then outputs according to a column address of the column decoder 13, so that a column address can be obtained, and further adjusts the adjustable resistor 26, and thus obtains an adjusted reference voltage, and then adjusts the voltage output 28.
The magnetic random access memory chip architecture using a common reference voltage generates a common read reference voltage 18 through a read reference system 19 for use by a readout circuit of a memory array 17, prevents the resistance characteristics of magnetic tunnel junctions from producing a wide range of variations, and converts the resistance of the magnetic random access memory cell array 04 into a voltage signal output by connecting the source lines and bit lines of the selected magnetic random access memory cell array 04 through the voltage detector 15 of the memory array 17 and the control connection of the row decoder 13 and the column decoder 14.
The terms "in an embodiment" and "in various embodiments" and the like are used repeatedly. This phrase generally does not refer to the same embodiment; but it may also refer to the same embodiment. The terms "comprising," "having," "including," and the like are synonymous, unless the context clearly dictates otherwise.
The foregoing description is only illustrative of the present application and is not intended to be limiting, since the present application is described in terms of specific embodiments, but rather is not intended to be limited to the details of the embodiments disclosed herein, and any and all modifications, equivalent to the above-described embodiments, may be made without departing from the scope of the present application, as long as the equivalent changes and modifications are within the scope of the present application.
Claims (8)
1. The magnetic random memory chip architecture using the common reference voltage comprises a plurality of memory arrays and at least one read reference system, wherein a readout circuit of the memory arrays comprises a plurality of voltage detectors, and the resistances of the memory arrays of the magnetic random memory are converted into voltage signals to be output through the control connection of a row decoder and a column decoder to source lines and bit lines of the memory arrays of the magnetic random memory; the comparators are positioned in the memory array, one end of each of the comparators is connected with a voltage detector to receive the voltage signal output of the magnetic random memory cell array, and the other end of each of the comparators receives the common reference voltage output by the read reference system and compares the voltage signal of the magnetic random memory cell array with the common reference voltage; and
the read reference system comprises a controller and a voltage detector, and converts the average resistance of a group of reference units into a voltage signal, and outputs the voltage signal as a common reference voltage, wherein the common reference voltage is used in a read circuit of the memory array so as to avoid the occurrence of wide variation of the resistance characteristic of a magnetic tunnel junction.
2. The mram chip architecture of claim 1, wherein the voltage of the read reference system is output to a capacitor through a switch for storage.
3. The mram chip architecture of claim 1, wherein the reading of the reference cell groups of the reference system is performed in parallel.
4. The mram chip architecture using a common reference voltage of claim 1, wherein the controller of the read reference system periodically measures the resistance of the reference cell group for outputting a voltage to a capacitor and recharging, and then turns off a switch to keep the capacitor in a voltage state.
5. The mram chip architecture of claim 1, wherein the output of each of the voltage detectors of the memory array is coupled to a comparator.
6. The mram chip architecture of claim 5, wherein the comparator of the memory array is responsible for comparing the output of the voltage detector with a common reference voltage and outputting the read-out data.
7. The mram chip architecture of claim 1, wherein the memory array is configured with a buffer regulator that receives an output from the column decoder and compensates for deviations due to the resistance of the conductive lines based on the column address.
8. The mram chip architecture of claim 7, wherein the buffer adjuster increases the common reference voltage and compensates for a deviation of the wire resistance, and then outputs a column address according to a column address of the column decoder, and further adjusts the adjustable resistance, and obtains an adjusted reference voltage, and then outputs the voltage.
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