CN101388246A - Ovonics unified memory - Google Patents
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- CN101388246A CN101388246A CNA2007101496502A CN200710149650A CN101388246A CN 101388246 A CN101388246 A CN 101388246A CN A2007101496502 A CNA2007101496502 A CN A2007101496502A CN 200710149650 A CN200710149650 A CN 200710149650A CN 101388246 A CN101388246 A CN 101388246A
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Abstract
The invention relates to a phase changing memory, which comprises more than one main storage unit, more than one reference storage unit and a comparing circuit, wherein the main storage unit produces at least a detecting signal, each main storage unit is equipped with a record layer, the reference storage unit produces at least a reference signal, each reference storage unit is equipped with a record layer, and the comparing circuit is used to compare the detecting signal and the reference signal to produce at least an output signal which corresponds to a comparing result. Electric property work curve of at least a record layer in a plurality of reference storage units is different from the electric property work curve of at least a record layer in a plurality of main storage unit, thereby being used to modulate the reference signal to increase the detection ability of the comparing circuit.
Description
Technical field
The present invention is relevant for Ovonics unified memory (Phase Change Memory), and is particularly to a kind of reference memory unit that Ovonics unified memory reads that is used for.
Background technology
Along with the growth of portable use product, the demand of nonvolatile memory has the trend that day by day increases.Ovonics unified memory is owing to have numerous competitive characteristics such as speed, power, fiduciary level, manufacturing integrated level and cost, has been regarded as the non-volatile memory technologies of tool potentiality of future generation.
Ovonics unified memory mainly utilizes the change of resistance to come as store status, therefore design one desirable read circuit correctly read in the storage array state of storage unit be have necessary.Generally speaking, in an accumulator system, except main main memory unit, one group of reference memory unit of additional designs.This group reference memory unit is mainly used to produce reference signal, and is used to provide to reading circuit to compare with this main signal that main memory unit was produced.Therefore, in order to make storer when carrying out read operation, can not cause the interpretation mistake of memory state because of the error of reference signal, it is necessary designing one group of desirable reference memory unit.
Desirable reference memory unit must possess following several characteristics: (1) makes simple, does not need extra manufacture craft or complex circuit design to realize; (2) possess higher stable degree and fiduciary level, this means tolerable manufacture craft homogeneity deviation and the memory state that causes changes; (3) possess the adjustable characteristic of state, and do not lose efficacy because of the change of element state or structure.In other words, applicable to the different elements structure Design.
The structural representation of the Ovonics unified memory 100 that Fig. 1 is proposed for calendar year 2001 Ovonyx company, it is to have parallel reference memory unit.As shown in the figure, Ovonics unified memory 100 comprises main memory array 120 (comprising four lines C1 to C4), reference memory array 130 (comprising two row C5 and C6 in parallel) and a comparator circuit 140.Wherein this main memory array 120 comprises a plurality of storage unit 121, and this reference memory array 130 comprises a plurality of storage unit 131, and has identical structure in storage unit 121 and 131.When storer 100 when carrying out read operation, memory array 120 can provide the detection signal SSE1 to SSE4 of corresponding its store status according to its store status, and reference memory array 130 can provide a reference signal SRE.After 140 couples of these a plurality of detection signal SSE1 to SSE4 of comparator circuit and reference signal SRE compare, promptly can read the data in the storage unit 121 that is stored in memory array 120.Yet, because the practice of the storage unit 131 of the C5 that reference memory array 130 employings two row are in parallel and the storage unit 121 tool same structures of C6 and main memory array, this reference signal SRE that produces except allowing is more nonelastic and be not easy to adjust its value, also may allow this reference signal SRE be partial to detection signal SSE under a certain store status, so the deviation on the manufacture craft cause the error of sentence read result easily.
For example, when the store status of memory array 120 is respectively Reset Status (high resistance state) and set condition (low resistance state), the pressure reduction of detection signal SSE and reference signal SRE is respectively:
ΔV
reset≡V
sense-V
reference＝I
read1×R
reset-I
read2×(R
reset‖R
set) (1)
ΔV
set≡V
sense-V
reference＝I
read1×R
set-I
read2×(R
reset‖R
set) (2)
I wherein
Read1For putting on the electric current that reads of memory array 120, and I
Read2For putting on the electric current that reads of reference memory array, R
SetFor storage unit is in the resistance value (be called set resistance) of set condition (low resistance state) and R
ResetBe in the resistance value (be called and reset resistance) of Reset Status (high resistance state) for storage unit.In order to make reference signal, read electric current I more near the mean value of the reset current of two store statuss
Read2Usually be set at and read electric current I
Read1Twice, therefore:
|ΔV
reset|＝|V
sense-V
reference|＝I
read1×[R
reset-2(R
reset‖R
set)] (3)
|ΔV
set|＝|V
sense-V
reference|＝I
read1×[2(R
reset‖R
set)-R
set] (4)
Owing to reset resistance R
ResetUsually much larger than setting resistance R
Set(surpassing more than hundred times usually), therefore | Δ V
Reset| enough big, yet | Δ V
Set| but relatively more weak and unreliable, thus the interpretation mistake of comparator circuit 140 caused.
Summary of the invention
The invention provides a kind of Ovonics unified memory, it has the primary memory block and the reference memory block of the storage unit of different structure, with so that can be different from the state of the storage unit of primary memory block with reference to the state of the storage unit of memory block, thereby can the reference signal that produce with reference to memory block can be modulated, and improve the detectability of comparator circuit.
The invention provides a kind of Ovonics unified memory, comprise more than one main memory unit, produce at least one detection signal, wherein each this main memory unit has a record layer, and this recording layer is programmed at least one first resistance and one second resistance; More than one reference memory unit produces at least one reference signal, and wherein each this reference memory unit has a recording layer, and this recording layer is able to programme to change its resistance value; And a comparator circuit, be coupled to these a plurality of main memory cell arrays and this a plurality of reference memory cell array, in order to relatively this at least one detection signal and this at least one reference signal, and produce the output signal of at least one correspondence in comparative result.
The electrical working curve of at least one recording layer is different from the electrical working curve of the central at least one recording layer of these a plurality of main memory units in the middle of these a plurality of reference memory units.In one embodiment, the size (as sectional area) of the central at least one recording layer of these a plurality of reference memory units is different from the size of the central at least one recording layer of these a plurality of main memory units.In another embodiment, the contact area of central at least one recording layer of these a plurality of reference memory units and heating electrode is different from the contact area of central at least one recording layer of these a plurality of main memory units and heating electrode.
Description of drawings
Fig. 1 is the structural representation of a conventional digital Ovonics unified memory;
Fig. 2 is the calcspar of the Ovonics unified memory 200 of demonstration one embodiment of the invention;
Fig. 3 is the calcspar of the Ovonics unified memory 300 of demonstration another embodiment of the present invention;
Fig. 4 A and 4B are the reset current of first embodiment of the structural drawing that shows main memory unit and reference memory unit respectively and the storage unit variation relation figure with the recording layer sectional area; And
Fig. 5 A and 5B for the reset current of second embodiment that shows main memory unit and the structural drawing of reference memory unit respectively and storage unit with the variation relation figure that contacts area between recording layer and heating electrode embolism;
The main element symbol description
The 100-Ovonics unified memory
The memory array that 120-is main
The 121-storage unit
130-reference memory array
The 131-storage unit
The 140-comparator circuit
The 200-Ovonics unified memory
220-primary memory block
The 221-main memory unit
230-reference memory block
The 231-reference memory unit
The 240-comparator circuit
241_1 to 241_4-first input
242_1 to 242_4-second input
The 300-Ovonics unified memory
320-reference memory block
331
1And 331
2-first and second reference memory unit
41
1And 41
2-top electrode
42
1And 42
2-recording layer
43
1And 43
2-heating electrode embolism
44
1And 44
2-bottom electrode
52
1And 52
2-recording layer
53
1And 53
2-heating electrode embolism
C1-C6-is capable
The CL1-CL6-line
The NR-reference mode
The R1-R4-row
The RL1-RL4-alignment
RML, RMLR, RML1 and RML2-recording layer
QM, QMR, QMR1, QMR2-switching transistor
The VA-reference voltage
Embodiment
Fig. 2 is the calcspar of the Ovonics unified memory 200 of demonstration one embodiment of the invention.As shown in the figure, Ovonics unified memory 200 comprises a primary memory block 220, a reference memory block 230 and a comparator circuit 240.
Primary memory block 220 comprises a plurality of main storage units 221.In embodiment, these a plurality of main storage units 221 are arranged at least delegation and at least one row and constitute an array, for example be that the four lines C1 to C4 and four among this figure is listed as R1 to R4.Primary memory block 220 also comprises at least one line and at least one alignment, each row (row) line is gone up all main storage units 221 for coupling a corresponding row (row) respectively, for example be the four lines line CL1 to CL4 and four alignment RL1 to RL4 among this figure, wherein each line CL1 to CL4 is the main storage unit 221 that is coupled to a corresponding row C1 to C4 respectively, and each alignment RL1 to RL4 is for being coupled to the main storage unit 221 of a respective column R1 to R4 respectively.Each main storage unit 221 comprises that a switching transistor QM and a recording layer RML are coupled to this a switching transistor QM and a reference voltage VA.Must notice that the position of switching transistor QM and recording layer RML is interchangeable.
When desire changes the resistance of recording layer of certain delegation or a certain main storage unit that lists 221 (write operation), change this voltage that is listed as pairing alignment so that all are coupled to the switching transistor QM conducting of this alignment, and apply an electric current (not shown) makes this main memory unit 221 to the pairing line of this row recording layer RML this electric current that circulates.This electric current can be programmed for different resistance with the recording layer RML of main memory unit 221.The recording layer of each main storage unit 221 has an electrical working curve, its expression circulates in the relation between the resistance (depending primarily on this recording layer RML) of recording layer of the electric current of recording layer of this main storage unit 221 and this main storage unit 221, or is added on the relation between the resistance of recording layer of the voltage of recording layer of this main storage unit 221 and this main storage unit 221.In embodiment, the recording layer of each main storage unit 221 has identical electrical working curve.The recording layer RML of each main storage unit 221 is programmed at least one first resistance and one second resistance, for example is respectively replacement resistance and sets resistance, uses so that this main storage unit 221 can store and provide a bit above data.
Primary memory block 220 is in order to produce at least one detection signal.As shown in Figure 2, the capable C1 to C4 of main storage unit 221 for respectively by line CL1 to CL4 to provide other detection signal SS1 to SS4 to comparator circuit 240.When the resistance of the recording layer of desiring to read certain delegation or a certain main storage unit that lists 221, method is to change this to be listed as the voltage of pairing alignment so that all are coupled to the switching transistor QM conducting of this alignment, and makes one first to read the recording layer that electric current I RE1 (not shown) circulates in pairing line of this row and pairing main memory unit.Must notice that this first reads electric current I RE1 and must enough hang down resistance with the recording layer of being avoided changing main memory unit 221.In embodiment, these a plurality of detection signals first read the detection voltage that recording layer that electric current I RE1 circulates in this corresponding main memory unit produces for this.Therefore, when the recording layer RML of main storage unit 221 was programmed for first resistance R 1 and second resistance R 2 respectively, this detection voltage was for equaling R1 * IRE1 and R2 * IRE1 respectively.
At least one structure is for being different from this a plurality of main storage units 221 central at least one structures in the middle of these a plurality of reference memory units 231, with so that in the middle of these a plurality of reference memory units 231 the electrical working curve of at least one recording layers be the electrical working curve that is different from least one recording layers in the middle of these a plurality of main storage units 221, thereby make this reference resistance RR be different from this first resistance R 1 and second resistance R 2.In embodiment, the recording layer of each main storage unit 221 has identical electrical working curve, and the recording layer of each reference memory unit 231 has identical electrical working curve, and the electrical working curve of the recording layer of these a plurality of main storage units 221 is different from the electrical working curve of the recording layer of reference memory unit 231.The detailed structure of main storage unit 221 and reference memory unit 231 will be narrated in the related description of following each embodiment.
The reason that the electrical working curve of the central at least one recording layer of these a plurality of reference memory units is different from the electrical working curve of the central at least one recording layer of these a plurality of main memory units is so can make this reference resistance to be different from this first resistance and second resistance.By this, be that order first reads electric current I RE1 and equals second reading power taking stream IRE2, when the recording layer of these a plurality of main memory units is programmed for first and second resistance, pairing detection voltage R1 * IRE1 and R2 * IRE1 are all inequality with reference voltage RR * IRE2, thereby comparator circuit 240 can be differentiated the store status of Ovonics unified memory by the gap between detection voltage and reference voltage.
In embodiment, no matter which store status this main memory unit is, this difference that detects voltage and this reference voltage is greater than a predetermined voltage difference, thereby the comparative result that comparator circuit 240 is produced has higher accuracy.
In one embodiment, read that electric current I RE1 equals IRE2 substantially and when the recording layer RML of main storage unit 221 only was programmed for first resistance R 1 and second resistance R 2 (R2〉R1), reference resistance RR can be adjusted to (R1+R2)/2 when first.Thus, when the recording layer RML of Ovonics unified memory 221 only is programmed for first resistance R 1 and second resistance R 2 (R2〉R1), this reference voltage equals the mean value of one first voltage and one second voltage substantially, and wherein this first and second voltage is respectively pairing detection voltage when the recording layer of this main memory unit is respectively first and second resistance.When detect voltage less than and during greater than reference voltage, comparator circuit 240 can judge that the recording layer RML of main storage unit 221 is programmed for first resistance R 1 and second resistance R 2 (R2〉R1) respectively.In addition, no matter when the recording layer RML of this main storage unit 221 is programmed for first resistance R 1 and second resistance R 2 (R2〉R1) respectively, the pressure reduction that detects between voltage and reference voltage all equals (R2-R1) * IRE/2.In known technology shown in Figure 1, as previously mentioned, when the recording layer RML of main storage unit 221 was programmed to second resistance R 2, its reference voltage and the pressure reduction that detects between voltage were approaching zero.Obviously as can be known, (R2-R1) * IRE/2 is much larger than zero, so the accuracy of the comparative result that produced of the comparator circuit 240 of present embodiment is much larger than the accuracy of known technology.
Must note, not be restricted to reference to memory block 230 and be arranged as delegation.In all the other embodiment, have more than the delegation with reference to memory block 230.Fig. 3 is the calcspar of the Ovonics unified memory 300 of demonstration another embodiment of the present invention.This figure omits its explanation with the interior similar elements of Fig. 2 with identical cross reference number.As shown in Figure 3, reference memory unit 331 has first reference memory unit 331
1And second reference memory unit 331
2, C5 and C6 are arranged in rows respectively.First reference memory unit 331 on the row C5
1Be coupled by a line CL5, and the reference memory unit 331 on the row C6
2Be coupled by a line CL6, be coupled to comparator circuit 240 by a reference line C LR again and line CL5 and CL6 are coupled to a reference mode NR.Each first reference memory unit 331
1Recording layer RMLR1 be programmed at least one first reference resistance RR1, each second reference memory unit 331
2Recording layer RMLR2 be programmed at least one second reference resistance RR2.In embodiment, this first reference resistance RR1 is that replacement resistance and this second reference resistance RR2 of recording layer RMLR1 is the setting resistance of recording layer RMLR2.In another embodiment, this first reference resistance RR1 is that setting resistance and this second reference resistance RR2 of recording layer RMLR1 is the replacement resistance of recording layer RMLR2.
First reference memory unit 331
1With second reference memory unit 331
2Structure can be identical also can be different.In addition, first reference memory unit 331
1With second reference memory unit 331
2One of them structure is the structure that is different from these a plurality of main storage units 221, uses so that first reference memory unit 331
1With second reference memory unit 331
2The electrical working curve of one of them recording layer is the electrical working curve that is different from the recording layer of these a plurality of main storage units 221.In embodiment, reference signal SSR is that second reading power taking stream IRE2 circulates in the reference voltage that the recording layer of first and second reference memory unit produces.Therefore when first reference memory unit 331
1Recording layer RMLR1 before be programmed for this first reference resistance RR1 and this second reference memory unit 331
2Recording layer RMLR2 when before being programmed for this second reference resistance RR2, this reference voltage equals (RR1 ‖ RR2) * IRE2.Similarly, first reference memory unit 331
1With second reference memory unit 331
2The electrical working curve of central at least one recording layer is different from the electrical working curve of the recording layer of these a plurality of main storage units 221, its reason is so can make reference voltage (RR1 ‖ RR2) * IRE2 to equal (R1+R2) * IRE2/2 substantially, thereby makes the accuracy of the comparative result that comparator circuit 240 produced be height than known technology.Relative high person among this reference resistance RR1 and this second reference resistance RR2 is different from this first resistance R 1 and the relative high person of second resistance R 2, that is is different from second resistance R 2 in the present embodiment.Moreover relative low person among this reference resistance RR1 and this second reference resistance RR2 is different from this first resistance R 1 and the relative low person of second resistance R 2, that is is different from first resistance R 1 in the present embodiment.
In addition, must notice that in the embodiment of Fig. 2 and 3, the Ovonics unified memory of each row is connected to the reference memory unit of single row.Yet, in all the other embodiment, reference memory unit arranged and made the Ovonics unified memory of each row be connected to the above reference memory unit of row.
In addition, must notice that Fig. 2 and 3 embodiment are extensible to connect a reference memory unit group for the Ovonics unified memory of each row.This reference memory unit group comprises the reference memory unit of (n) more than, and at least one structure is the structure that is different from these a plurality of main storage units 221 in the middle of these a plurality of reference memory units.In Fig. 2, n=1.In Fig. 3, n=2.The connected mode of these a plurality of reference memory units is not defined as parallel connection, and various connected modes can be arranged.The equivalent resistance that reference voltage equals a reference memory unit group is multiplied by one and reads electric current.
In addition, must notice that in the embodiment of Fig. 2 and 3, the line CL1 to CL4 of main storage unit 221 is for being coupled to different detecting amplifier SA1 to SA4 respectively.Yet in all the other embodiment, the line CL1 to CL4 of main storage unit 221 can be coupled to identical detecting amplifier respectively.For example, in another embodiment, comparator circuit 240 comprises single detecting amplifier, the detecting amplifier so far and the line CL1 to CL4 of all main storage units 221 all is coupled, thereby the same time can only read the Ovonics unified memory of independent delegation.
In addition, must note, in the embodiment of Fig. 2 and 3, only produce single reference signal with reference to memory block 230 or 330.Yet, can produce more than one reference signal with reference to memory block 230 or 330.These a plurality of reference signals can convert another reference signal to by a change-over circuit (for linear transformation or non-linear electrical addition, multiply each other, be divided by, conversion such as mixing) and be coupled to comparator circuit 240, or can couple directly to comparator circuit 240.
In addition, must note, in the embodiment of Fig. 2 and 3, main storage unit 221 or reference memory unit 231,331
1And 331
2For only having single recording layer respectively.Yet, in all the other embodiment, main storage unit 221 or reference memory unit 231,331
1And 331
2For having one or more recording layers respectively, couple mutually with parallel connection or series system each other, and be programmable to the reference resistance of an equivalence.
The structure that below will describe the reference memory unit 231 of Fig. 2 is different from the implementation of the structure of main memory unit 221.The implementation of Fig. 3 can be analogized easily and learns, is omitted at this.
Fig. 4 A is first embodiment of demonstration main storage unit 221 with the structural drawing of reference memory unit 231.As shown in the figure, main storage unit 221 comprises a top electrode 41
1, a recording layer 42
1, a heating electrode embolism 43
1, and a bottom electrode 44
1Similarly, reference memory unit 231 comprises a top electrode 41
2, a recording layer 42
2, a heating electrode embolism 43
2, and a bottom electrode 44
2As shown in the figure, recording layer 42
1And 42
2Sectional area difference (sectional area of indication is the sectional area of overlooking of vertical paper herein), and material can be identical or different.Fig. 4 B publishes thesis the reset current of the storage unit that discloses with the variation relation figure of recording layer sectional area for showing Samsung company in IEDM 2003, and wherein reset current is that to make recording layer be the operating current of amorphous structure by the crystalline state Structure Conversion.Scheme as can be known thus, the recording layer with different cross-sectional has different big or small reset currents.Hence one can see that, even recording layer 42
1And 42
2Be identical materials, under the identical write current of circulation, its active region can have different crystal phase structures and have different resistance values, and the main storage unit 221 and the working curve of reference memory unit 231 are differed from one another.
Fig. 5 A is second embodiment of demonstration main storage unit 221 with the structural drawing of reference memory unit 231.The difference of this figure and Fig. 4 A only is recording layer 52
1And 52
2With its heating electrode embolism 53
1And 53
2Between the contact area difference.Fig. 5 B fastens the variation relation figure of plug contact area for showing Samsung company in the publish thesis reset current of the storage unit that discloses of IEDM 2003 with heating electrode.Figure has the different heating electrode and fastens the reset current that the recording layer of plug contact area has different sizes as can be known thus.Hence one can see that, even recording layer 52
1And 52
2Be identical materials, under the identical write current of circulation, its active region can have different crystal phase structures and have different resistance values, and the main storage unit 221 and the working curve of reference memory unit 231 are differed from one another.
Though the structure of below having described the reference memory unit 231 of Fig. 2 is different from the implementation of the structure of main memory unit 221, right the present invention is not restricted to above embodiment.For example, in all the other embodiment, when reference memory unit 231 or main memory unit 221 have a plurality of recording layer, the number of recording layer each other or serial connection mode difference.
Reference memory unit of the present invention can be realized by the adjustment of component structure the purpose that reference signal can be modulated making reference signal more stable, thereby comparator circuit possesses optimized detectability.In addition, reference memory unit of the present invention does not need extra manufacture craft to realize.
Though the present invention with embodiment openly as above, so it is not in order to limit the present invention.Those of ordinary skill under any in the technical field under the situation that does not break away from the spirit and scope of the present invention, can carry out various changes and modification.Therefore, protection scope of the present invention is as the criterion with the scope of the claim that proposed.
Claims (10)
1. Ovonics unified memory comprises:
More than one main memory unit produces at least one detection signal, and wherein each this main memory unit has at least one record layer, and the recording layer of this main memory unit is programmed at least one first resistance and one second resistance;
More than one reference memory unit produces at least one reference signal, and wherein each this reference memory unit has at least one recording layer, and the recording layer of this reference memory unit is able to programme to change its resistance value; And
One comparator circuit is coupled to these a plurality of main memory cell arrays and this a plurality of reference memory cell array, in order to relatively this at least one detection signal and this at least one reference signal, and produces the output signal of at least one correspondence in comparative result,
Wherein the electrical working curve of at least one recording layer is the electrical working curve that is different from the central at least one recording layer of these a plurality of main memory units in the middle of these a plurality of reference memory units.
2. Ovonics unified memory as claimed in claim 1, wherein each this detection signal is a detection voltage, and each this reference signal is a reference voltage.
3. Ovonics unified memory as claimed in claim 2, the difference between the electrical working curve of the electrical working curve of at least one recording layer and the central at least one recording layer of this a plurality of main memory units in the middle of these a plurality of reference memory units wherein, with so that when arbitrary recording layer in the middle of these a plurality of main memory units was programmed at least this first and second resistance, this difference that detects voltage and this reference voltage was all greater than a predetermined voltage difference.
4. Ovonics unified memory as claimed in claim 1, the difference between the electrical working curve of the electrical working curve of at least one recording layer and the central at least one recording layer of this a plurality of main memory units in the middle of these a plurality of reference memory units wherein, with so that this reference voltage equals the mean value of first voltage and second voltage, wherein this first voltage and second voltage are respectively the detection voltage when arbitrary recording layer is programmed for first and second resistance in the middle of these a plurality of main memory units.
5. Ovonics unified memory as claimed in claim 1 wherein at least onely in the middle of this reference memory unit is programmed at least one the 3rd resistance, and wherein the 3rd resistance is different from this first and second resistance.
6. Ovonics unified memory as claimed in claim 1, wherein these a plurality of reference memory units comprise a plurality of reference memory unit groups, each reference memory unit group comprises one first reference memory unit and one second reference memory unit, be programmed for one the 3rd resistance and one the 4th resistance respectively, wherein in the middle of the 3rd and the 4th resistance relative high person be different from the relative high person of this first resistance and second resistance with and/or the 3rd and the 4th resistance in the middle of relative low person be different from this first resistance and the relative low person of second resistance.
7. Ovonics unified memory as claimed in claim 6, wherein each group reference memory unit group comprises that this first reference memory unit is parallel to this second reference memory unit.
8. Ovonics unified memory as claimed in claim 1, wherein the size of the central at least one recording layer of these a plurality of reference memory units is different from the size of the central at least one recording layer of these a plurality of main memory units.
9. Ovonics unified memory as claimed in claim 8, wherein the sectional area of the central at least one recording layer of these a plurality of reference memory units is different from the sectional area of the central at least one recording layer of these a plurality of main memory units.
10. Ovonics unified memory as claimed in claim 1, wherein each this main memory unit comprises that also a heating electrode embolism is coupled to the recording layer of this main memory unit, each this reference memory unit comprises that also a heating electrode embolism is coupled to the recording layer of this reference memory unit, and wherein the contact area of central at least one recording layer of these a plurality of reference memory units and heating electrode is different from the contact area of central at least one recording layer of these a plurality of main memory units and heating electrode.
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| CNA2007101496502A CN101388246A (en) | 2007-09-10 | 2007-09-10 | Ovonics unified memory |
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|---|---|---|---|
| CNA2007101496502A CN101388246A (en) | 2007-09-10 | 2007-09-10 | Ovonics unified memory |
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| CN103680616A (en) * | 2012-08-29 | 2014-03-26 | 爱思开海力士有限公司 | Variable resistance memory device and operating method thereof |
| WO2016155410A1 (en) * | 2015-03-30 | 2016-10-06 | 山东华芯半导体有限公司 | Rram subarray structure |
| CN107039062A (en) * | 2015-10-30 | 2017-08-11 | 台湾积体电路制造股份有限公司 | Memory device and its operating method |
| US10522221B2 (en) | 2014-09-30 | 2019-12-31 | Xi'an Uniic Semiconductors Co., Ltd. | Storage array programming method and device for resistive random access memory |
| CN112349321A (en) * | 2019-08-06 | 2021-02-09 | 上海磁宇信息科技有限公司 | Magnetic random access memory chip architecture using common reference voltage |
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2007
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| CN103680616B (en) * | 2012-08-29 | 2018-11-02 | 爱思开海力士有限公司 | Variable resistance memory device and its operating method |
| CN103680616A (en) * | 2012-08-29 | 2014-03-26 | 爱思开海力士有限公司 | Variable resistance memory device and operating method thereof |
| US10522221B2 (en) | 2014-09-30 | 2019-12-31 | Xi'an Uniic Semiconductors Co., Ltd. | Storage array programming method and device for resistive random access memory |
| US10418100B2 (en) | 2015-03-30 | 2019-09-17 | Xi'an Uniic Semiconductors Co., Ltd. | RRAM subarray structure proving an adaptive read reference current |
| WO2016155410A1 (en) * | 2015-03-30 | 2016-10-06 | 山东华芯半导体有限公司 | Rram subarray structure |
| US10515680B2 (en) | 2015-10-30 | 2019-12-24 | Taiwan Semiconductor Manufacturing Co., Ltd. | Memory device and reference circuit thereof |
| US10157654B2 (en) | 2015-10-30 | 2018-12-18 | Taiwan Semiconductor Manufacturing Co., Ltd. | Memory device and reference circuit thereof |
| CN107039062A (en) * | 2015-10-30 | 2017-08-11 | 台湾积体电路制造股份有限公司 | Memory device and its operating method |
| CN107039062B (en) * | 2015-10-30 | 2020-10-30 | 台湾积体电路制造股份有限公司 | Memory device and method of operating the same |
| US11211106B2 (en) | 2015-10-30 | 2021-12-28 | Taiwan Semiconductor Manufacturing Co., Ltd. | Memory device and reference circuit thereof |
| US11848040B2 (en) | 2015-10-30 | 2023-12-19 | Taiwan Semiconductor Manufacturing Co., Ltd. | Memory device and reference circuit thereof |
| CN112349321A (en) * | 2019-08-06 | 2021-02-09 | 上海磁宇信息科技有限公司 | Magnetic random access memory chip architecture using common reference voltage |
| CN112349321B (en) * | 2019-08-06 | 2024-03-12 | 上海磁宇信息科技有限公司 | Magnetic random access memory chip architecture using common reference voltage |
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