CN112289352B - MRAM system with ECC function and operation method thereof - Google Patents
MRAM system with ECC function and operation method thereof Download PDFInfo
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- CN112289352B CN112289352B CN201910678832.1A CN201910678832A CN112289352B CN 112289352 B CN112289352 B CN 112289352B CN 201910678832 A CN201910678832 A CN 201910678832A CN 112289352 B CN112289352 B CN 112289352B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1675—Writing or programming circuits or methods
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1677—Verifying circuits or methods
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/38—Response verification devices
- G11C29/42—Response verification devices using error correcting codes [ECC] or parity check
Abstract
The invention discloses an MRAM system with ECC function, comprising an MRAM, an ECC circuit and a register group, wherein the register group is arranged between the MRAM and the ECC circuit and is electrically connected with the MRAM and the ECC circuit, and the register group is used for reading data from the MRAM and storing the read data into the register group; an ECC circuit for reading data from the MRAM simultaneously with the register set; when the MRAM writes back data, it is used to compare the written back data with the data stored in the register set, and check and correct the data error. The invention can detect the state of the written bit while performing the writing operation, has high reliability of the MRAM, reduces the writing power consumption and has no influence on the chip speed and the design complexity.
Description
Technical Field
The present invention relates to the field of MRAM technologies, and in particular, to an MRAM system with ECC function and an operation method thereof.
Background
MRAM is a new memory and storage technology, which can be read and written randomly as fast as SRAM/DRAM, and also can permanently retain data after power failure as Flash. Unlike DRAM and Flash, which are not compatible with standard CMOS semiconductor processes, MRAM can be integrated with logic circuitry into one chip. MRAM of magnetic tunnel junctions is considered to be a future solid state nonvolatile memory that has the characteristics of high speed reading and writing, large capacity, and low power consumption.
The principle of MRAM is based on the structure of a Magnetic Tunnel Junction (MTJ). It is composed of two layers of ferromagnetic material sandwiching a very thin layer of non-ferromagnetic insulating material, as shown in fig. 1 and 2. The lower layer of ferromagnetic material is a reference layer 13 having a fixed magnetization direction, the upper layer of ferromagnetic material is a memory layer 11 having a variable magnetization direction, and the magnetization direction of the memory layer 11 may be parallel or antiparallel to the reference layer 13. Due to quantum-physical effects, current may pass through the intermediate tunnel barrier layer 12, but the resistance of the magnetic tunnel junction is related to the magnetization direction of the variable magnetization layer. The resistance is low when the magnetization directions of the memory layer 11 and the reference layer 13 are parallel, as shown in fig. 1; the resistance is high in antiparallel, as in fig. 2.
The process of reading MRAM is to measure the resistance of the magnetic tunnel junction. Writing MRAM is also simpler using newer STT-MRAM technology: a stronger current than reading is used to perform a write operation through the magnetic tunnel junction. A bottom-up current places the variable magnetization layer in an antiparallel direction to the fixed layer. The top-down current places it in a parallel direction.
The read-out circuitry of MRAM is required to detect the resistance of the MRAM memory cells. The resistance of the magnetic tunnel junction may drift due to manufacturing process, read/write times, temperature, etc., resulting in data errors (the data bits read out are opposite to the data bits last written before). To solve this problem, error detection and correction circuits (ECC, error Checking and Correcting) may be added to encode data of one word and to add some check bit bits to detect and correct data errors.
In the prior art, although the read-write power consumption of the MRAM technology of various manufacturers approaching mass production is much lower than that of a flash memory, the write power consumption is still relatively high, and the write current is relatively high, so that the MRAM technology is not ideal if the DRAM or the SRAM is replaced. In particular, the current writing technology is very wasteful of energy: if a 1 is required to be written in a certain bit, the probability of half the bit is already a 1, and no more energy is required. However, the write circuit cannot know the state before the bit, so whether the previous state is a 1 or a 0, a common practice is to do a write operation. In a statistical sense, half of the energy is wasted as such.
In order to reduce the waste of writing energy, the industry has started to study writing state detection circuits capable of detecting the state of a written bit while performing a writing operation, and terminating the writing operation immediately upon detecting that the state of the bit has reached a target value. Such a write state detection circuit can greatly reduce write power consumption.
US patent US20180061466 is currently the most advanced concept in the industry. It proposes: a write state detection circuit is added to the MRAM to terminate the write operation in advance when it is detected that the bit being written has reached the target state. A reference cell is required with a reference resistance. The write detection circuit determines its current state by comparing the resistance of the written cell with a reference resistance. The specific implementation method is to apply the same voltage to the reference unit as the written unit and compare the same potential of one point on the writing loop. The different resistances of the written cells necessarily result in different circuit voltage division, resulting in a change in the point location on the detected point. The above patent is too complex to implement and is vulnerable.
Therefore, it is necessary to design an MRAM system having an ECC function and an operation method thereof that can support MRAM, detect a state of a written bit while performing a write operation, have high MRAM reliability, reduce write power consumption, and have no influence on chip speed and design complexity.
Disclosure of Invention
In view of the drawbacks of the prior art, an object of the present invention is to provide an MRAM system with ECC functionality, which is capable of supporting MRAM, detecting the state of written bits while performing write operations, has high MRAM reliability, reduces write power consumption, and has no impact on chip speed, design complexity.
The invention discloses an MRAM system with ECC function, comprising an MRAM, an ECC circuit and a register set, wherein the register set is arranged between the MRAM and the ECC circuit and is electrically connected with the MRAM and the ECC circuit,
the register set is used for reading data from the MRAM and storing the read data into the register set;
the ECC circuit is used for reading data from the MRAM simultaneously with the register set; and when the MRAM writes back data, the MRAM is used for comparing the written back data with the data stored in the register group, and checking and correcting data errors.
Further, the ECC circuit realizes the checking and correction of data errors by encoding data of one word and adding check bit.
Further, when the write-back data is the same as the data stored in the register set, the data does not need to be written back into the MRAM; when the write back data is different from the data stored in the register set, the data needs to be written back into the MRAM.
Correspondingly, the invention also discloses an operation method of the MRAM system with ECC function, which comprises the following steps:
step 1: a register set for reading data from the MRAM, for storing the read data in the register set;
step 2: and the ECC circuit is used for reading data from the MRAM simultaneously with the register set, and comparing the written-back data with the data stored in the register set when the MRAM writes back the data, so as to check and correct data errors.
Further, the ECC circuit in step 2 performs checking and correcting of data errors by encoding data of one word and adding check bit.
Further, in the step 2, when the write-back data is the same as the data stored in the register set, the write-back data is not required to be written back into the MRAM;
in step 2, when the write-back data is different from the data stored in the register set, the data needs to be written back into the MRAM.
The implementation of the invention has the following beneficial effects:
(1) The operation method of the MRAM system with the ECC function can support the magnetic random access memory, check the state of the written bit while performing the writing operation, and the magnetic random access memory has high reliability and reduces the writing power consumption;
(2) The operation method of the MRAM system with ECC function improves the reliability of bit, and the writing state detection method has no influence on the speed of a chip and the complexity of design;
(3) The operation method of the MRAM system with ECC function of the invention compares the data coded by the error checking and correcting circuit with the data in the register group when writing the data, and the data are different in bit, and the method is simple and can effectively reduce the frequency of writing the magnetic random access memory.
Drawings
In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram showing a structure in which magnetization directions of a memory layer and a reference layer of a magnetic random access memory are parallel;
FIG. 2 is a schematic diagram showing the anti-parallel structure of the magnetization directions of the memory layer and the reference layer of the MRAM;
FIG. 3 is a schematic diagram of an MRAM system with ECC function according to the present invention.
Wherein, corresponding reference numerals in the figures are as follows: 11-memory layer, 12-tunnel barrier layer, 13-reference layer.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. It will be apparent that the described embodiments are only some, but not all, embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Example 1
The embodiment of the invention provides an MRAM system with ECC function, which comprises an MRAM, an ECC circuit and a register set, wherein the register set is arranged between the MRAM and the ECC circuit and is electrically connected with the MRAM and the ECC circuit,
the register set is used for reading data from the MRAM and storing the read data into the register set;
the ECC circuit is used for reading data from the MRAM simultaneously with the register set; and when the MRAM writes back data, the MRAM is used for comparing the written back data with the data stored in the register group, and checking and correcting data errors.
The ECC circuit realizes the checking and correction of data errors by encoding data of one word and adding check bit.
When the write-back data is the same as the data stored in the register set, the data does not need to be written back into the MRAM; when the write back data is different from the data stored in the register set, the data needs to be written back into the MRAM.
The register set may be provided with control parameters and status parameters.
Example 2
On the basis of the embodiment 1, the present invention also provides an operation method of the MRAM system with ECC function, which includes the following steps:
step 1: a register set for reading data from the MRAM, for storing the read data in the register set;
step 2: and the ECC circuit is used for reading data from the MRAM simultaneously with the register set, and comparing the written-back data with the data stored in the register set when the MRAM writes back the data, so as to check and correct data errors.
The ECC circuit in the step 2 realizes the checking and correction of data errors by encoding the data of one word and adding check bit.
In the step 2, when the write-back data is the same as the data stored in the register set, the write-back data is not needed to be written back into the MRAM;
in step 2, when the write-back data is different from the data stored in the register set, the data needs to be written back into the MRAM.
The implementation of the invention has the following beneficial effects: the operation method of the MRAM system with the ECC function can support the magnetic random access memory, check the state of the written bit while performing the writing operation, and the magnetic random access memory has high reliability and reduces the writing power consumption; the reliability of the bit is improved, and the writing state detection method has no influence on the speed of the chip and the complexity of the design; when writing data, the data coded by the error checking and correcting circuit is compared with the data in the register group, and the different bits are truly written back into the magnetic random access memory.
The foregoing description of the preferred embodiments of the invention is not intended to limit the invention to the precise form disclosed, and any such modifications, equivalents, and alternatives falling within the spirit and scope of the invention are intended to be included within the scope of the invention.
Claims (2)
1. An MRAM system having an ECC function, comprising an MRAM, an ECC circuit, and a register set disposed between and electrically connected to the MRAM and the ECC circuit,
the register set is used for reading data from the MRAM and storing the read data into the register set;
the ECC circuit is used for reading data from the MRAM simultaneously with the register set; when the MRAM writes back data, the ECC circuit is used for comparing the written back data with the data stored in the register set, and the ECC circuit realizes the checking and correction of data errors by encoding the data of one word and adding check bit;
when the write-back data is the same as the data stored in the register set, the data does not need to be written back into the MRAM; when the write back data is different from the data stored in the register set, the data needs to be written back into the MRAM.
2. A method of operating an MRAM system having ECC functionality, comprising the steps of:
step 1: a register set for reading data from the MRAM, for storing the read data in the register set;
step 2: the ECC circuit is used for reading data from the MRAM simultaneously with the register set, and comparing the written-back data with the data stored in the register set when the MRAM writes-back data, and the ECC circuit realizes the checking and correction of data errors by encoding the data of one word and adding check bit; when the write-back data is the same as the data stored in the register set, the data does not need to be written back into the MRAM; when the write back data is different from the data stored in the register set, the data needs to be written back into the MRAM.
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| CN104503707A (en) * | 2014-12-24 | 2015-04-08 | 华为技术有限公司 | Method and device for reading data |
| CN107195329A (en) * | 2017-05-17 | 2017-09-22 | 西安紫光国芯半导体有限公司 | The wrong method and DRAM of storage array in DRAM are corrected in read operation |
| US10115444B1 (en) * | 2017-08-09 | 2018-10-30 | Qualcomm Incorporated | Data bit inversion tracking in cache memory to reduce data bits written for write operations |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JP2004288311A (en) * | 2003-03-24 | 2004-10-14 | Toshiba Corp | Semiconductor storage device and control method therefor |
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| CN1819054A (en) * | 2005-02-08 | 2006-08-16 | 尔必达存储器股份有限公司 | Semiconductor memory device and writing method thereof |
| CN102063340A (en) * | 2011-01-19 | 2011-05-18 | 西安交通大学 | Method for improving fault-tolerant capability of high-speed cache of magnetoresistance RAM (Random Access Memory) |
| CN103268292A (en) * | 2013-06-13 | 2013-08-28 | 江苏大学 | Method for prolonging life of non-volatile external memory and high-speed long-life external memory system |
| CN104503707A (en) * | 2014-12-24 | 2015-04-08 | 华为技术有限公司 | Method and device for reading data |
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| US10115444B1 (en) * | 2017-08-09 | 2018-10-30 | Qualcomm Incorporated | Data bit inversion tracking in cache memory to reduce data bits written for write operations |
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