CN112289352A

CN112289352A - MRAM system with ECC function and operation method thereof

Info

Publication number: CN112289352A
Application number: CN201910678832.1A
Authority: CN
Inventors: 戴瑾; 夏文斌
Original assignee: Shanghai Ciyu Information Technologies Co Ltd
Current assignee: Shanghai Ciyu Information Technologies Co Ltd
Priority date: 2019-07-25
Filing date: 2019-07-25
Publication date: 2021-01-29
Anticipated expiration: 2039-07-25
Also published as: CN112289352B

Abstract

The invention discloses an MRAM system with an ECC function, which comprises an MRAM, an ECC circuit and a register group, wherein the register group is arranged between the MRAM and the ECC circuit and is electrically connected with the MRAM and the ECC circuit; an ECC circuit for reading out data from the MRAM at the same time as the register group; when MRAM writes back data, it compares the data with data stored in register set to check and correct data error. The invention can detect the state of the written bit while writing, has high MRAM reliability, reduces writing power consumption, and has no influence on chip speed and design complexity.

Description

MRAM system with ECC function and operation method thereof

Technical Field

The present invention relates to the field of MRAM technology, and in particular, to an MRAM system having an ECC function and an operating method thereof.

Background

MRAM is a new memory and storage technology, can be read and written randomly as SRAM/DRAM, and can permanently retain data after power failure as Flash memory. Unlike DRAMs and Flash, which are not compatible with standard CMOS semiconductor processes, MRAM can be integrated with logic circuitry in one chip. MRAM with magnetic tunnel junctions is considered as a future solid-state nonvolatile memory, which has features of high speed read and write, large capacity, and low power consumption.

The principle of MRAM is based on the structure of a Magnetic Tunnel Junction (MTJ). It consists of two layers of ferromagnetic material sandwiching a very thin layer of non-ferromagnetic insulating material, as shown in fig. 1 and 2. The lower layer of ferromagnetic material is a reference layer 13 with a fixed magnetization direction and the upper layer of ferromagnetic material is a memory layer 11 with a variable magnetization direction, the magnetization direction of the memory layer 11 can be parallel or anti-parallel to the reference layer 13. Due to quantum physical effects, current can pass through the middle tunnel barrier layer 12, but the resistance of the magnetic tunnel junction is related to the magnetization direction of the variable magnetization layer. The resistance is low when the magnetization directions of the memory layer 11 and the reference layer 13 are parallel, as shown in FIG. 1; the resistance is high in anti-parallel, as in fig. 2.

The process of reading an MRAM is to measure the resistance of the magnetic tunnel junction. Using the newer STT-MRAM technology, writing to MRAM is also simpler: a stronger current than reading is used for writing across the magnetic tunnel junction. A bottom-up current places the variable magnetization layer in an anti-parallel direction with the fixed layer. The current from top to bottom sets it in a parallel direction.

The read-out circuit of an MRAM needs to detect the resistance of the MRAM memory cell. Data errors (reading data bits as opposed to the last previously written data bits) may result due to drift in the resistance of the magnetic tunnel junction due to manufacturing processes, read and write times, temperature, etc. To solve this problem, an Error Checking and Correcting circuit (ECC) may be added to encode data of one word and add some check bits to detect and correct data errors.

At present, the MRAM technology of each factory close to mass production has the disadvantages that although the read-write power consumption is much lower than that of a flash memory, the write-in power consumption is still larger, the write current is higher, and the MRAM technology is not ideal if replacing a DRAM or an SRAM. In particular, with current writing techniques, the waste of energy is very large: if a bit of 1 is required, the probability that the bit is half of a 1 is already present, and no more energy is required. However, the write circuit cannot know the previous state of the bit, so whether the previous state is a 1 or a 0, it is common practice to do a write operation once. In a statistical sense, half of the energy is thus wasted.

In order to reduce the waste of writing energy, the industry has started studying a writing state detection circuit capable of detecting the state of a bit being written while a writing operation is being performed, and terminating the writing operation immediately upon detecting that the state of the bit has reached a target value. Such a write state detection circuit can significantly reduce write power consumption.

US patent US20180061466 is currently the most advanced concept in the industry. It proposes: a write state detection circuit is added to the MRAM to terminate the write operation early when it is detected that the written bit has reached the target state. A reference cell is required having a reference resistance. The write detection circuit compares the resistance of the cell being written to with the reference resistance to determine its current state. The specific implementation method is to apply the same voltage of the written unit to the reference unit and compare the potential of the same point on the writing circuit. The different resistances of the written-in units inevitably lead to different circuit voltage division, which causes the change of the point position on the detected point. The above patent implementation is too complex and has holes.

Therefore, it is necessary to design an MRAM system having an ECC function and an operating method thereof capable of supporting the MRAM, detecting a state of a written bit while performing a write operation, having high reliability of the MRAM, reducing write power consumption, and having no influence on a chip speed, design complexity.

Disclosure of Invention

In view of the drawbacks of the prior art, it is an object of the present invention to provide an MRAM system having an ECC function, which can support MRAM, detect the state of a written bit while performing a write operation, have high reliability of MRAM, reduce write power consumption, and have no influence on chip speed and design complexity.

The invention discloses an MRAM system with ECC function, which comprises an MRAM, an ECC circuit and a register set, wherein the register set is arranged between the MRAM and the ECC circuit and is electrically connected with the MRAM and the ECC circuit,

the register group is used for reading data from the MRAM and storing the read data into the register group;

the ECC circuit to read out data from the MRAM at the same time as the register group; when the MRAM writes back data, the MRAM is used for comparing the written back data with the data stored in the register set and checking and correcting data errors.

Furthermore, the ECC circuit realizes the check and correction of data errors by encoding data of one word and adding check bit bits.

Further, when the write-back data is the same as the data stored in the register set, the data does not need to be written back to the MRAM; when the write-back data is different from the data stored in the register set, the data needs to be written back to the MRAM.

Correspondingly, the invention also discloses an operation method of the MRAM system with the ECC function, which comprises the following steps:

step 1: a register set which reads out data from the MRAM and stores the read-out data in the register set;

step 2: and the ECC circuit is used for reading data from the MRAM at the same time with the register group, comparing the write-back data with the data stored in the register group when the MRAM writes back the data, and checking and correcting data errors.

Further, the ECC circuit in step 2 implements checking and correcting of data errors by encoding data of one word and adding check bit bits.

Further, in step 2, when the write-back data is the same as the data stored in the register set, the data does not need to be written back to the MRAM;

in step 2, when the write-back data is different from the data stored in the register set, the data needs to be written back to the MRAM.

The implementation of the invention has the following beneficial effects:

(1) the operation method of the MRAM system with the ECC function can support the magnetic random access memory, check the state of the written bit while performing the writing operation, and has the advantages of high reliability and reduced writing power consumption;

(2) the operation method of the MRAM system with the ECC function improves the reliability of bit, and the writing state detection method has no influence on the speed of a chip and the complexity of design;

(3) the operation method of MRAM system with ECC function of the invention, while writing data, compare the data after error check and correction circuit coding with data in the register group, different bit, write back the magnetic random access memory really, the method of the invention is simple, can reduce the frequency of writing the magnetic random access memory effectively.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

FIG. 1 is a schematic diagram of a MRAM memory device with parallel magnetization directions of a memory layer and a reference layer;

FIG. 2 is a schematic diagram of a structure in which magnetization directions of a memory layer and a reference layer of a magnetic random access memory are antiparallel;

FIG. 3 is a schematic diagram of an MRAM system with ECC function according to the present invention.

Wherein corresponding reference numerals in the figures are: 11-memory layer, 12-tunnel barrier layer, 13-reference layer.

Detailed Description

The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention.

Example 1

The embodiment of the invention provides an MRAM system with an ECC function, which comprises an MRAM, an ECC circuit and a register group, wherein the register group is arranged between the MRAM and the ECC circuit and is electrically connected with the MRAM and the ECC circuit,

The ECC circuit realizes the check and correction of data errors by encoding data of one word and adding check bit bits.

When the write-back data is the same as the data stored in the register set, the data does not need to be written back to the MRAM; when the write-back data is different from the data stored in the register set, the data needs to be written back to the MRAM.

The register set may be provided with control parameters and status parameters.

Example 2

On the basis of the foregoing embodiment 1, the present invention further provides an operating method of an MRAM system having an ECC function, including the steps of:

The ECC circuit in step 2 implements checking and correcting of data errors by encoding data of one word and adding check bit bits.

In the step 2, when the write-back data is the same as the data stored in the register set, the data does not need to be written back to the MRAM;

The implementation of the invention has the following beneficial effects: the operation method of the MRAM system with the ECC function can support the magnetic random access memory, check the state of the written bit while performing the writing operation, and has the advantages of high reliability and reduced writing power consumption; the reliability of bit is improved, and the writing state detection method has no influence on the speed of a chip and the complexity of design; when writing data, the data coded by the error checking and correcting circuit is compared with the data in the register group, different bits are really written back to the magnetic random access memory, the method is simple, and the frequency of writing the magnetic random access memory can be effectively reduced.

The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.

Claims

1. An MRAM system having an ECC function, comprising an MRAM, an ECC circuit, and a register set disposed between and electrically connected to the MRAM and the ECC circuit,

2. The MRAM system with ECC function of claim 1, wherein the ECC circuit performs checking and correcting data errors by encoding a word of data and adding check bit bits.

3. The MRAM system with ECC function of claim 2, wherein when the write-back data is the same as the data stored in the register set, the data does not need to be written back to the MRAM; when the write-back data is different from the data stored in the register set, the data needs to be written back to the MRAM.

4. A method of operating an MRAM system having an ECC function, comprising the steps of:

5. The method of claim 4, wherein the ECC circuit in step 2 checks and corrects data errors by encoding a word of data and adding check bit bits.

6. The method of operating an MRAM system with ECC functionality of claim 5,