CN107957541B - A kind of power semiconductor modular internal parallel cDNA microarray method and system - Google Patents
A kind of power semiconductor modular internal parallel cDNA microarray method and system Download PDFInfo
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- CN107957541B CN107957541B CN201711166334.6A CN201711166334A CN107957541B CN 107957541 B CN107957541 B CN 107957541B CN 201711166334 A CN201711166334 A CN 201711166334A CN 107957541 B CN107957541 B CN 107957541B
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- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
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- G—PHYSICS
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- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
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Abstract
The invention discloses a kind of power semiconductor modular internal parallel cDNA microarray method and system.The described method includes: obtaining the transfer characteristic curve of multiple chips；By each transfer characteristic curve discretization, multiple discrete points of transfer characteristic curve are obtained, constitute chip discrete point set；Obtain the chip discrete point set of any two chip in multiple chips；Several relative differences values of two chips are calculated, relative differences value is drain current relative differences value or gate-source voltage relative differences value；The average relative differences value of two chips is calculated, average relative differences value is the average value of several relative differences values of two chips；All average relative differences values, determine minimum average B configuration relative differences value in more multiple chips；Determine corresponding two chips of minimum average B configuration relative differences value as object filtering chip.The present invention can obtain two parallel chips of the dispersibility of threshold voltage and dispersibility very littles of mutual conductance coefficient, so that the transient state of parallel chip flows better effect.
Description
Technical field
The present invention relates to power semiconductor parallel technology fields, more particularly to a kind of power semiconductor modular internal parallel
CDNA microarray method and system.
Background technique
In recent years, with the quickening of silicon carbide power semiconductor devices commercialization process, good market prospects are pushed
The continuous development of technology.Compared to the silicon preparation process that there is decades technology to precipitate, silicon carbide power device is in electric current
Grade, reliability and cost etc. still have many shortcomings.The high-power applications demand and existing carbonization increasingly gradually grown
The physical limit of silicon device current density makes equipment research staff have to using device parallel way as a kind of substitution
Solution.However, even if in the case where circuit layout is full symmetric, due to chip parameter unavoidable in preparation process
Otherness can also have current distribution is uneven weighing apparatus between parallel units, this brings greatly to the application in parallel of carbonization silicon chip
Challenge.
In chip fabrication process, due to manufacture craft, environment and personnel or the difference of equipment operation, not same core will lead to
Piece parameter is inconsistent.Similar to the concept of electronic component tolerance, chip parameter dispersibility refers to the characterisitic parameter of different components simultaneously
Characteristic that is inconsistent, but being distributed in a certain range.For mature silicon-based devices, the development of many years, existing work have passed through
Skill technology or it is difficult to ensure that device parameters are completely the same, and for developing for still not mature enough silicon carbide device technology,
The dispersibility of device parameters will be bigger.Therefore, before parallel connection encapsulation, the screening of chip parameter is particularly important.
Grade division method is generallyd use to the screening of chip at present.For example, the Ch.Keller of AEG company, Germany in 1993
Point out that chip manufacturer would generally provide different grades of insulated gate bipolar transistor (Insulated Gate Bipolar
Transistor, IGBT) chip, the conduction voltage drop degree of scatter of these chips is generally no more than 0.5V, to keep on-state electric
The unbalanced degree of stream can control between 10%-20%；The D.Medaule of nineteen ninety-five Mitsubishi Corporation of Japan is proposed all standards
The conduction voltage drop for being ready for use on igbt chip in parallel is screened by grade classification, and the conduction voltage drop interval range of each grade is
0.25V or 0.3V, and when pointing out to carry out in parallel using the chip under same grade, it is ensured that the unbalanced degree of chip parallel-current
Within 15%；The Takeharu Koga of FUJI ELECTRIC company in 1998 is in the compression joint type IGBT module to 2.5kV/1.8kA
It points out in the research of robustness and reliability, other than being screened to the conduction voltage drop of igbt chip, also needs to chip
Dynamic parameter such as turn off storage time and fall time is screened, and give conduction voltage drop difference be no more than ±
0.1V, storage time difference are no more than the screening index such as ± 5%；With its company in FUJI ELECTRIC technical manuals in 2014
For the MOSFET of Super FAP series, the screening criteria of threshold voltage is formulated, the threshold voltage of all batch products has been pressed
Classify according to different brackets, wherein carrying out grade classification, power device system by interval of 0.35V for logic family device
Column are with 0.4V for a divided rank.
The method of existing cDNA microarray, is some parameter of acquisition chip, such as conduction voltage drop or threshold voltage,
Then grade classification is carried out according to the parameter of acquisition, this method is typically only capable to the core in parallel for carrying out rough screening, filtering out
The transient state of piece flow it is ineffective, although and in theory, can suitably increase the quantity of screening parameter improve sieve
The transient state for the parallel chip selected flows effect, but increases in practice as the number of parameters of screening, according to different parameters institute
The device label that demarcation interval filters out may be different, the intersection in these sections will very little, be difficult to combine multiple
Parameter.Therefore, existing cDNA microarray method can only realize the rough screening of parallel chip, the transient state of the parallel chip filtered out
It flows ineffective.
Summary of the invention
Based on this, it is necessary to provide a kind of power semiconductor modular internal parallel cDNA microarray method and system, Lai Shixian
The accurate screening of parallel chip, the transient state for improving the parallel chip filtered out flow effect.
To achieve the above object, the present invention provides following schemes:
A kind of power semiconductor modular internal parallel cDNA microarray method, comprising:
The transfer characteristic curve of multiple chips is obtained, the transfer characteristic curve is each chip in opening process
Gate-source voltage and drain current variation relation curve；
By each transfer characteristic curve discretization, multiple discrete points of the transfer characteristic curve are obtained, constitute core
Piece discrete point set；
Obtain the chip discrete point set of any two chip in multiple chips；
Calculate several relative differences values of two chips, the relative differences value be drain current relative differences value or
Gate-source voltage relative differences value；The drain current relative differences value is that the two chip discrete points concentrate on the same grid source
The relative differences value of the drain current of discrete point under pole tension；The gate-source voltage relative differences value be two chips from
Scatterplot concentrates on the relative differences value of the gate-source voltage of the discrete point under the same drain current；
The average relative differences value of two chips is calculated, the average relative differences value is several of two chips
The average value of relative differences value；
All average relative differences values, determine minimum average B configuration relative differences value in more multiple chips；
Determine corresponding two chips of the minimum average B configuration relative differences value as object filtering chip.
Optionally, the transfer characteristic curve for obtaining multiple chips, specifically includes:
The transfer characteristic measured value of each chip is obtained by power analyzer；
According to the transfer characteristic measured value of each chip, the transfer characteristic curve of multiple chips is drawn.
Optionally, described by each transfer characteristic curve discretization, obtain the transfer characteristic curve it is multiple from
Scatterplot constitutes chip discrete point set, specifically includes:
The transfer characteristic curve is handled by the way of interpolation, obtain the transfer characteristic curve it is multiple from
Scatterplot.
Optionally, the transfer characteristic measured value that each chip is obtained by power analyzer, specifically includes:
Fixed step size is obtained, the fixed step size is within a preset range；
The transfer characteristic measured value of each chip is obtained according to the fixed step size.
The present invention also provides a kind of power semiconductor modular internal parallel cDNA microarray systems, comprising:
First obtains module, and for obtaining the transfer characteristic curve of multiple chips, the transfer characteristic curve is each institute
State the curve of the variation relation of gate-source voltage and drain current of the chip in opening process；
Discrete block, for obtaining the multiple of the transfer characteristic curve for each transfer characteristic curve discretization
Discrete point constitutes chip discrete point set；
Second obtains module, for obtaining the chip discrete point set of any two chip in multiple chips；
First computing module, for calculating several relative differences values of two chips, the relative differences value is leakage
Electrode current relative differences value or gate-source voltage relative differences value；The drain current relative differences value is that two chips are discrete
Point concentrates on the relative differences value of the drain current of the discrete point under the same gate-source voltage；The gate-source voltage is with respect to phase
Difference is the relative differences value for the gate-source voltage that the two chip discrete points concentrate on the discrete point under the same drain current；
Second computing module, for calculating the average relative differences value of two chips, the average relative differences value is
The average value of several relative differences values of two chips；
Comparison module determines minimum average B configuration phase for the average relative differences values all in more multiple chips
To phase difference；
Objective chip determining module, for determining corresponding two chips of the minimum average B configuration relative differences value as target
Screening chip.
Optionally, described first module is obtained, specifically included:
Transfer characteristic measured value acquiring unit, the transfer characteristic for obtaining each chip by power analyzer measure
Value；
Transfer characteristic curve acquiring unit draws multiple cores for the transfer characteristic measured value according to each chip
The transfer characteristic curve of piece.
Optionally, the discrete block, specifically includes:
Discrete point acquiring unit, for being handled by the way of interpolation the transfer characteristic curve, described in acquisition
Multiple discrete points of transfer characteristic curve.
Optionally, the transfer characteristic measured value acquiring unit, specifically includes:
Step-length obtains subelement, and for obtaining fixed step size, the fixed step size is within a preset range；
Transfer characteristic measured value obtains subelement, and the transfer characteristic for obtaining each chip according to the fixed step size is surveyed
Magnitude.
Compared with prior art, the beneficial effects of the present invention are:
The invention proposes a kind of power semiconductor modular internal parallel cDNA microarray method and system, the method packets
It includes: obtaining the transfer characteristic curve of multiple chips；By each transfer characteristic curve discretization, the multiple of transfer characteristic curve are obtained
Discrete point constitutes chip discrete point set；Obtain the chip discrete point set of any two chip in multiple chips；Calculate two chips
Several relative differences values；Calculate the average relative differences value of two chips；All average relative differences values in more multiple chips,
Determine minimum average B configuration relative differences value；Determine corresponding two chips of minimum average B configuration relative differences value as object filtering chip.
Present invention obviates the screening techniques that grade classification is carried out according to a parameter, but by comparing the transfer characteristic of different chips
The similarity of curve is screened, and chip threshold voltage and mutual conductance coefficient two are reflected by the similarity of transfer characteristic curve
The dispersibility of key parameter, and using relative differences value as screening index, the accurate screening of chip is realized, screening is improved
The transient state of parallel chip out flows effect, wherein relative differences value is smaller using relative differences value as screening index, then two
The transfer characteristic curve similarity of a chip is higher, and then shows the dispersibility and mutual conductance coefficient of the threshold voltage of two chips
Dispersibility all very littles, wherein the dispersibility of threshold voltage is small, illustrates that two chips open the difference very little at moment, mutual conductance coefficient
Dispersibility is small, illustrates that the rate of climb of conducting electric current is almost the same；Relative differences value is smaller, then the transfer characteristic of two chips is bent
Line similarity is higher, also can show that the transient state after chip is in parallel flows better effect.
Detailed description of the invention
It in order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, below will be to institute in embodiment
Attached drawing to be used is needed to be briefly described, it should be apparent that, the accompanying drawings in the following description is only some implementations of the invention
Example, for those of ordinary skill in the art, without any creative labor, can also be according to these attached drawings
Obtain other attached drawings.
Fig. 1 is the flow chart of power semiconductor modular of embodiment of the present invention internal parallel cDNA microarray method；
Fig. 2 is the transfer characteristic curve of No. 1 chip and No. 2 chips of the embodiment of the present invention；
Fig. 3 is the structural schematic diagram of power semiconductor modular of embodiment of the present invention internal parallel cDNA microarray system.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
In order to make the foregoing objectives, features and advantages of the present invention clearer and more comprehensible, with reference to the accompanying drawing and specific real
Applying mode, the present invention is described in further detail.
Fig. 1 is the flow chart of power semiconductor modular of embodiment of the present invention internal parallel cDNA microarray method.
Referring to Fig. 1, the power semiconductor modular internal parallel cDNA microarray method of embodiment, comprising:
S1: obtaining the transfer characteristic curve of multiple chips, and the transfer characteristic curve is that each chip was being opened
The curve of the variation relation of gate-source voltage and drain current in journey.
Specifically, obtaining the transfer characteristic curve of multiple chips by power analyzer or other measuring devices, comprising: obtain
Fixed step size is taken, the fixed step size is within a preset range；The transfer characteristic for obtaining each chip according to the fixed step size is surveyed
Magnitude；According to the transfer characteristic measured value of each chip, the transfer characteristic curve of multiple chips is drawn.
S2: by each transfer characteristic curve discretization, obtaining multiple discrete points of the transfer characteristic curve, constitutes
Chip discrete point set.
Specifically, handling by the way of interpolation the transfer characteristic curve, the transfer characteristic curve is obtained
Multiple discrete points.
S3: the chip discrete point set of any two chip in multiple chips is obtained.
S4: calculating several relative differences values of two chips, and the relative differences value is drain current relative differences
Value or gate-source voltage relative differences value.
Specifically, the drain current relative differences value is that the two chip discrete points concentrate on the same gate-source voltage
Under discrete point drain current relative differences value；The gate-source voltage relative differences value is the two chip discrete point sets
In discrete point under the same drain current gate-source voltage relative differences value.
S5: calculating the average relative differences value of two chips, if the average relative differences value is two chips
The average value of dry relative differences value.
S6: all average relative differences values in more multiple chips determine minimum average B configuration relative differences value.
S7: determine corresponding two chips of the minimum average B configuration relative differences value as object filtering chip.
In practical applications, the power semiconductor modular internal parallel cDNA microarray method of above-described embodiment can be used for volume
Chip number from 1 to No. 30 is screened, and required parallel chip is obtained, specifically:
The transfer characteristic curve of 30 chips is obtained by power analyzer or other measuring device measurements, every transfer is special
Linearity curve is all made of being drawn as several transfer characteristic measured values, and transfer characteristic measured value is measured by following steps: being obtained
Fixed step size is taken, the fixed step size is within a preset range；The transfer characteristic for obtaining each chip according to the fixed step size is surveyed
Magnitude.
The transfer characteristic curve is handled by the way of interpolation, obtain the transfer characteristic curve it is multiple from
Scatterplot, its purpose is to obtain sufficient discrete point.
In the present embodiment, selection fixed step size is 1V, obtains the transfer characteristic curve of No. 1 chip and No. 2 chips, using slotting
The mode of value carries out the transfer characteristic curve of No. 1 chip and No. 2 chips discrete respectively, makes the number of the discrete point of every curve
It is n.
Fig. 2 is the transfer characteristic curve of embodiment No. 1 chip and No. 2 chips.
Referring to fig. 2, curve l1For the transfer characteristic curve of No. 1 chip, curve l2For the transfer characteristic curve of No. 2 chips, move
Characteristic abscissa indicates gate-source voltage, and ordinate indicates drain current, under identical gate-source voltage, for appointing
It anticipates a pair of discrete point k (A, B), A indicates that the discrete point on the transfer characteristic curve of No. 1 chip, B are indicated with No. 1 chip same
Discrete point on the transfer characteristic curve of No. 2 chips under a gate-source voltage, the coordinate of point A are (x, pk), the coordinate of point B is
(x,qk)。
No. 1 chip and No. 2 chips are calculated in the drain current relative differences value of discrete point k (A, B), calculation formula are as follows:
The drain current relative differences value of No. 1 chip and No. 2 all discrete points of chip is calculated, and is averaging, No. 1 core is obtained
The average relative differences value of piece and No. 2 chips, calculation formula are as follows:
The average relative differences value of No. 1 chip and No. 2 chipsScreening index value as No. 1 chip and No. 2 chips.
On the basis of the transfer curve of No. 1 chip, No. 1 chip and No. 2 chips, 1 are calculated separately using above-mentioned two formula
The average relative differences value of every group of chip of number chip and No. 1 chip of No. 3 chips ... and No. 30 chips, it is average to obtain several
Relative differences value
It is above-mentioned the whole of No. 1 chip and 2-30 chip are completed to compare, below need to only repeat the above steps and complete residue
The comparison of chip calculates separately No. 2 chips and No. 2 No. 3 chips, No. 2 chips and No. 4 chips ... cores on the basis of No. 2 chips
Every group of average relative differences value of piece and No. 30 chips, similar, achievable No. 3 chips, No. 4 chips are up to all chips
All comparisons.
By above-mentioned calculating, the screening index value of any two chip can be obtained, as shown in the table:
The average relative differences value for comparing any two chip in 30 chips in above table, determines that minimum average B configuration is opposite
Corresponding two chips of phase difference are as parallel chip.
Power semiconductor modular internal parallel cDNA microarray method in embodiment is avoided to be carried out etc. according to a parameter
The screening technique that grade divides, but screened by comparing the similarity of the transfer characteristic curve of different chips, pass through transfer
Characteristic similarity reflects the dispersibilities of two key parameters of chip threshold voltage and mutual conductance coefficient, and utilizes opposite phase
Difference can be realized the accurate screening of chip as screening index, and the transient state for improving the parallel chip filtered out flows effect.Benefit
Use relative differences value as screening index, relative differences value is smaller, then the transfer characteristic curve similarity of two chips is higher, into
And show the dispersibility of the threshold voltage of two chips and dispersibility all very little of mutual conductance coefficient, the wherein dispersibility of threshold voltage
It is small, illustrate that two chips open the difference very little at moment, the dispersibility of mutual conductance coefficient is small, illustrates the rate of climb base of conducting electric current
This is consistent；Relative differences value is smaller, then the transfer characteristic curve similarity of two chips is higher, after also can show that chip is in parallel
Transient state flow better effect.
The present invention also provides a kind of power semiconductor modular internal parallel cDNA microarray system, Fig. 3 is that the present invention is implemented
The structural schematic diagram of example power semiconductor modular internal parallel cDNA microarray system.
Referring to Fig. 3, the cDNA microarray system 30 of embodiment, comprising:
First obtains module 301, and for obtaining the transfer characteristic curve of multiple chips, the transfer characteristic curve is each
The curve of the variation relation of gate-source voltage and drain current of the chip in opening process.
Specifically, described first obtains module 301, comprising:
Transfer characteristic measured value acquiring unit, the transfer characteristic for obtaining each chip by power analyzer measure
Value, specifically includes:
Step-length obtains subelement, and for obtaining fixed step size, the fixed step size is within a preset range；
Transfer characteristic measured value obtains subelement, and the transfer characteristic for obtaining each chip according to the fixed step size is surveyed
Magnitude.
Transfer characteristic curve acquiring unit draws multiple cores for the transfer characteristic measured value according to each chip
The transfer characteristic curve of piece.
Discrete block 302, for obtaining the more of the transfer characteristic curve for each transfer characteristic curve discretization
A discrete point constitutes chip discrete point set.
Specifically, the discrete block 302, comprising:
Discrete point acquiring unit, for being handled by the way of interpolation the transfer characteristic curve, described in acquisition
Multiple discrete points of transfer characteristic curve.
Second obtains module 303, for obtaining the chip discrete point set of any two chip in multiple chips.
First computing module 304, for calculating several relative differences values of two chips, the relative differences value is
Drain current relative differences value or gate-source voltage relative differences value；The drain current relative differences value be two chips from
Scatterplot concentrates on the relative differences value of the drain current of the discrete point under the same gate-source voltage；The gate-source voltage is opposite
Phase difference is the relative differences for the gate-source voltage that the two chip discrete points concentrate on the discrete point under the same drain current
Value.
Second computing module 305, for calculating the average relative differences value of two chips, the average relative differences value
For the average value of several relative differences values of two chips.
Comparison module 306 determines minimum average B configuration for the average relative differences values all in more multiple chips
Relative differences value.
Objective chip determining module 307, for determining the corresponding two chip conducts of the minimum average B configuration relative differences value
Object filtering chip.
Power semiconductor modular internal parallel cDNA microarray system in the present embodiment is avoided and is carried out according to a parameter
The screening technique of grade classification, but screened by comparing the similarity of the transfer characteristic curve of different chips, by turning
Characteristic similarity is moved to reflect the dispersibility of two key parameters of chip threshold voltage and mutual conductance coefficient, and using relatively
Phase difference realizes the accurate screening of chip as screening index, and the transient state for improving the parallel chip filtered out flows effect.
Used herein a specific example illustrates the principle and implementation of the invention, and above embodiments are said
It is bright to be merely used to help understand method and its core concept of the invention；At the same time, for those skilled in the art, foundation
Thought of the invention, there will be changes in the specific implementation manner and application range.In conclusion the content of the present specification is not
It is interpreted as limitation of the present invention.
Claims (8)
1. a kind of power semiconductor modular internal parallel cDNA microarray method characterized by comprising
The transfer characteristic curve of multiple chips is obtained, the transfer characteristic curve is grid of each chip in opening process
The curve of the variation relation of source voltage and drain current；
By each transfer characteristic curve discretization, obtain multiple discrete points of the transfer characteristic curve, constitute chip from
Scatterplot collection；
Obtain the chip discrete point set of any two chip in multiple chips；
Several relative differences values of two chips are calculated, the relative differences value is drain current relative differences value or grid source
Pole tension relative differences value；The drain current relative differences value is that the two chip discrete points concentrate on the same grid source electrode electricity
The relative differences value of the drain current of the discrete point of pressure；The gate-source voltage relative differences value is the two chip discrete points
Concentrate on the relative differences value of the gate-source voltage of the discrete point under the same drain current；The drain current relative differences value
Calculation formula are as follows:
Wherein,For No. 1 chip and No. 2 chips in kth to the drain current relative differences value of discrete point k (A, B), identical
Under gate-source voltage, for any pair of discrete point k (A, B), A indicates the discrete point on the transfer characteristic curve of No. 1 chip, B
Indicate the discrete point on the transfer characteristic curve with No. 2 chips of No. 1 chip under the same gate-source voltage, the coordinate of point A
For (x, pk), the coordinate of point B is (x, qk)；
The average relative differences value of two chips is calculated, the average relative differences value is opposite for several of two chips
The average value of phase difference；
All average relative differences values, determine minimum average B configuration relative differences value in more multiple chips；
Determine corresponding two chips of the minimum average B configuration relative differences value as object filtering chip.
2. a kind of power semiconductor modular internal parallel cDNA microarray method according to claim 1, which is characterized in that institute
The transfer characteristic curve for obtaining multiple chips is stated, is specifically included:
The transfer characteristic measured value of each chip is obtained by power analyzer；
According to the transfer characteristic measured value of each chip, the transfer characteristic curve of multiple chips is drawn.
3. a kind of power semiconductor modular internal parallel cDNA microarray method according to claim 1, which is characterized in that institute
It states each transfer characteristic curve discretization, obtains multiple discrete points of the transfer characteristic curve, it is discrete to constitute chip
Point set specifically includes:
The transfer characteristic curve is handled by the way of interpolation, obtains the multiple discrete of the transfer characteristic curve
Point.
4. a kind of power semiconductor modular internal parallel cDNA microarray method according to claim 2, which is characterized in that institute
The transfer characteristic measured value for obtaining each chip by power analyzer is stated, is specifically included:
Fixed step size is obtained, the fixed step size is within a preset range；
The transfer characteristic measured value of each chip is obtained according to the fixed step size.
5. a kind of power semiconductor modular internal parallel cDNA microarray system characterized by comprising
First obtains module, and for obtaining the transfer characteristic curve of multiple chips, the transfer characteristic curve is each core
The curve of the variation relation of gate-source voltage and drain current of the piece in opening process；
Discrete block, for obtaining the multiple discrete of the transfer characteristic curve for each transfer characteristic curve discretization
Point constitutes chip discrete point set；
Second obtains module, for obtaining the chip discrete point set of any two chip in multiple chips；
First computing module, for calculating several relative differences values of two chips, the relative differences value is drain electrode electricity
Flow relative differences value or gate-source voltage relative differences value；The drain current relative differences value is the two chip discrete point sets
In discrete point under the same gate-source voltage drain current relative differences value；The gate-source voltage relative differences value
The relative differences value of the gate-source voltage of the discrete point under the same drain current is concentrated on for the two chip discrete points；It is described
The calculation formula of drain current relative differences value are as follows:
Wherein,For No. 1 chip and No. 2 chips in kth to the drain current relative differences value of discrete point k (A, B), identical
Under gate-source voltage, for any pair of discrete point k (A, B), A indicates the discrete point on the transfer characteristic curve of No. 1 chip, B
Indicate the discrete point on the transfer characteristic curve with No. 2 chips of No. 1 chip under the same gate-source voltage, the coordinate of point A
For (x, pk), the coordinate of point B is (x, qk)；
Second computing module, for calculating the average relative differences value of two chips, the average relative differences value is two institutes
State the average value of several relative differences values of chip；
Comparison module determines minimum average B configuration with respect to phase for the average relative differences values all in more multiple chips
Difference；
Objective chip determining module, for determining corresponding two chips of the minimum average B configuration relative differences value as object filtering
Chip.
6. a kind of power semiconductor modular internal parallel cDNA microarray system according to claim 5, which is characterized in that institute
The first acquisition module is stated, is specifically included:
Transfer characteristic measured value acquiring unit, for obtaining the transfer characteristic measured value of each chip by power analyzer；
Transfer characteristic curve acquiring unit draws multiple chips for the transfer characteristic measured value according to each chip
Transfer characteristic curve.
7. a kind of power semiconductor modular internal parallel cDNA microarray system according to claim 5, which is characterized in that institute
Discrete block is stated, is specifically included:
Discrete point acquiring unit obtains the transfer for handling by the way of interpolation the transfer characteristic curve
Characteristic multiple discrete points.
8. a kind of power semiconductor modular internal parallel cDNA microarray system according to claim 6, which is characterized in that institute
Transfer characteristic measured value acquiring unit is stated, is specifically included:
Step-length obtains subelement, and for obtaining fixed step size, the fixed step size is within a preset range；
Transfer characteristic measured value obtains subelement, and the transfer characteristic for obtaining each chip according to the fixed step size measures
Value.
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Family Cites Families (17)
| Publication number | Priority date | Publication date | Assignee | Title |
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| DE112005003538T5 (en) * | 2005-04-15 | 2008-03-06 | Qimonda Ag | IC chip device, test device and interface for performing a functional test of a chip contained in the chip device |
| CN101216528B (en) * | 2008-01-15 | 2010-06-02 | 中国科学院上海微系统与信息技术研究所 | On-chip test method for microwave power amplifier chip and its test system |
| EP2491586B1 (en) * | 2009-10-21 | 2019-11-20 | Semiconductor Energy Laboratory Co. Ltd. | Semiconductor device |
| CN101814443B (en) * | 2010-03-31 | 2011-07-20 | 中国人民解放军国防科学技术大学 | Chip design method for multi-chip module of high-performance processor with optical interface |
| CN202083773U (en) * | 2011-01-18 | 2011-12-21 | 上海理工大学 | Semiconductor parameter testing system |
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