CN109783861B - Chip complementary current-sharing packaging method and device for crimping type IGBT device - Google Patents
Chip complementary current-sharing packaging method and device for crimping type IGBT device Download PDFInfo
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Abstract
The embodiment of the invention provides a chip complementary current-sharing packaging method and a chip complementary current-sharing packaging device of a crimping type IGBT device, wherein the chip complementary current-sharing packaging method of the crimping type IGBT device comprises the following steps: testing the threshold voltage of each chip to be selected; sequencing all chips to be selected according to the threshold voltage to obtain a chip sequence group; sequentially selecting chips to be selected from the chip sequence groups according to a preset quantity requirement and a preset screening condition, and obtaining a plurality of chip groups to be packaged; and packaging each chip group to be packaged according to the on-state resistance of each chip to be selected in each chip group to be packaged. By implementing the invention, the difference of current in each chip is reduced by screening the threshold voltage and considering the influence of on-state resistance, so that complementary current sharing is realized among the chips packaged in the crimping type IGBT device, and the service life of the crimping type IGBT device is further prolonged.
Description
Technical Field
The invention relates to the technical field of power semiconductors, in particular to a chip complementary current-sharing packaging method and device for a crimping type IGBT device.
Background
In the application occasions of high-power electronics, the crimping type device is widely applied to the advantages of multi-chip parallel connection, failure short circuit, easy series connection and the like. When the crimping type IGBT device is switched on, the current flowing through each chip in the device is different due to the difference of chip parameters. This inevitably leads to under the long-term operating condition, and different chips pass through the electric current long-term difference, and then influences crimping formula IGBT device's life. In the prior art, a simple and effective mode for solving the problem of different currents among chips does not exist.
Disclosure of Invention
The embodiment of the invention provides a chip complementary current-sharing packaging method and device of a crimping type IGBT device, which aim to solve the problem that when the crimping type IGBT device in the prior art is switched on, the current flowing through each chip in the device is different due to the difference of chip parameters, so that the service life of the device is influenced.
According to a first aspect, an embodiment of the present invention provides a chip complementary current sharing packaging method for a crimping type IGBT device, including: testing the threshold voltage of each chip to be selected; sorting the chips to be selected according to the threshold voltage to obtain a chip sequence group; sequentially selecting the chips to be selected from the chip sequence group according to a preset quantity requirement and a preset screening condition, and obtaining a plurality of chip groups to be packaged; and packaging each chip group to be packaged according to the on-state resistance of each chip to be selected in each chip group to be packaged.
With reference to the first aspect, in a first implementation manner of the first aspect, the sequentially selecting the chips to be selected from the chip sequence group according to a preset number requirement and a preset screening condition to obtain a plurality of chip groups to be packaged according to a sequence includes:
step S31: sequentially selecting a plurality of chips to be selected according to a preset quantity requirement from the chip sequence group according to the sequence to obtain a standby selection group;
step S32: calculating the maximum deviation of each threshold voltage of each chip to be selected in the alternative group;
step S33: judging whether the maximum deviation meets a preset deviation range or not;
step S34: when each maximum deviation meets a preset deviation range, determining the alternative group as the chip group to be packaged;
and repeating the step S31 to the step S34, and determining a plurality of groups of the chip groups to be packaged until the number of the chips in the chip sequence group is less than the preset number requirement.
With reference to the first implementation manner of the first aspect, in a second implementation manner of the first aspect, the sequentially selecting the chips to be selected from the chip sequence group according to a preset number requirement and a preset screening condition to obtain a plurality of chip groups to be packaged according to a sequence, further includes:
step S35: when each maximum deviation does not meet a preset deviation range, the chip to be selected with the minimum serial number is removed from the alternative group;
step S36: and selecting the chip to be selected with the next serial number from the chip sequence group according to the sequence, supplementing the chip to be selected into the alternative group, and returning to the step S32.
With reference to the first embodiment of the first aspect, in a third embodiment of the first aspect, the maximum deviation is calculated by the following formula:
wherein β represents the maximum deviation, V th,max Represents the maximum value of the threshold voltage, V th,min Represents the minimum value of the threshold voltage, N represents the number of chips。
With reference to the first aspect, in a fourth implementation manner of the first aspect, the packaging each to-be-packaged chip set according to an on-state resistance value of each to-be-selected chip in each to-be-packaged chip set includes: testing the on-state resistance of each chip to be selected in the chip group to be packaged; sequencing all the chips to be selected in the chip group to be packaged from small to large according to the on-state resistance to obtain an on-state resistance chip sequence group; and packaging the chips to be selected which are smaller than the preset serial number in the on-state resistance chip sequence group at the central position of the crimping type IGBT device to be packaged, and packaging the chips to be selected which are larger than or equal to the preset serial number in the on-state resistance chip sequence group at the edge position of the crimping type IGBT device to be packaged.
According to a second aspect, an embodiment of the present invention provides a chip complementary current sharing package device for a crimping type IGBT device, including: the threshold voltage testing module is used for testing the threshold voltage of each chip to be selected; the chip sequence group generating module is used for sequencing the chips to be selected according to the threshold voltage to obtain a chip sequence group; the chip set to be packaged selecting module is used for sequentially selecting the chips to be selected from the chip sequence group according to a preset quantity requirement and a preset screening condition so as to obtain a plurality of chip sets to be packaged; and the packaging module is used for packaging each chip group to be packaged according to the on-state resistance of each chip to be selected in each chip group to be packaged.
According to a third aspect, an embodiment of the present invention provides a non-transitory computer-readable storage medium, which stores computer instructions for causing a computer to execute the chip complementary current sharing packaging method for a crimped IGBT device described in the first aspect or any one of the implementation manners of the first aspect.
According to a fourth aspect, an embodiment of the present invention provides a computer program product, the computer program product including a computer program stored on a non-transitory computer readable storage medium, the computer program including program instructions, when the program instructions are executed by a computer, the computer is caused to execute the chip complementary current sharing packaging method of the crimped IGBT device according to the first aspect or any one of the embodiments of the first aspect.
The technical scheme of the invention has the following advantages:
according to the chip complementary current-sharing packaging method for the crimping type IGBT device, provided by the embodiment of the invention, the threshold voltage of the chips to be selected is tested, the chips are sequenced according to the threshold voltage to obtain the chip sequence group, a plurality of chip groups to be packaged are obtained from the chip sequence group according to the preset quantity requirements and the preset screening conditions, and the chip groups to be packaged are packaged according to the on-state resistance of each chip in the chip groups to be packaged. Therefore, by screening the threshold voltage and considering the influence of the on-state resistance, the difference of the current in each chip is reduced, the complementary current sharing is realized among the chips packaged in the crimping type IGBT device, and the service life of the crimping type IGBT device is prolonged.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 is a flow chart of a chip complementary current sharing packaging method of a crimping type IGBT device in the embodiment of the invention;
fig. 2 is a specific flowchart of sequentially selecting chips to be selected from a chip sequence group according to a preset number requirement and a preset screening condition to obtain a plurality of chip groups to be packaged according to the order in the embodiment of the present invention;
fig. 3 is a specific flowchart of packaging each chipset to be packaged according to the on-state resistance value of each chip to be selected in each chipset to be packaged in the embodiment of the present invention;
FIG. 4 is a schematic structural diagram of a chip complementary current-sharing packaging apparatus of a crimping type IGBT device in the embodiment of the invention;
fig. 5 is a schematic structural diagram of an electronic device in an embodiment of the invention.
Detailed Description
The technical solutions of the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be obtained by a person skilled in the art without making any creative effort based on the embodiments in the present invention, belong to the protection scope of the present invention.
In addition, the technical features involved in the different embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.
Example 1
The embodiment of the invention provides a chip complementary current-sharing packaging method of a crimping type IGBT device, which comprises the following steps of:
step S1: and testing the threshold voltage of each chip to be selected. In practical application, the chip to be selected may be connected to various voltage testers in the prior art or a test system set up according to actual needs for testing, so as to obtain the threshold voltage of each chip, which is not limited in the present invention.
Step S2: and sequencing the chips to be selected according to the threshold voltage to obtain a chip sequence group.
And step S3: and sequentially selecting chips to be selected from the chip sequence groups according to the preset quantity requirement and the preset screening condition and obtaining a plurality of chip groups to be packaged.
And step S4: and packaging each chip group to be packaged according to the on-state resistance of each chip to be selected in each chip group to be packaged.
Through the steps S1 to S4, the chip complementary current sharing packaging method for the crimping type IGBT device according to the embodiment of the present invention reduces the difference of currents in the chips by screening the threshold voltage and considering the influence of the on-state resistance, so that complementary current sharing is realized between the chips packaged in the crimping type IGBT device, and the service life of the crimping type IGBT device is further prolonged.
The chip complementary current-sharing packaging method for the crimping type IGBT device provided by the embodiment of the present invention will be described in detail with reference to specific examples.
Specifically, in an embodiment, in the step S1, the threshold voltage of each chip to be selected is tested. In practical application, because of the influence of the production process, the production batch and the like of a chip manufacturer, the threshold voltages of the chips of the same type have certain difference, in order to reduce the influence of the difference of the threshold voltages on the size of the on-current in the chips, the threshold voltages of all the chips to be selected are tested, and the actual threshold voltage of each chip is recorded.
Specifically, in an embodiment, in the step S2, the chips to be selected are sorted according to the threshold voltage, so as to obtain a chip sequence group. In practical application, the chip sequence group may sequence all chips to be selected according to a sequence from large to small of the threshold voltage, or sequence all chips to be selected according to a sequence from small to large of the threshold voltage, which is not limited in the present invention.
In a preferred embodiment, as shown in fig. 2, in the step S3, the chips to be selected are sequentially selected from the chip sequence group according to the predetermined number requirement and the predetermined screening condition, so as to obtain a plurality of chip groups to be packaged, which specifically includes:
step S31: and sequentially selecting a plurality of chips to be selected with preset quantity requirements from the chip sequence group according to the sequence to obtain a candidate group. Specifically, the preset number is required to be the number of chips to be packaged in the pressure-welding type IGBT device to be packaged, for example: if 10 chips need to be packaged in one crimping type IGBT device, the preset number requirement is 10, and 10 chips to be selected with serial numbers of 1 to 10 are selected from the chip sequence group to form an alternative group.
Step S32: and calculating the maximum deviation of each threshold voltage of each chip to be selected in the alternative group. Specifically, the above maximum deviation can be calculated by the following formula:
wherein β represents the maximum deviation, V th,max Represents the maximum value of the threshold voltage, V th,min Represents the minimum value of the threshold voltage and N represents the number of chips. In practical applications, if there are 10 chips in the selected device group, N =10.
Step S33: and judging whether the maximum deviation meets a preset deviation range. In practical application, the preset deviation range can be set as required, for example, when the threshold voltage of each chip to be selected is larger, the preset deviation range can be expanded, so that the current influence caused by larger threshold voltage deviation is smaller, for example, the preset deviation range is selected to be 5%; when the threshold voltage of each chip to be selected is small, the preset deviation range can be narrowed, because even if the deviation of the threshold voltage is small, the on-current value of the chip may be affected, for example, the preset deviation range is selected to be 2%.
Step S34: and when each maximum deviation meets a preset deviation range, determining the alternative group as the chip group to be packaged. In practical application, if each chip to be selected in the alternative group meets the maximum deviation range, it is indicated that the threshold voltages of the chips to be selected in the alternative group are relatively consistent, and the alternative group can be used as a chip group to be packaged to wait for packaging.
Step S35: and when each maximum deviation does not meet the preset deviation range, eliminating the chip to be selected with the minimum serial number from the alternative group. Specifically, the threshold voltages of the chips produced by the chip manufacturers are in gaussian distribution, so that when the maximum deviation in the alternative group does not meet the preset deviation range, the chip with the minimum serial number in the group can be removed first, and the waste of the chips to be selected is reduced.
In a preferred embodiment, the candidate groups may be sequentially selected from the chip list from two ends according to a sorting order, for example, when the chip list is sorted from a smaller threshold voltage to a larger threshold voltage, the candidate groups may be sequentially selected from two sides of the chip list, when the chip list is selected from a side with a smaller serial number, if the largest deviation does not satisfy the preset deviation range, the chip list with the smallest serial number is rejected, and when the chip list is selected from a side with a larger serial number, if the largest deviation does not satisfy the preset deviation range, the chip list with the largest serial number is rejected.
Step S36: and selecting the chip to be selected with the next serial number from the chip serial group according to the sequence, supplementing the chip to be selected into the alternative group, and returning to the step S32. In practical application, for example, if the serial numbers of the chips to be selected in the original candidate group are numbers 1 to 10, the chips to be selected with the serial number of 1 are removed, the chips to be selected with the serial number of 11 are supplemented into the candidate group, and then the maximum deviation of the candidate group is recalculated.
And repeating the step S31 to the step S34, and determining a plurality of groups of chip groups to be packaged until the number of the chips in the chip sequence group is less than the preset number requirement. In practical application, the number of chips to be selected is large, and in order to select the chips to be selected which can be packaged in the crimping type IGBT device as much as possible, all the chips to be selected need to be repeatedly selected until the number of chips in the chip sequence group does not meet the requirement of the number of chips to be packaged in the crimping type IGBT device.
In a preferred embodiment, the step S4 of encapsulating each to-be-encapsulated chipset according to the on-state resistance value of each to-be-encapsulated chip in each to-be-encapsulated chipset specifically includes:
step S41: and testing the on-state resistance of each chip to be selected in the chip group to be packaged. In practical application, the chip to be selected may be connected to various resistance testers in the prior art or a test system built according to actual needs for testing, so as to obtain the on-state resistance of each chip, which is not limited by the invention.
Step S42: and sequencing all chips to be selected in the chip group to be packaged from small to large according to the on-state resistance to obtain an on-state resistance chip sequence group. In practical application, considering that a plurality of chips are packaged in a crimping type IGBT device, due to the influence of chip heat dissipation, the heat dissipation of the chip packaged at the middle position is poor, namely the equivalent resistance of the chip at the middle position is larger than the on-state resistance, and the heat dissipation of the chip packaged at the edge position is good, namely the difference between the equivalent resistance of the chip at the edge position and the on-state resistance is small, so that the on-state resistances in the chip groups to be packaged are sequenced to obtain the on-state resistance chip sequence group.
Step S43: and packaging each chip to be selected which is smaller than the preset serial number in the on-state resistance chip sequence group at the central position of the crimping type IGBT device to be packaged, and packaging each chip to be selected which is greater than or equal to the preset serial number in the on-state resistance chip sequence group at the edge position of the crimping type IGBT device to be packaged. In practical applications, the preset serial number may be set as needed, for example, when the to-be-encapsulated crimp type IGBT device needs to encapsulate 10 chips, the preset serial number may be 5, that is, the first 4 chips to be selected in the on-state resistor chip sequence group are encapsulated in the central position of the to-be-encapsulated crimp type IGBT device, and the rest chips to be selected are encapsulated in the edge position of the device, where the edge position is the outer encapsulation position in the chip encapsulation position set for the to-be-encapsulated crimp type IGBT device.
By executing the steps S1 to S4, the chip complementary current sharing packaging method for the crimping type IGBT device according to the embodiment of the present invention reduces the difference between the currents in the chips by screening the threshold voltage and considering the influence of the on-state resistance, and reduces the influence of the chip heat dissipation condition on the current balance, so that complementary current sharing is realized between the chips packaged in the crimping type IGBT device, and the service life of the crimping type IGBT device is further prolonged.
Example 2
The embodiment of the invention provides a chip complementary current-sharing packaging device of a crimping type IGBT device, as shown in fig. 4, the chip complementary current-sharing packaging device of the crimping type IGBT device comprises:
and the threshold voltage testing module 1 is used for testing the threshold voltage of each chip to be selected. See the description relating to step S1 in example 1 for details.
And the chip sequence group generating module 2 is used for sequencing the chips to be selected according to the threshold voltage to obtain a chip sequence group. See the description related to step S2 in example 1 for details.
And the chip group to be packaged selecting module 3 is used for sequentially selecting chips to be selected from the chip sequence group according to the preset quantity requirement and the preset screening condition and obtaining a plurality of chip groups to be packaged. . See the description relating to step S3 in example 1 for details.
And the packaging module 4 is used for packaging each chip group to be packaged according to the on-state resistance of each chip to be selected in each chip group to be packaged. See the description relating to step S4 in example 1 for details.
Through the cooperative cooperation of the components, the chip complementary current-sharing packaging device of the crimping type IGBT device reduces the difference of current in each chip by screening the threshold voltage and considering the influence of on-state resistance, so that complementary current sharing is realized among the chips packaged in the crimping type IGBT device, and the service life of the crimping type IGBT device is further prolonged.
Example 3
An embodiment of the present invention provides a non-transitory computer storage medium, where a computer executable instruction is stored in the computer storage medium, and the computer executable instruction can execute the chip complementary current sharing packaging method for the crimp-type IGBT device in any embodiment 1. The storage medium may be a magnetic Disk, an optical Disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a Flash Memory (Flash Memory), a Hard Disk (Hard Disk Drive, abbreviated as HDD), a Solid State Drive (SSD), or the like; the storage medium may also comprise a combination of memories of the kind described above.
Example 4
The embodiment of the invention provides electronic equipment of a chip complementary current sharing packaging method of a crimping type IGBT device, a schematic structural diagram of the electronic equipment is shown in FIG. 5, and the equipment comprises: one or more processors 410 and a memory 420, with one processor 410 being an example in fig. 5.
The electronic device performing the chip complementary current sharing packaging method of the crimping type IGBT device may further include: an input device 430 and an output device 440.
The processor 410, the memory 420, the input device 430, and the output device 440 may be connected by a bus or other means, such as the bus connection in fig. 5.
The memory 420 is used as a non-transitory computer readable storage medium, and may be used to store a non-transitory software program, a non-transitory computer executable program, and a module, such as program instructions/modules corresponding to the chip complementary current sharing packaging method for the crimp-type IGBT device in the embodiment of the present application, and the processor 410 executes various functional applications and data processing of the server by running the non-transitory software program, instructions, and modules stored in the memory 420, that is, implements the chip complementary current sharing packaging method for the crimp-type IGBT device in the embodiment of the method.
The memory 420 may include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application program required for at least one function; the storage data area can store data and the like created according to the use of the chip complementary current-sharing package processing device of the crimping type IGBT device. Further, the memory 420 may include high speed random access memory, and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid state storage device. In some embodiments, the memory 420 optionally includes memory remotely located from the processor 410, which may be connected to the chip complementary current sharing package of the crimp type IGBT device through a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
The input device 430 may receive input numeric or character information and generate key signal inputs related to user settings and function control related to the processing device of the chip complementary current sharing package operation of the crimp-type IGBT device. The output device 440 may include a display device such as a display screen.
One or more modules are stored in the memory 420, which when executed by the one or more processors 410 perform the methods illustrated in fig. 1-3.
The product can execute the method provided by the embodiment of the invention, and has corresponding functional modules and beneficial effects of the execution method. For details of the embodiments of the present invention, reference may be made to the description of the embodiments shown in fig. 1 to 3.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. This need not be, nor should it be exhaustive of all embodiments. And obvious variations or modifications therefrom are within the scope of the invention.
Claims (6)
1. A chip complementary current sharing packaging method of a crimping type IGBT device is characterized by comprising the following steps:
testing the threshold voltage of each chip to be selected;
sorting the chips to be selected according to the threshold voltage to obtain a chip sequence group;
sequentially selecting the chips to be selected from the chip sequence group according to a preset quantity requirement and a preset screening condition, and obtaining a plurality of chip groups to be packaged;
packaging each chip group to be packaged according to the on-state resistance of each chip to be selected in each chip group to be packaged;
the method for sequentially selecting the chips to be selected from the chip sequence group according to the preset quantity requirement and the preset screening condition and obtaining a plurality of chip groups to be packaged comprises the following steps:
step S31: sequentially selecting a plurality of chips to be selected according to a preset quantity requirement from the chip sequence group according to the sequence to obtain a standby selection group;
step S32: calculating the maximum deviation of each threshold voltage of each chip to be selected in the alternative group;
step S33: judging whether the maximum deviation meets a preset deviation range or not;
step S34: when each maximum deviation meets a preset deviation range, determining the alternative group as the chip group to be packaged;
repeatedly executing the step S31 to the step S34, and determining a plurality of groups of the chip groups to be packaged until the number of the chips in the chip sequence group is less than the preset number requirement;
the packaging of each chip group to be packaged according to the on-state resistance value of each chip to be selected in each chip group to be packaged comprises the following steps:
testing the on-state resistance of each chip to be selected in the chip group to be packaged;
sequencing all the chips to be selected in the chip group to be packaged from small to large according to the on-state resistance to obtain an on-state resistance chip sequence group;
and packaging the chips to be selected which are smaller than the preset serial number in the on-state resistance chip sequence group at the central position of the crimping type IGBT device to be packaged, and packaging the chips to be selected which are larger than or equal to the preset serial number in the on-state resistance chip sequence group at the edge position of the crimping type IGBT device to be packaged.
2. The chip complementary current-sharing packaging method of the crimping type IGBT device according to claim 1, wherein the chips to be selected are sequentially selected from the chip sequence group according to a preset number requirement and a preset screening condition, so as to obtain a plurality of chip groups to be packaged, and further comprising:
step S35: when each maximum deviation does not meet a preset deviation range, the chip to be selected with the minimum serial number is removed from the alternative group;
step S36: and selecting the chip to be selected with the next serial number from the chip sequence group according to the sequence, supplementing the chip to be selected into the alternative group, and returning to the step S32.
3. The chip complementary current sharing packaging method of the crimping type IGBT device according to claim 1,
calculating the maximum deviation by the following formula:
wherein β represents the maximum deviation, V th,max Represents the maximum value of the threshold voltage, V th,min Represents the minimum value of the threshold voltage, and N represents the number of chips.
4. The utility model provides a complementary packaging hardware that flow equalizes of chip of crimping type IGBT device which characterized in that includes:
the threshold voltage testing module (1) is used for testing the threshold voltage of each chip to be selected;
the chip sequence group generating module (2) is used for sequencing the chips to be selected according to the threshold voltage to obtain a chip sequence group;
the chip set to be packaged selecting module (3) is used for sequentially selecting the chips to be selected from the chip sequence set according to the preset quantity requirement and the preset screening condition and obtaining a plurality of chip sets to be packaged; the method for sequentially selecting the chips to be selected from the chip sequence group according to the preset quantity requirement and the preset screening condition and obtaining a plurality of chip groups to be packaged comprises the following steps:
step S31: sequentially selecting a plurality of chips to be selected according to a preset quantity requirement from the chip sequence group according to the sequence to obtain a standby selection group;
step S32: calculating the maximum deviation of each threshold voltage of each chip to be selected in the alternative group;
step S33: judging whether the maximum deviation meets a preset deviation range or not;
step S34: when each maximum deviation meets a preset deviation range, determining the alternative group as the chip group to be packaged;
repeatedly executing the step S31 to the step S34, and determining a plurality of groups of the chip groups to be packaged until the number of the chips in the chip sequence group is less than the preset number requirement;
the packaging module (4) is used for packaging each chip group to be packaged according to the on-state resistance of each chip to be selected in each chip group to be packaged; the packaging of each chip group to be packaged according to the on-state resistance value of each chip to be selected in each chip group to be packaged comprises the following steps:
testing the on-state resistance of each chip to be selected in the chip group to be packaged;
sequencing all the chips to be selected in the chip group to be packaged from small to large according to the on-state resistance to obtain an on-state resistance chip sequence group;
and packaging the chips to be selected which are smaller than the preset serial number in the on-state resistance chip sequence group at the central position of the crimping type IGBT device to be packaged, and packaging the chips to be selected which are larger than or equal to the preset serial number in the on-state resistance chip sequence group at the edge position of the crimping type IGBT device to be packaged.
5. A non-transitory computer readable storage medium, wherein the non-transitory computer readable storage medium stores computer instructions, which when executed by a processor, implement the chip complementary current sharing packaging method of the crimp-type IGBT device according to any one of claims 1-3.
6. An electronic device, comprising:
at least one processor; and
a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor to cause the at least one processor to perform the chip complementary current sharing packaging method of the crimped IGBT device according to any one of claims 1-3.
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| 压接型IGBT封装寄生参数对芯片开通过程中的均流影响分析;张睿等;《智能电网》;20160410(第04期);全文 * |
| 器件参数对SiC MOSFET并联均流影响的统计分析;柯俊吉等;《半导体技术》;20180303(第03期);全文 * |
| 器件特性参数对SiC MOSFET静动态均流影响的实验研究;孙鹏等;《智能电网》;20170810(第08期);全文 * |
| 大功率IGBT器件并联均流研究;余伟等;《大功率变流技术》;20170918(第05期);全文 * |
| 高压IGBT芯片高温测试温度的阈值电压标定;涂启志等;《电子与封装》;20171020(第10期);全文 * |
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