CN103915417B - A kind of test device group's feeler switch - Google Patents
A kind of test device group's feeler switch Download PDFInfo
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- CN103915417B CN103915417B CN201410142677.9A CN201410142677A CN103915417B CN 103915417 B CN103915417 B CN 103915417B CN 201410142677 A CN201410142677 A CN 201410142677A CN 103915417 B CN103915417 B CN 103915417B
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- effect transistor
- feeler switch
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Abstract
A kind of TEG feeler switch, including: field-effect transistor, there is on it substrate being formed with source electrode, grid and drain electrode, described source electrode, grid and drain electrode are arranged in order in the first direction on the surface of described substrate, and described grid extends along the second direction vertical with described first direction on the surface of described substrate;Control wall, close on the first end and the second end that described grid extends in this second direction, and close on described substrate, and not with described grid and described substrate contact, conductive material formed;Source electrode testing cushion, is connected to described source electrode by conductor;Grid testing cushion, is connected to described grid by conductor;Drain electrode testing cushion, is connected to described drain electrode by conductor;And control pad, it is connected to described control wall by conductor, for External Control Voltage being provided described control wall.Owing to the application has distinguished the difference between the edge of field-effect transistor and middle part reliability and operating characteristic, therefore, it is possible to fully understand the operating characteristic of semiconductor device.
Description
Technical field
The application relates to a kind of test device group (TEG:Test Element Group) feeler switch (Test
Key), one is particularly related to for eliminating the hump effect (Hump of TFT (TFT)
Effect) TEG feeler switch.
Background technology
In semiconductor device production process, through monitoring semiconductor device frequently with TEG feeler switch
Product attribute or Technical expression.
Fig. 1 illustrates the schematic diagram of a kind of TEG feeler switch of the prior art.Fig. 2 example
Property show field-effect transistor in the TEG feeler switch of the prior art shown in Fig. 1 containing camel
The schematic diagram of the transfer characteristic of peak effect.It is of the prior art that Fig. 3 illustrates shown in Fig. 1
The schematic diagram of the source-drain current distribution of field-effect transistor in TEG feeler switch.
As shown in fig. 1, TEG feeler switch of the prior art includes: field-effect transistor 1, test
Pad Ps, testing cushion Pg and testing cushion Pd.Wherein, described field-effect transistor 1 includes substrate 10,
On substrate 10, along raceway groove (i.e. current channel between source electrode and the drain electrode) side of field-effect transistor 1
It is arranged in sequence with source S, grid G and drain D to a-a.Wherein, source S is connected by conductor M
To testing cushion Ps being positioned at outside field-effect transistor 1, grid G is connected to by another strip conductor M
Outside testing cushion Pg, drain D is connected to testing cushion Pd of outside by another strip conductor M again.Its
In, the two ends of grid G extend along the width b-b of field-effect transistor 1, and width b-b hangs down
Straight in channel direction a-a.
Testing product attribute or the technique table of the semiconductor device comprising the batch such as field-effect transistor 1
Now, by source electrode testing cushion Ps, drain electrode testing cushion Pd and grid testing cushion Pg, test signal is applied
To source S, drain D and the grid G of this field-effect transistor 1, obtain field-effect transistor 1
Voltage/current response curve, such as transfer characteristic curve, it follows that the product of this batch semiconductor device
Characteristic or Technical expression.
But, in the technique producing field-effect transistor, imitate in the field as shown in dotted line frame 2 in Fig. 1
Answer the marginal portion of transistor 1, due near field-effect transistor trench edges at than in the middle part of raceway groove more more
Easily there is defective workmanship, such as, the oxide layer of polysilicon edge is often because of spreadability (Step Coverage)
The best, cause oxide layer relatively thin, add the Aspect Ratio factor of field effect transistor tube edges so that field is imitated
Answer the transfer characteristic at transistor edges to cause in advance, cause, in subcritical district, hump phenomenon occurs, make
Obtain the critical voltage definition difficulty of field-effect transistor.
As shown in Figure 2, the critical voltage in the middle part of field-effect transistor 1 raceway groove is Vt, and transfer characteristic is bent
The relation curve of line, i.e. source-drain current Id and gate source voltage Vgs is along dotted line from Vt, then to A point it
After solid line.Critical voltage at field-effect transistor 1 trench edges is Vh, owing to Vh is less than Vt
And shorting advance, so that the source-drain current Id of whole field-effect transistor produced one before A point
The hump of individual small area analysis, thus distorted the transfer characteristic curve of whole field-effect transistor, mask field
Critical voltage Vt when effect transistor normally works, i.e. critical voltage Vt in the middle part of field-effect transistor.
Although the curve shown in Fig. 2 reflects the situation of nmos type field-effect transistor, it will be appreciated that this
Hump phenomenon is not limited to the type of field-effect transistor, the most either nmos type field-effect transistor, also
It is that pmos type field-effect transistor all can exist.
As shown in Figure 3, between the source S and drain D of field-effect transistor 1, there is conducting electric current
Time, such as can produce CURRENT DISTRIBUTION as shown by arrows in FIG..Due to when close to critical voltage near field
Meeting shorting advance at effect transistor trench edges, thus electric current can be flow through in the middle part of raceway groove ahead of time by ratio, therefore,
When the TEG feeler switch using prior art as shown in Figure 1 carries out TEG test, due to not district
Difference between edge and middle part reliability and the operating characteristic of branch effect transistor, therefore can not be complete
The operating characteristic of semiconductor device is understood in face, thus is unfavorable for the improvement of semiconductor device product quality and carries
High.
Summary of the invention
In order to solve one of above-mentioned technical problem, the application provides a kind of TEG feeler switch, including: field
Effect transistor, has on it substrate being formed with source electrode, grid and drain electrode, described source electrode, grid and
Drain electrode is arranged in order in the first direction on the surface of described substrate, and described grid is on the edge, surface of described substrate
The second direction vertical with described first direction extends;Control wall, close on described grid in described second party
Upwardly extending first end and the second end, and close on described substrate, and not with described grid and described lining
The end, contacts, conductive material formed;Source electrode testing cushion, is connected to described source electrode by conductor;Grid is surveyed
Examination pad, is connected to described grid by conductor;Drain electrode testing cushion, is connected to described drain electrode by conductor;
And control pad, it is connected to described control wall by conductor, for providing described by External Control Voltage
Control wall.
Wherein, described control wall overlaps with described grid in the lower section of described grid.
Wherein, described control wall in the lower section of described grid and does not has overlapping with described grid.
Wherein, described conductive material is polysilicon.
Wherein, described conductive material is metal.
Wherein, the Part I of first end closing on described grid of described control wall with close on described grid
The Part II of the second end be connected to described control pad by conductor.
Wherein, described control wall forms around in described source electrode or described drain electrode.
Wherein, described conductor is metal.
Use the TEG feeler switch of the application, comprise criticizing of the field-effect transistor such as the application in test
When the product attribute of secondary semiconductor device or Technical expression, provide outside control via control pad to controlling wall
Voltage processed, i.e. bias voltage, imitate by controlling the electric capacity between wall and fieldistor channel edge
The conducting situation of fieldistor channel edge should be affected so that the voltage applied at grid reaches
Before critical voltage in the middle part of fieldistor channel, fieldistor channel edge no longer does sth. in advance
Conducting, thus eliminate the hump effect in field-effect transistor such that it is able to obtain field-effect transistor
The transfer characteristic curve at middle part, and understood the critical voltage in the middle part of field-effect transistor, i.e. field effect
Critical voltage during its normal operation.Due to the application distinguished field-effect transistor edge and
Difference between middle part reliability and operating characteristic, therefore, it is possible to fully understand that the work of semiconductor device is special
Property, thus beneficially the improving of semiconductor device product quality.
Accompanying drawing explanation
Below with reference to appended accompanying drawing, embodiments herein is described, wherein:
Fig. 1 illustrates the schematic diagram of a kind of TEG feeler switch of the prior art;
It is brilliant that Fig. 2 illustrates field effect in the TEG feeler switch of the prior art shown in Fig. 1
The schematic diagram of the transfer characteristic containing hump effect of body pipe;
It is brilliant that Fig. 3 illustrates field effect in the TEG feeler switch of the prior art shown in Fig. 1
The schematic diagram of the source-drain current distribution of body pipe;
Fig. 4 illustrates the schematic diagram of the TEG feeler switch according to the application first embodiment;
Fig. 5 illustrates the schematic diagram of the TEG feeler switch according to the application the second embodiment;
Fig. 6 illustrates the schematic diagram of the TEG feeler switch according to the application the 3rd embodiment;
Fig. 7 illustrates the schematic diagram of the TEG feeler switch according to the application the 4th embodiment;With
And
Fig. 8 illustrates eliminating of field-effect transistor in the TEG feeler switch according to the application
The schematic diagram of the transfer characteristic of hump effect.
Detailed description of the invention
Describing the application in detail below in conjunction with Fig. 4 to Fig. 8, the most identical reference represents
Same or analogous equipment, material or device.
Fig. 4 illustrates the schematic diagram of the TEG feeler switch according to the application first embodiment.For
Be easy to explanation, intend here in FIG shown in prior art TEG feeler switch on the basis of come
Further describe the TEG feeler switch according to the application first embodiment shown in Fig. 4.
As shown in Figure 4, the TEG feeler switch of the application first embodiment includes: field-effect transistor 1,
There is on it substrate 10 being formed with source S, grid G and drain D, described source S, grid G
With drain D on the surface of described substrate 10 in the first direction (i.e. the channel direction of field-effect transistor 1)
A-a is arranged in order, and described grid G is vertical with described first direction on edge, the surface of described substrate 10
Second direction (i.e. the width of field-effect transistor 1) b-b extends;Control wall 3, have and face respectively
The Part I C1 of the first end G1 that nearly described grid G extends in described second direction b-b and facing
The second end G2 Part II C2 that nearly described grid G extends in described second direction b-b, and first
Part C1 and Part II C2 close on described substrate 10, and not with described grid G and described lining
The end 10, contacts, and wherein said control wall 3 is formed by conductive material;Source electrode testing cushion Ps, passes through conductor
M is connected to described source S;Grid testing cushion Pg, is connected to described grid G by conductor M;Leakage
Pole testing cushion Pd, is connected to described drain D by conductor M;And control pad Pc, by conductor M
It is connected to the Part I C1 and Part II C2 of described control wall 3, for by External Control Voltage (not
Illustrate) described control wall 3 is provided to.
In the diagram, the Part I C1 and Part II C2 that control wall 3 are positioned at the lower section of grid G,
And control the Part I C1 and Part II C2 of wall 3 in the lower section of grid G and grid G respectively
Overlap.
In the present embodiment, the quasiconductor of the batch of the field-effect transistor 1 in test comprises such as Fig. 4
When the product attribute of device or Technical expression, except by source electrode testing cushion Ps, grid testing cushion Pg and
Drain electrode testing cushion Pd applies test signals to the source S of field-effect transistor 1, grid G and drain D
Outside, also provide External Control Voltage via control pad Pc to controlling wall 3, i.e. bias voltage, passes through
Control the capacity effect between wall 3 and field-effect transistor 1 trench edges and affect field-effect transistor
Conducting situation at 1 trench edges so that the voltage applied in grid G reaches field-effect transistor 1 ditch
Before critical voltage Vt in the middle part of road, conducting no longer ahead of time at field-effect transistor 1 trench edges, from
And eliminate the hump effect in field-effect transistor 1 such that it is able to obtain in the middle part of field-effect transistor 1
Transfer characteristic curve, and understood the critical voltage Vt in the middle part of field-effect transistor 1, i.e. field effect
Critical voltage Vt when transistor 1 normally works.
Should be appreciated that the field-effect transistor in the present embodiment is not limited to nmos type, or
Pmos type.
When the TEG feeler switch using the application as shown in Figure 4 carries out TEG test, due to
Distinguish the difference between the edge of field-effect transistor 1 and middle part reliability and operating characteristic, therefore
Can fully understand the operating characteristic of semiconductor device, thus beneficially the changing of semiconductor device product quality
It is apt to and improves.
In the TEG feeler switch in this embodiment and following example of the application, it is used for forming control
The conductive material of wall 3 processed can be polysilicon or metal, and conductor M can be metal.
In order to be more fully understood that the application, Fig. 5 illustrates according to the application the second embodiment
The schematic diagram of TEG feeler switch.The TEG feeler switch of the application the second embodiment shown in Fig. 5 and Fig. 4
Shown in the difference of TEG feeler switch of the application first embodiment be, the control in Fig. 5
The Part I C1 and Part II C2 of wall 30 are in the lower section of grid G, and do not have weight with grid G
Folded.Although the control wall 30 in Fig. 5 is not overlapping with grid G, owing to controlling the Part I of wall 30
C1 and Part II C2 is near two ends G1 and G2 of grid G, namely close field-effect transistor 1
The edge of raceway groove, therefore, remain able to by controlling wall 30 and field-effect transistor 1 raceway groove limit
Capacity effect between edge affects the conducting situation at field-effect transistor 1 trench edges, thus takes
The effect of the hump effect eliminating field-effect transistor 1 that must be similar with the application first embodiment.
In order to be more fully understood that the application, Fig. 6 illustrates according to the application the 3rd embodiment
The schematic diagram of TEG feeler switch.The TEG feeler switch of the application the 3rd embodiment shown in Fig. 6 and Fig. 4
Shown in the difference of TEG feeler switch of the application first embodiment be, the control in Fig. 6
Wall 300 forms around in source electrode D or source S, and controls the first of wall 300
Part C1 and Part II C2 in the lower section of grid G respectively two ends G1 and G2 with grid G have portion
Divide overlap.Owing to controlling the Part I C1 and Part II C2 of wall 300 all near the two of grid G
End G1 and G2, namely the edge of the raceway groove near field-effect transistor 1, therefore, remain able to lead to
Cross the capacity effect between control wall 300 and field-effect transistor 1 trench edges brilliant to affect field effect
Conducting situation at body pipe 1 trench edges, thus obtain the elimination field similar with the application first embodiment
The effect of the hump effect of effect transistor 1.
In order to be more fully understood that the application, Fig. 7 illustrates according to the application the 4th embodiment
The schematic diagram of TEG feeler switch.The TEG feeler switch of the application the 4th embodiment shown in Fig. 6 and Fig. 5
Shown in the difference of TEG feeler switch of the application the second embodiment be, the control in Fig. 7
Wall 3000 forms around in source electrode D or source S, and in the lower section of grid G not
Have overlapping with grid G.Owing to controlling the Part I C1 and Part II C2 of wall 3000 all near grid
Two ends G1 and G2 of pole G, namely the edge of the raceway groove near field-effect transistor 1, therefore, still
So can carry out shadow by the capacity effect between control wall 3000 and field-effect transistor 1 trench edges
Ring the conducting situation at field-effect transistor 1 trench edges, thus obtain and the application first embodiment class
As eliminate the effect of hump effect of field-effect transistor 1.
Fig. 8 illustrates eliminating of field-effect transistor in the TEG feeler switch according to the application
The schematic diagram of the transfer characteristic of hump effect.As shown in Figure 8, owing to eliminating hump effect, field is imitated
The transfer characteristic curve answering transistor overall have been able to field-effect transistor in the middle part of transfer characteristic bent
Line is basically identical, has clearly showed that the critical voltage Vt in the middle part of field-effect transistor, and source and drain
Electric current Id presents good linear relationship before saturation with Vgs.
Use the TEG feeler switch of the application, comprise the field-effect transistor such as the application in test
When the product attribute of the semiconductor device of batch or Technical expression, provide to controlling wall via control pad
External Control Voltage, i.e. bias voltage, by control wall and fieldistor channel edge it
Between capacity effect affect the conducting situation of fieldistor channel edge so that at grid
Before the voltage applied reaches the critical voltage in the middle part of fieldistor channel, field-effect transistor
Conducting no longer ahead of time at trench edges, thus eliminate the hump effect in field-effect transistor, from
And be obtained in that the transfer characteristic curve in the middle part of field-effect transistor, and understood field effect transistor
Critical voltage in the middle part of pipe, critical voltage when i.e. field-effect transistor normally works.Due to this Shen
Please distinguish the difference between the edge of field-effect transistor and middle part reliability and operating characteristic,
Therefore, it is possible to fully understand the operating characteristic of semiconductor device, thus beneficially semiconductor device product
Improving of quality.
Although with reference to exemplary embodiment describing the application, it is to be understood that, term used is explanation
With exemplary and nonrestrictive term.Owing to the application can be embodied as in a variety of forms, so
Should be appreciated that above-described embodiment is not limited to any aforesaid details, and should be limited in appended claims
In the range of explain widely, therefore fall in claim or its equivalency range whole change and remodeling
All should be appended claims to be contained.
Claims (8)
1. a TEG feeler switch, including:
Field-effect transistor, has on it substrate being formed with source electrode, grid and drain electrode, described source
Pole, grid and drain electrode are arranged in order in the first direction on the surface of described substrate, and described grid is in institute
The surface stating substrate extends along the second direction vertical with described first direction;
Control wall, close on the first end and the second end that described grid extends in this second direction,
And close on described substrate, and not with described grid and described substrate contact, conductive material formed;
Source electrode testing cushion, is connected to described source electrode by conductor;
Grid testing cushion, is connected to described grid by conductor;
Drain electrode testing cushion, is connected to described drain electrode by conductor;And
Control pad, is connected to described control wall by conductor, for being provided by External Control Voltage
Described control wall.
TEG feeler switch the most according to claim 1, wherein,
Described control wall overlaps with described grid in the lower section of described grid.
TEG feeler switch the most according to claim 1, wherein,
Described control wall in the lower section of described grid and does not has overlapping with described grid.
4. according to the TEG feeler switch that in claim 1-3, any one is described, wherein,
Described conductive material is polysilicon.
5. according to the TEG feeler switch that in claim 1-3, any one is described, wherein,
Described conductive material is metal.
6. according to the TEG feeler switch that in claim 1-3, any one is described, wherein, described control
The Part I of first end closing on described grid of wall processed and the of the second end closing on described grid
Two parts are connected to described control pad by conductor.
7. according to the TEG feeler switch that in claim 1-3, any one is described, wherein, described control
Wall processed forms around in described source electrode or described drain electrode.
8. according to the TEG feeler switch that in claim 1-3, any one is described, wherein,
Described conductor is metal.
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CN201410142677.9A CN103915417B (en) | 2014-04-10 | 2014-04-10 | A kind of test device group's feeler switch |
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CN201410142677.9A CN103915417B (en) | 2014-04-10 | 2014-04-10 | A kind of test device group's feeler switch |
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CN107957541B (en) * | 2017-11-21 | 2019-11-08 | 华北电力大学 | A kind of power semiconductor modular internal parallel cDNA microarray method and system |
CN109166507A (en) * | 2018-11-01 | 2019-01-08 | 京东方科技集团股份有限公司 | Testing element group, electrical performance test method, array substrate, display device |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6033940A (en) * | 1995-05-25 | 2000-03-07 | Sharp Kabushiki Kaisha | Anodization control for forming offset between semiconductor circuit elements |
CN1426098A (en) * | 2001-11-02 | 2003-06-25 | 联华电子股份有限公司 | Test window structure for monitoring self alignment of silicide residue |
US6586765B2 (en) * | 1999-12-20 | 2003-07-01 | Taiwan Semiconductor Manufacturing Company | Wafer-level antenna effect detection pattern for VLSI |
CN101707209A (en) * | 2009-11-26 | 2010-05-12 | 上海宏力半导体制造有限公司 | Lateral diffusion metal oxide semiconductor transistor structure |
CN102097475A (en) * | 2009-11-27 | 2011-06-15 | 美格纳半导体有限公司 | Semiconductor device and method for fabricating semiconductor device |
-
2014
- 2014-04-10 CN CN201410142677.9A patent/CN103915417B/en active Active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6033940A (en) * | 1995-05-25 | 2000-03-07 | Sharp Kabushiki Kaisha | Anodization control for forming offset between semiconductor circuit elements |
US6586765B2 (en) * | 1999-12-20 | 2003-07-01 | Taiwan Semiconductor Manufacturing Company | Wafer-level antenna effect detection pattern for VLSI |
CN1426098A (en) * | 2001-11-02 | 2003-06-25 | 联华电子股份有限公司 | Test window structure for monitoring self alignment of silicide residue |
CN101707209A (en) * | 2009-11-26 | 2010-05-12 | 上海宏力半导体制造有限公司 | Lateral diffusion metal oxide semiconductor transistor structure |
CN102097475A (en) * | 2009-11-27 | 2011-06-15 | 美格纳半导体有限公司 | Semiconductor device and method for fabricating semiconductor device |
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