CN103915417A - Test device cluster testing key - Google Patents
Test device cluster testing key Download PDFInfo
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- CN103915417A CN103915417A CN201410142677.9A CN201410142677A CN103915417A CN 103915417 A CN103915417 A CN 103915417A CN 201410142677 A CN201410142677 A CN 201410142677A CN 103915417 A CN103915417 A CN 103915417A
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Abstract
The invention discloses a TEG testing key which comprises a field effect transistor, a control wall, a source electrode test pad, a grid electrode test pad, a drain electrode test pad and a control pad. The field effect transistor is provided with a substrate on which a source electrode, a grid electrode and a drain electrode are formed. The surfaces, on the substrate, of the source electrode, the grid electrode and the drain electrode are sequentially arranged in the first direction. The surface, on the substrate, of the grid electrode extends in the second direction perpendicular to the first direction. The control wall is adjacent to the first end and the second end, extending in the second direction, of the grid electrode and adjacent to the substrate, does not make contact with the grid electrode and the substrate and is made of electric conduction materials. The source electrode test pad is connected to the source electrode through a conductor. The grid electrode test pad is connected to the grid electrode through a conductor. The drain electrode test pad is connected to the drain electrode through a conductor. The control pad is connected to the control wall through a conductor, and the control pad is used for providing the external control voltage for the control wall. According to the TEG testing key, the difference between the reliability and the working characteristics of the edge and the middle of the field effect transistor is differentiated, and therefore the working characteristics of a semiconductor device can be comprehensively mastered.
Description
Technical field
The application relates to a kind of test component group (TEG:Test Element Group) feeler switch (Test Key), relates in particular to a kind of for eliminating the TEG feeler switch of hump effect (Hump Effect) of Thin Film Transistor (TFT) (TFT).
Background technology
In semiconductor device production process, often adopt TEG feeler switch to monitor product performance or the technique performance of semiconductor device.
Fig. 1 illustrates a kind of schematic diagram of TEG feeler switch of the prior art.Fig. 2 illustrates the schematic diagram of the transfer characteristic that contains hump effect of field-effect transistor in the TEG feeler switch of the prior art shown in Fig. 1.Fig. 3 illustrates the schematic diagram of the source-drain current distribution of field-effect transistor in the TEG feeler switch of the prior art shown in Fig. 1.
As shown in fig. 1, TEG feeler switch of the prior art comprises: field-effect transistor 1, testing cushion Ps, testing cushion Pg and testing cushion Pd.Wherein, described field-effect transistor 1 comprises substrate 10, on substrate 10, is aligned in sequence with source S, grid G and drain D along raceway groove (being the current channel between source electrode and drain electrode) the direction a-a of field-effect transistor 1.Wherein, source S is connected to the testing cushion Ps that is positioned at field-effect transistor 1 outside by conductor M, and grid G is connected to outside testing cushion Pg by another strip conductor M, and drain D is connected to outside testing cushion Pd by another strip conductor M again.Wherein, extend along the Width b-b of field-effect transistor 1 at the two ends of grid G, and Width b-b is perpendicular to channel direction a-a.
Test pack containing as field-effect transistor 1 batch the product performance of semiconductor device or technique while showing, by source electrode testing cushion Ps, drain electrode testing cushion Pd and grid testing cushion Pg, test signal is applied to source S, drain D and the grid G of this field-effect transistor 1, obtain the voltage/current response curve of field-effect transistor 1, for example transfer characteristic curve, learns product performance or the technique performance of this batch of semiconductor device thus.
But, in the technique of production field-effect transistor, in the marginal portion of the field-effect transistor 1 as shown in dotted line frame 2 in Fig. 1, because the trench edges place near field-effect transistor more easily exists defective workmanship than raceway groove middle part, for example, the oxide layer at polysilicon edge is often because spreadability (Step Coverage) is not good, cause oxide layer thinner, add the Aspect Ratio factor of field effect transistor tube edges, the transfer characteristic of field-effect transistor edge can be caused in advance, cause in subcritical district and occur hump phenomenon, make the critical voltage definition difficulty of field-effect transistor.
As shown in Figure 2, the critical voltage at field-effect transistor 1 raceway groove middle part is Vt, transfer characteristic curve, and the relation curve of source-drain current Id and gate source voltage Vgs is from Vt along dotted line, then to A point solid line afterwards.The critical voltage at field-effect transistor 1 trench edges place is Vh, the shorting advance because Vh is less than Vt, thereby make the source-drain current Id of whole field-effect transistor before A point, produce the hump of a little electric current, thereby distortion the transfer characteristic curve of whole field-effect transistor, cover critical voltage Vt when field-effect transistor is normally worked, i.e. the critical voltage Vt at field-effect transistor middle part.Although the curve shown in Fig. 2 has reflected the situation of nmos type field-effect transistor, should be appreciated that this hump phenomenon is not limited to the type of field-effect transistor, no matter be nmos type field-effect transistor, pmos type field-effect transistor all can exist.
As shown in Figure 3, in the time there is On current between the source S of field-effect transistor 1 and drain D, for example, can produce CURRENT DISTRIBUTION as shown by arrows in FIG..Owing to understanding shorting advance near fieldistor channel edge in the time approaching critical voltage, thereby can be than raceway groove middle part current flowing ahead of time, therefore, in the time adopting the TEG feeler switch of prior art as shown in Figure 1 to carry out TEG test, due to the difference of not distinguishing between edge and middle part reliability and the operating characteristic of field-effect transistor, therefore can not fully understand the operating characteristic of semiconductor device, thereby be unfavorable for improving of semiconductor device product quality.
Summary of the invention
In order one of to solve the problems of the technologies described above, the application provides a kind of TEG feeler switch, comprise: field-effect transistor, there is the substrate that is formed with source electrode, grid and drain electrode on it, described source electrode, grid and drain electrode are arranged in order along first direction on the surface of described substrate, and described grid extends along the second direction vertical with described first direction on the surface of described substrate; Control wall, close on described grid at the upwardly extending first end of described second party and the second end, and close on described substrate, and not with described grid and described substrate contact, formed by electric conducting material; Source electrode testing cushion, is connected to described source electrode by conductor; Grid testing cushion, is connected to described grid by conductor; Drain electrode testing cushion, is connected to described drain electrode by conductor; And control pad, be connected to described control wall by conductor, for external control voltage being provided to described control wall.
Wherein, described control wall overlaps with described grid below described grid.
Wherein, described control wall has overlapping with described grid below described grid and not.
Wherein, described electric conducting material is polysilicon.
Wherein, described electric conducting material is metal.
Wherein, the Part I of the first end that closes on described grid of described control wall is connected to described control pad with the Part II of the second end that closes on described grid by conductor.
Wherein, described control wall is around one in described source electrode or described drain electrode and form.
Wherein, described conductor is metal.
Adopt the application's TEG feeler switch, test pack containing as the application's field-effect transistor batch the product performance of semiconductor device or technique while showing, provide external control voltage via control pad to controlling wall, it is bias voltage, affect the conducting situation of fieldistor channel edge by the capacity effect between control wall and fieldistor channel edge, before the voltage that makes to apply at grid reaches the critical voltage at fieldistor channel middle part, the conducting no longer ahead of time of fieldistor channel edge, thereby eliminate the hump effect in field-effect transistor, thereby can obtain the transfer characteristic curve at field-effect transistor middle part, and understood the critical voltage at field-effect transistor middle part, be the critical voltage of field-effect transistor while normally working.Because the application has distinguished the difference between edge and middle part reliability and the operating characteristic of field-effect transistor, therefore can fully understand the operating characteristic of semiconductor device, thereby be conducive to improving of semiconductor device product quality.
Accompanying drawing explanation
The application's embodiment is described below with reference to appended accompanying drawing, wherein:
Fig. 1 illustrates a kind of schematic diagram of TEG feeler switch of the prior art;
Fig. 2 illustrates the schematic diagram of the transfer characteristic that contains hump effect of field-effect transistor in the TEG feeler switch of the prior art shown in Fig. 1;
Fig. 3 illustrates the schematic diagram of the source-drain current distribution of field-effect transistor in the TEG feeler switch of the prior art shown in Fig. 1;
Fig. 4 illustrates according to the schematic diagram of the TEG feeler switch of the application the first embodiment;
Fig. 5 illustrates according to the schematic diagram of the TEG feeler switch of the application the second embodiment;
Fig. 6 illustrates according to the schematic diagram of the TEG feeler switch of the application the 3rd embodiment;
Fig. 7 illustrates according to the schematic diagram of the TEG feeler switch of the application the 4th embodiment; And
Fig. 8 has illustrated according to the elimination of field-effect transistor in the application's TEG feeler switch the schematic diagram of the transfer characteristic of hump effect.
Embodiment
Below in conjunction with Fig. 4 to Fig. 8 DETAILED DESCRIPTION The present application, wherein identical Reference numeral represents same or analogous equipment, material or device.
Fig. 4 illustrates according to the schematic diagram of the TEG feeler switch of the application the first embodiment.For convenience of explanation, intend here to further describe on the basis of the TEG of the prior art shown in Fig. 1 feeler switch shown in Fig. 4 according to the TEG feeler switch of the application the first embodiment.
As shown in Figure 4, the TEG feeler switch of the application the first embodiment comprises: field-effect transistor 1, there is the substrate 10 that is formed with source S, grid G and drain D on it, described source S, grid G and drain D are arranged in order along first direction (being the channel direction of field-effect transistor 1) a-a on the surface of described substrate 10, and described grid G is extended along second direction (be the Width of the field-effect transistor 1) b-b vertical with described first direction on the surface of described substrate 10; Control wall 3, have and close on respectively the Part I C1 of the first end G1 that described grid G extends on described second direction b-b and close on the second end G2 Part II C2 that described grid G is extended on described second direction b-b, and Part I C1 and Part II C2 close on described substrate 10, and do not contact with described substrate 10 with described grid G, wherein said control wall 3 is formed by electric conducting material; Source electrode testing cushion Ps, is connected to described source S by conductor M; Grid testing cushion Pg, is connected to described grid G by conductor M; Drain electrode testing cushion Pd, is connected to described drain D by conductor M; And control pad Pc, be connected to Part I C1 and the Part II C2 of described control wall 3 by conductor M, for external control voltage (not shown) is provided to described control wall 3.
In Fig. 4, control the Part I C1 of wall 3 and Part II C2 and be positioned at the below of grid G, and control the Part I C1 of wall 3 and Part II C2 and overlap with grid G respectively below grid G.
In the present embodiment, test pack containing as the field-effect transistor 1 in Fig. 4 batch the product performance of semiconductor device or technique while showing, except passing through source electrode testing cushion Ps, grid testing cushion Pg and drain electrode testing cushion Pd are applied to test signal the source S of field-effect transistor 1, outside grid G and drain D, also provide external control voltage via control pad Pc to controlling wall 3, it is bias voltage, affect the conducting situation at field-effect transistor 1 trench edges place by the capacity effect between control wall 3 and field-effect transistor 1 trench edges place, before the voltage that makes to apply in grid G reaches the critical voltage Vt at field-effect transistor 1 raceway groove middle part, the conducting no longer ahead of time of field-effect transistor 1 trench edges place, thereby eliminate the hump effect in field-effect transistor 1, thereby can obtain the transfer characteristic curve at field-effect transistor 1 middle part, and understood the critical voltage Vt at field-effect transistor 1 middle part, critical voltage Vt while being field-effect transistor 1 normal work.
Should be appreciated that it is nmos type that field-effect transistor in the present embodiment is not limited to, or pmos type.
In the time adopting as shown in Figure 4 the application's TEG feeler switch to carry out TEG test, due to the difference of having distinguished between edge and middle part reliability and the operating characteristic of field-effect transistor 1, therefore can fully understand the operating characteristic of semiconductor device, thereby be conducive to improving of semiconductor device product quality.
In TEG feeler switch in this embodiment and following examples of the application, the electric conducting material that is used to form control wall 3 can be polysilicon or metal, and conductor M can be metal.
In order to understand better the application, Fig. 5 illustrates according to the schematic diagram of the TEG feeler switch of the application the second embodiment.The difference of the TEG feeler switch of the application the first embodiment shown in TEG feeler switch and the Fig. 4 of the application the second embodiment shown in Fig. 5 is, the Part I C1 of the control wall 30 in Fig. 5 and Part II C2, below grid G, and do not have overlapping with grid G.Although the control wall 30 in Fig. 5 is not overlapping with grid G, owing to controlling Part I C1 and all two ends G1 and G2 of close grid G of Part II C2 of wall 30, also the edge of the raceway groove of close field-effect transistor 1, therefore, still can affect the conducting situation at field-effect transistor 1 trench edges place by the capacity effect of controlling between wall 30 and field-effect transistor 1 trench edges place, thereby obtain the effect of similarly eliminating the hump effect of field-effect transistor 1 with the application the first embodiment.
In order to understand better the application, Fig. 6 illustrates according to the schematic diagram of the TEG feeler switch of the application the 3rd embodiment.The difference of the TEG feeler switch of the application the first embodiment shown in TEG feeler switch and Fig. 4 of the 3rd embodiment of the application shown in Fig. 6 is, control wall 300 in Fig. 6 forms around one in source electrode D or source S, and the Part I C1 and the Part II C2 that control wall 300 overlap with two ends G1 and the G2 of grid G respectively below grid G.Owing to controlling Part I C1 and all two ends G1 and G2 of close grid G of Part II C2 of wall 300, also the edge of the raceway groove of close field-effect transistor 1, therefore, still can affect the conducting situation at field-effect transistor 1 trench edges place by the capacity effect of controlling between wall 300 and field-effect transistor 1 trench edges place, thereby obtain the effect of similarly eliminating the hump effect of field-effect transistor 1 with the application the first embodiment.
In order to understand better the application, Fig. 7 illustrates according to the schematic diagram of the TEG feeler switch of the application the 4th embodiment.The difference of the TEG feeler switch of the application the second embodiment shown in TEG feeler switch and Fig. 5 of the 4th embodiment of the application shown in Fig. 6 is, control wall 3000 in Fig. 7 is around one in source electrode D or source S and form, and do not have overlapping with grid G below grid G.Owing to controlling Part I C1 and all two ends G1 and G2 of close grid G of Part II C2 of wall 3000, also the edge of the raceway groove of close field-effect transistor 1, therefore, still can affect the conducting situation at field-effect transistor 1 trench edges place by the capacity effect of controlling between wall 3000 and field-effect transistor 1 trench edges place, thereby obtain the effect of similarly eliminating the hump effect of field-effect transistor 1 with the application the first embodiment.
Fig. 8 has illustrated according to the elimination of field-effect transistor in the application's TEG feeler switch the schematic diagram of the transfer characteristic of hump effect.As shown in Figure 8, owing to having eliminated hump effect, the transfer characteristic curve of field-effect transistor entirety can be basically identical with the transfer characteristic curve at field-effect transistor middle part, clearly demonstrated the critical voltage Vt at field-effect transistor middle part, and source-drain current Id presented good linear relationship with Vgs before saturated.
Adopt the application's TEG feeler switch, test pack containing as the application's field-effect transistor batch the product performance of semiconductor device or technique while showing, provide external control voltage via control pad to controlling wall, it is bias voltage, affect the conducting situation of fieldistor channel edge by the capacity effect between control wall and fieldistor channel edge, before the voltage that makes to apply at grid reaches the critical voltage at fieldistor channel middle part, the conducting no longer ahead of time of fieldistor channel edge, thereby eliminate the hump effect in field-effect transistor, thereby can obtain the transfer characteristic curve at field-effect transistor middle part, and understood the critical voltage at field-effect transistor middle part, be the critical voltage of field-effect transistor while normally working.Because the application has distinguished the difference between edge and middle part reliability and the operating characteristic of field-effect transistor, therefore can fully understand the operating characteristic of semiconductor device, thereby be conducive to improving of semiconductor device product quality.
Although described the application with reference to exemplary embodiments, should be appreciated that term used is explanation and exemplary and nonrestrictive term.Because the application can specifically implement in a variety of forms, so be to be understood that, above-described embodiment is not limited to any aforesaid details, and should explain widely enclosing in claim limited range, therefore fall into whole variations in claim or its equivalency range and remodeling and all should be the claim of enclosing and contain.
Claims (8)
1. a TEG feeler switch, comprising:
Field-effect transistor, there is the substrate that is formed with source electrode, grid and drain electrode on it, described source electrode, grid and drain electrode are arranged in order along first direction on the surface of described substrate, and described grid extends along the second direction vertical with described first direction on the surface of described substrate;
Control wall, close on described grid at the upwardly extending first end of described second party and the second end, and close on described substrate, and not with described grid and described substrate contact, formed by electric conducting material;
Source electrode testing cushion, is connected to described source electrode by conductor;
Grid testing cushion, is connected to described grid by conductor;
Drain electrode testing cushion, is connected to described drain electrode by conductor; And
Control pad, is connected to described control wall by conductor, for external control voltage being provided to described control wall.
2. TEG feeler switch according to claim 1, wherein,
Described control wall overlaps with described grid below described grid.
3. TEG feeler switch according to claim 1, wherein,
Described control wall has overlapping with described grid below described grid and not.
4. according to the TEG feeler switch described in any one in claim 1-3, wherein,
Described electric conducting material is polysilicon.
5. according to the TEG feeler switch described in any one in claim 1-3, wherein,
Described electric conducting material is metal.
6. according to the TEG feeler switch described in any one in claim 1-5, wherein, the Part I of the first end that closes on described grid of described control wall is connected to described control pad with the Part II of the second end that closes on described grid by conductor.
7. according to the TEG feeler switch described in any one in claim 1-5, wherein, described control wall is around one in described source electrode or described drain electrode and form.
8. according to the TEG feeler switch described in claim 1-7, wherein,
Described conductor is metal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410142677.9A CN103915417B (en) | 2014-04-10 | 2014-04-10 | A kind of test device group's feeler switch |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201410142677.9A CN103915417B (en) | 2014-04-10 | 2014-04-10 | A kind of test device group's feeler switch |
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| CN103915417A true CN103915417A (en) | 2014-07-09 |
| CN103915417B CN103915417B (en) | 2016-08-17 |
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| CN201410142677.9A Active CN103915417B (en) | 2014-04-10 | 2014-04-10 | A kind of test device group's feeler switch |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107957541A (en) * | 2017-11-21 | 2018-04-24 | 华北电力大学 | A kind of power semiconductor modular internal parallel cDNA microarray method and system |
| CN109166507A (en) * | 2018-11-01 | 2019-01-08 | 京东方科技集团股份有限公司 | Testing element group, electrical performance test method, array substrate, display device |
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| US6586765B2 (en) * | 1999-12-20 | 2003-07-01 | Taiwan Semiconductor Manufacturing Company | Wafer-level antenna effect detection pattern for VLSI |
| CN101707209A (en) * | 2009-11-26 | 2010-05-12 | 上海宏力半导体制造有限公司 | Lateral diffusion metal oxide semiconductor transistor structure |
| CN102097475A (en) * | 2009-11-27 | 2011-06-15 | 美格纳半导体有限公司 | Semiconductor device and method for fabricating semiconductor device |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US6033940A (en) * | 1995-05-25 | 2000-03-07 | Sharp Kabushiki Kaisha | Anodization control for forming offset between semiconductor circuit elements |
| US6586765B2 (en) * | 1999-12-20 | 2003-07-01 | Taiwan Semiconductor Manufacturing Company | Wafer-level antenna effect detection pattern for VLSI |
| CN1426098A (en) * | 2001-11-02 | 2003-06-25 | 联华电子股份有限公司 | Test window structure for monitoring self alignment of silicide residue |
| CN101707209A (en) * | 2009-11-26 | 2010-05-12 | 上海宏力半导体制造有限公司 | Lateral diffusion metal oxide semiconductor transistor structure |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107957541A (en) * | 2017-11-21 | 2018-04-24 | 华北电力大学 | A kind of power semiconductor modular internal parallel cDNA microarray method and system |
| CN109166507A (en) * | 2018-11-01 | 2019-01-08 | 京东方科技集团股份有限公司 | Testing element group, electrical performance test method, array substrate, display device |
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| CN103915417B (en) | 2016-08-17 |
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Address after: 201506, No. nine, No. 1568, Jinshan Industrial Zone, Shanghai, Jinshan District Patentee after: Shanghai Hehui optoelectronic Co., Ltd Address before: 201500, building two, building 100, 1, Jinshan Industrial Road, 208, Shanghai, Jinshan District Patentee before: EverDisplay Optronics (Shanghai) Ltd. |