CN107947777B - Reset circuit of optical module, optical module and optical network terminal - Google Patents
Reset circuit of optical module, optical module and optical network terminal Download PDFInfo
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- CN107947777B CN107947777B CN201711156077.8A CN201711156077A CN107947777B CN 107947777 B CN107947777 B CN 107947777B CN 201711156077 A CN201711156077 A CN 201711156077A CN 107947777 B CN107947777 B CN 107947777B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/567—Circuits characterised by the use of more than one type of semiconductor device, e.g. BIMOS, composite devices such as IGBT
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/24—Resetting means
Abstract
The invention discloses a reset circuit of an optical module, the optical module and an optical network terminal, and belongs to the technical field of computers, optical modules, optical network terminals and electronics. The reset circuit of the optical module comprises: the PHY chip comprises a charge and discharge unit and a first switch unit, wherein the charge and discharge process of the charge and discharge unit is controlled by the jump of an in-place signal, the on-off of the first switch unit is controlled by the charge and discharge process of the charge and discharge unit, a control signal is generated through the on-off of the first switch unit, and the low level in the control signal is increased to a high level after the PHY chip is controlled to reset. In addition, an optical module and an optical network terminal are also provided. The reset circuit of the optical module, the optical module and the optical network terminal can simply reset the PHY chip, and the normal work of the PHY chip is not influenced after the PHY chip is reset.
Description
Technical Field
The invention relates to the technical field of computer application, in particular to a reset circuit, an optical module and an optical network terminal.
Background
In practical application, an in-place signal of an optical module is at a high level during initial power-on, and after the optical module completes initialization, the in-place signal jumps to a low level and is output to a PHY chip at a next stage. However, due to hot plugging and signal jumping, the PHY chip may be abnormal in state. Therefore, the PHY chip needs to be reset, so that the PHY chip can normally operate after being reset.
Currently, the reset of the PHY chip is usually realized by increasing MCU read level change or powering back on the PHY chip after directly powering off the PHY chip. However, increasing the MCU leads to a complex circuit structure, and additional software is required for control, which increases the design cost and complexity of the circuit, and the PHY chip is directly powered off and then powered on again, which leads to a complicated operation, and thus the PHY chip cannot be reset easily.
Disclosure of Invention
In order to solve the technical problem that the PHY chip cannot be reset simply in the related technology, the invention provides a reset circuit, an optical module and an optical network terminal.
In a first aspect, a reset circuit is provided, where the reset circuit generates a control signal to perform reset control on a PHY chip connected to an optical module by receiving a transition of an in-place signal in the optical module, and the reset circuit includes: a charge and discharge unit and a first switching unit, wherein,
the charging and discharging process of the charging and discharging unit is controlled by the jump of the in-place signal;
the on-off of the first switch unit is controlled by the charging and discharging process of the charging and discharging unit, and a control signal is generated through the on-off of the first switch unit;
after the PHY chip is controlled to reset by the low level in the control signal, the low level is raised to the high level.
In a second aspect, an optical module or an optical network terminal is provided, which includes the reset circuit according to the first aspect.
The technical scheme provided by the embodiment of the invention can obtain the following beneficial effects:
after receiving an in-place signal of the optical module, the reset circuit controls the charging and discharging processes of the charging and discharging unit in the reset circuit through the jumping of the in-place signal, further controls the on-off of the first switch unit, generates a control signal, controls the PHY chip to reset through the low level in the control signal, and raises the low level in the control signal to the high level after the PHY chip is reset, so that the PHY chip is prevented from being in a reset state all the time, and the control signal of the reset circuit does not influence the normal work of the PHY chip after the PHY chip is reset. Therefore, through the reset circuit, extra software control is not needed to be added in the optical module, or the PHY chip is directly powered off and then powered on again, the PHY chip can be reset simply, conveniently and quickly, and the design cost and the circuit complexity for resetting the PHY chip are greatly reduced while the normal work of the PHY chip is not influenced after the PHY chip is reset.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention.
Fig. 1 is a schematic structural diagram of a reset circuit of a light module according to an exemplary embodiment.
Fig. 2 is a schematic structural diagram of a reset circuit of another optical module according to the embodiment shown in fig. 1.
Fig. 3 is a schematic structural diagram of a reset circuit of another optical module according to the embodiment shown in fig. 1.
Fig. 4 is a schematic structural diagram of a reset circuit of another optical module according to the embodiment shown in fig. 1.
Fig. 5 is a schematic structural diagram of a reset circuit of a light module according to an exemplary embodiment.
Fig. 6 is a waveform diagram of input signals and output signals of the reset circuit.
Wherein the reference numerals are as follows: OP, operational amplifier; r1, a first resistor; r2, a second resistor; r3, third resistor; r4, fourth resistor; r5, fifth resistor; r6, sixth resistor; c1, capacitance; q1, Q2 and a triode.
Detailed Description
Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the invention, as set forth in the claims below.
Fig. 1 is a schematic structural diagram of a reset circuit of an optical module according to an exemplary embodiment, where the reset circuit generates a control signal to perform reset control on a PHY chip connected to the optical module by receiving a transition from a low level to a high level of an in-place signal in the optical module. The reset circuit includes a charge and discharge unit 2 and a first switching unit 1. The charging and discharging process of the charging and discharging unit 2 is controlled by the jump of the in-place signal, the on-off of the first switch unit 1 is controlled by the charging and discharging process of the charging and discharging unit 2, and the control signal is generated by the on-off of the first switch unit 1. The low level in the control signal rises to the high level after the PHY chip is controlled to reset.
After receiving an in-place signal of the optical module, the reset circuit controls the on-off of the first switch unit 1 through the jumping from a low level to a high level of the in-place signal, generates a control signal, controls the PHY chip to reset through the low level in the control signal, and raises the low level in the control signal to the high level after the PHY chip is reset, so that the PHY chip is prevented from being always in a reset state, and the control signal of the reset circuit does not influence the normal work of the PHY chip after the PHY chip is reset. Through the reset circuit, the PHY chip can be reset simply, conveniently and quickly without being powered off directly and then powered on again in the optical module or adding extra software control, and the design cost and the circuit complexity for resetting the PHY chip are greatly reduced while the normal work of the PHY chip is not influenced after the PHY chip is reset.
Fig. 2 is a schematic structural diagram illustrating a reset circuit of a light module according to an exemplary embodiment, where the reset circuit includes a second switch unit 3, a charge and discharge unit 2, and a first switch unit 1. The on-off of the second switch unit 3 is controlled by an on-position signal, and an output signal is generated according to the on-off of the second switch unit to control the charging and discharging unit 2. The charging and discharging unit 2 is controlled by the output signal of the second switch unit 3 to charge and discharge, the on-off of the first switch unit 1 is controlled by the charging and discharging process of the charging and discharging unit 2, and a control signal is generated by the on-off of the first switch unit 1. The low level in the control signal rises to the high level after the PHY chip is controlled to reset.
After receiving the in-place signal of the optical module, the reset circuit controls the charging and discharging process of the charging and discharging unit 2 in the reset circuit through the jumping from the high level to the low level of the in-place signal, further controls the on-off of the first switch unit 1, generates a control signal, controls the PHY chip to reset through the low level in the control signal, and raises the low level in the control signal to the high level after the PHY chip is reset, so that the PHY chip is prevented from being always in a reset state, and the control signal of the reset circuit after the PHY chip is reset does not influence the normal work of the PHY chip. Through the reset circuit, extra software control is not needed to be added in the optical module, or the PHY chip is powered on again after being powered off directly, the PHY chip can be reset simply, conveniently and quickly, and the design cost and the circuit complexity for resetting the PHY chip are greatly reduced while the normal work of the PHY chip is not influenced after the PHY chip is reset.
Optionally, fig. 3 is a reset circuit of another optical module shown in fig. 1 according to a corresponding embodiment, and as shown in fig. 3, the reset circuit further includes a voltage dividing unit 4, where the voltage dividing unit 4 is connected to the charge and discharge unit 2 and is configured to divide an input signal input to the charge and discharge unit 2. The voltage division unit 4 is connected with the charge and discharge unit 2 and is used for dividing the voltage of the in-place signal to obtain a voltage division signal.
Optionally, the voltage dividing unit 4 may further be connected to the second switch unit 3, and is configured to divide the voltage of the in-place signal to obtain a voltage-divided signal.
The voltage division unit 4 divides the in-place signal, so that the input signal input to the second switch unit 3 better meets the circuit requirement, and the switch function of the second switch unit 3 is better realized.
The voltage division unit 4 divides the in-place signal, so that the input range of the in-place signal is larger, and the input requirement of the in-place signal is reduced.
Optionally, fig. 4 is a reset circuit of another optical module shown in fig. 1 according to a corresponding embodiment, and as shown in fig. 4, the reset circuit further includes a voltage stabilizing unit 5, where the voltage stabilizing unit 5 is configured to perform voltage stabilization isolation on an input signal input to the charging and discharging unit 2.
In a specific exemplary embodiment, the voltage stabilizing unit 5 is an operational amplifier. The positive input end of the operational amplifier is used for receiving an input in-place signal; the output end of the operational amplifier is connected with the input end of the second switch unit 3, and the output signal of the operational amplifier is fed back to the negative input end of the operational amplifier. The operational amplifier forms a unit gain buffer structure, so that the input in-place signal is subjected to voltage stabilization isolation.
The in-place signal firstly passes through the operational amplifier, and the operational amplifier has an overlarge input resistance, so that the in-place signal is output to an infinite resistance when being output at the front stage of the in-place signal, and the in-place signal output at the front stage is not influenced by a rear-stage circuit similarly to an open circuit.
In an exemplary embodiment, the second switch unit 3 includes a second switch tube, and the on-bit signal is input from an input end of the second switch tube to control on/off of the second switch tube; the output end of the second switch tube is connected with the charge and discharge unit 2 so as to generate an output signal according to the on-off of the second switch tube to control the charge and discharge unit 2 to charge and discharge.
Optionally, the second switching tube is a transistor Q2, a base of the transistor Q2 is used as an input end of the second switching tube, an emitter is connected to ground, and a collector is used as an output end of the second switching tube.
In an exemplary embodiment, the first switch unit 1 includes a first switch tube, an input end of the first switch tube is connected to the charge and discharge unit 2, so that the on and off of the first switch tube is controlled by the charge and discharge process of the charge and discharge unit 2, and an output end of the first switch tube outputs a control signal.
Optionally, the first switch tube is a transistor Q1, a base of the transistor Q1 is used as an input end of the first switch tube, an emitter of the transistor Q1 is connected to ground, and a collector of the transistor Q1 is used as an output end of the first switch tube.
Fig. 5 is a schematic structural diagram of a reset circuit of a light module according to an exemplary embodiment. As shown in fig. 5, the reset circuit includes a voltage stabilizing unit 5, a voltage dividing unit 4, a second switching unit 3, a charging and discharging unit 2, a first switching unit 1, a third resistor R3, and a sixth resistor R6.
The voltage stabilization unit 5 includes an operational amplifier OP. The positive input end of the operational amplifier OP receives the on-position signal; the negative input end of the operational amplifier OP is connected with the output end to form a unity gain buffer structure, and is connected with the voltage division unit 4.
The voltage dividing unit 4 includes a first resistor R1 and a second resistor R2, the first resistor R1 and the second resistor R2 are sequentially connected in series, the other end of the first resistor R1 is connected with the output end of the operational amplifier OP as the input end of the voltage dividing unit, and the connection point between the first resistor R1 and the second resistor R2 is connected with the input end of the second switch unit 3 as the output end of the voltage dividing unit 4.
The second switch unit 3 is a triode Q2, the base of the triode Q2 is connected with the connection point between the first resistor R1 and the second resistor R2, the emitter of the triode Q2 is connected with the ground, the collector of the triode Q2 is connected with the third resistor R3, and the other end of the third resistor R3 is connected with the power supply.
The charging and discharging unit 2 comprises a capacitor C1, a fourth resistor R4 and a fifth resistor R5 which are sequentially connected in series, the other end of the capacitor C1 is connected with a collector of a triode Q1, the other end of the fifth resistor R5 is connected with the ground, and R5 also plays a role in voltage division.
The first switch unit 1 is a triode Q1, the base of the triode Q1 is connected with the connection point between the fourth resistor R4 and the fifth resistor R5, the emitter of the triode Q1 is connected with the ground, the collector of the triode Q1 is connected with the sixth resistor R6, the other end of the sixth resistor R6 is connected with the power supply, and the connection point between the collector of the triode Q1 and the sixth resistor R6 outputs a control signal.
The working principle of the present invention will be explained with reference to fig. 5.
When the presence signal Absent of the optical module is at a high level, the high level equal to the presence signal Absent is output through the voltage stabilization of the operational amplifier OP, and because the operational amplifier OP has an oversized input resistance, when the preceding stage output of the presence signal is seen, the presence signal is equivalently output to an infinite resistance, which is similar to an open circuit, and the presence signal output by the preceding stage can be ensured not to be influenced by a subsequent stage circuit. Meanwhile, the voltage stabilization is also carried out on the presence signal Absent, so that the influence of clutter in the presence signal Absent on a subsequent circuit is avoided. The high level output by the operational amplifier OP outputs a higher divided voltage signal to the base of the triode Q2 after being divided by the first resistor R1 and the second resistor R2, so that the emitter junction of the triode Q2 is conducted, the collector voltage is low level, the voltage on the left side of the capacitor C1 is lower than the voltage on the right side, at this time, the emitter junction of the triode Q1 is reversely biased and cannot be conducted, and Reset output is high level.
At the moment when the presence signal Absent is switched from the high level to the low level, after the presence signal Absent is subjected to voltage stabilization and voltage division, the base voltage of the triode Q2 is at the low level, the triode Q2 is switched from on to off, and the collector of the triode Q2 is switched from the low level to the high level; the left voltage of the capacitor C1 is higher than the right voltage, the power supply VCC charges the capacitor C1 through the first resistor R3, the current loop flowing through the capacitor is the power supply VCC → R3 → C1 → R4 → R5 → ground GND, and a certain voltage drop is generated at two ends of the fifth resistor R5, so that the emitter junction of the transistor Q1 is biased in the forward direction, the transistor Q1 is turned on, and Reset output is at a low level. When the capacitor C1 is charged, the current path is not present, the voltage drop across the fifth resistor R5 disappears, the transistor Q1 is turned off, and the Reset output goes high.
When the presence signal Absent is kept at a low level, the transistor Q2 is turned off, the collector thereof is at a high level, the capacitor C1 is in a saturation state, no voltage drop exists across the fifth resistor R5, the transistor Q1 is in a cut-off state, and the Reset output is kept at a high level.
At the moment when the bit signal Absent changes from low level to high level, the transistor Q2 changes from off to on, the capacitor C1 discharges in reverse direction, and a short-time reverse voltage is formed across the fifth resistor R5 by the loop of ground GND → R5 → R4 → C1 → Q2 → ground GND, but the transistor Q1 is always in off state, and the Reset output remains at high level.
It can be known from the description of the above operation principle that in the Reset circuit, only when the presence signal Absent of the optical module jumps from the high level to the low level, the Reset output appears at the low level for a short time (the duration of the low level can be adjusted by the size of the capacitor C1, the fourth resistor R4, and the fifth resistor R5), and the Reset output is in the high level state at any other time, so that the PHY chip is Reset, and the low level is raised to the high level after the PHY chip is Reset, which does not affect the normal operation of the PHY chip.
In practical circuit operation, the absence signal may be affected by the back-end circuit, that is, the first resistor R1 and the second resistor R2 may make the absence signal output by the front-end circuit in a pulled-down state for a long time, which affects the overall circuit performance.
Fig. 6 is a waveform diagram of the input signal and the output signal of the Reset circuit, where the vertical axis represents the amplitude of the two signals output by the bit signals Absent and Reset, and the horizontal axis represents time. As can be seen from the waveform diagram, at the moment when the in-place signal Absent changes from a high level to a low level, the Reset output changes to a low level, the PHY chip is Reset, and then the Reset output gradually returns to a high level; when the next in-place signal Absent changes from low level to high level and when the in-place signal Absent is kept at low level, Reset output is uniformly kept at high level, so that the design purpose is achieved, when the in-place signal Absent changes from high level to low level, the PHY chip is Reset by outputting low level, and the PHY chip is restored to high level after being Reset, and the normal work of the PHY chip is not influenced.
In an exemplary embodiment, there is also provided an optical module or an optical network terminal including the reset circuit as described above.
It is to be understood that the invention is not limited to the precise arrangements described above and shown in the drawings, and that various modifications and changes may be effected therein by one skilled in the art without departing from the scope thereof. The scope of the invention is limited only by the appended claims.
Claims (10)
1. A reset circuit of an optical module, the reset circuit generates a control signal to perform reset control on a PHY chip connected with the optical module by receiving a jump of an in-place signal in the optical module, and the reset circuit comprises: a charge and discharge unit, a first switch unit, and a second switch unit, wherein,
at the moment when the on-position signal jumps from a high level to a low level, the second switch unit generates an output signal to control the charge and discharge unit to start charging;
at the moment when the on-position signal jumps from a low level to a high level, the second switch unit generates an output signal to control the charge and discharge unit to start discharging;
the on-off of the first switch unit is controlled by the charging and discharging process of the charging and discharging unit, and a control signal is generated through the on-off of the first switch unit;
after the PHY chip is controlled to reset by the low level in the control signal, the low level is raised to the high level.
2. The reset circuit of claim 1, wherein the second switching unit comprises a second switching tube;
the on-position signal is input from the input end of the second switch tube to control the on-off of the second switch tube;
the output end of the second switch tube is connected with the charge and discharge unit so as to generate an output signal according to the on-off of the second switch tube to control the charge and discharge unit to charge and discharge.
3. The reset circuit according to claim 2, wherein the second switching tube is a transistor, a base of the transistor serves as an input terminal of the second switching tube, an emitter of the transistor is connected to ground, and a collector of the transistor serves as an output terminal of the second switching tube.
4. The reset circuit according to claim 1, wherein the first switching unit comprises a first switching tube;
the input end of the first switch tube is connected with the charge and discharge unit, so that the on-off of the first switch tube is controlled by the charge and discharge process of the charge and discharge unit;
and the output end of the first switching tube outputs the control signal.
5. The reset circuit according to claim 4, wherein the first switching tube is a transistor, a base of the transistor serves as an input terminal of the first switching tube, an emitter of the transistor is connected to ground, and a collector of the transistor serves as an output terminal of the first switching tube.
6. The reset circuit of claim 1, wherein the charge and discharge unit comprises a capacitor and a fourth resistor connected in series, wherein the other end of the capacitor receives the on-bit signal, and the other end of the fourth resistor is connected to the input terminal of the first switch unit.
7. The reset circuit of claim 1, further comprising a voltage stabilizing unit for performing voltage stabilizing isolation on the input signal input to the charging and discharging unit.
8. The reset circuit according to claim 7, wherein the voltage stabilization unit includes an operational amplifier;
the positive input end of the operational amplifier is used for inputting the in-place signal;
the output end of the operational amplifier is connected with the input end of the charging and discharging unit, and the output signal of the operational amplifier is fed back to the negative input end of the operational amplifier.
9. The reset circuit according to claim 1, further comprising a voltage dividing unit for dividing an input signal inputted to the charge and discharge unit.
10. An optical module or optical network terminal, characterized in that it comprises a reset circuit according to any of claims 1-9.
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| CN201711156077.8A CN107947777B (en) | 2017-11-20 | 2017-11-20 | Reset circuit of optical module, optical module and optical network terminal |
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| CN201711156077.8A CN107947777B (en) | 2017-11-20 | 2017-11-20 | Reset circuit of optical module, optical module and optical network terminal |
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| CN107947777B true CN107947777B (en) | 2021-06-22 |
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| CN113630187B (en) * | 2021-07-25 | 2022-06-10 | 苏州浪潮智能科技有限公司 | PHY initialization method, system, equipment and medium |
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| JP2008113207A (en) * | 2006-10-30 | 2008-05-15 | Sumitomo Electric Ind Ltd | Optical data link |
| CN202720690U (en) * | 2012-06-29 | 2013-02-06 | 深圳市金溢科技有限公司 | Electronic tag and reset circuit thereof |
| CN103532541B (en) * | 2013-09-30 | 2017-02-22 | 上海斐讯数据通信技术有限公司 | Light module power supply control method and system |
| CN105656546B (en) * | 2014-11-13 | 2019-04-26 | 中兴通讯股份有限公司 | A kind of the burr filtering method and device of optical signal lossing signal |
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| CN201846323U (en) * | 2010-10-29 | 2011-05-25 | 中兴通讯股份有限公司 | Reset circuit and terminal |
| CN203840362U (en) * | 2014-04-18 | 2014-09-17 | 武汉电信器件有限公司 | Synchronous Ethernet electrical interface module structure |
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