US20130257511A1 - Power good signal generating circuit - Google Patents
Power good signal generating circuit Download PDFInfo
- Publication number
- US20130257511A1 US20130257511A1 US13/656,545 US201213656545A US2013257511A1 US 20130257511 A1 US20130257511 A1 US 20130257511A1 US 201213656545 A US201213656545 A US 201213656545A US 2013257511 A1 US2013257511 A1 US 2013257511A1
- Authority
- US
- United States
- Prior art keywords
- terminal
- electronic switch
- resistor
- transistor
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/28—Supervision thereof, e.g. detecting power-supply failure by out of limits supervision
Definitions
- the present disclosure relates to a signal generating circuit.
- the FIGURE is a circuit diagram of an exemplary embodiment of a signal generating circuit.
- the signal generating circuit outputs a power good signal PWROK.
- the signal generating circuit is set on a motherboard.
- the signal generating circuit processes a signal to be output as a PWROK signal developing gradually from a low level to a high level, and to output a reverse signal (from a high level to a low level) rapidly.
- the signal generating circuit includes resistors R 1 -R 8 , a capacitor C 1 , a diode D 1 , and transistors Q 1 -Q 3 .
- a standby power terminal +5 VSB on the motherboard is grounded through the resistors R 1 and R 2 connected in series.
- a node between the resistors R 1 and R 2 is grounded through the resistor R 3 and the capacitor C 1 connected in series.
- a cathode of the diode D 1 is connected to the node between the resistors R 1 and R 2 .
- An anode of the diode D 1 is connected to a node between the resistor R 3 and the capacitor C 1 .
- the resistors R 1 and R 2 make up a voltage divider circuit.
- Abase of the transistor Q 1 is connected to the node between the resistor R 3 and the capacitor C 1 . An emitter of the transistor Q 1 is grounded. A collector of the transistor Q 1 is connected to the standby power terminal +5 VSB through the resistor R 4 . The collector of the transistor Q 1 is further connected to a base of the transistor Q 2 through the resistor R 5 . An emitter of the transistor Q 2 is grounded. A collector of the transistor Q 2 is connected to a dual power terminal +3V_DUAL on the motherboard through the resistor R 6 . The collector of the transistor Q 2 outputs a signal PWROK as a power good signal.
- a base of the transistor Q 3 is connected to the collector of the transistor Q 1 through the resistor R 7 .
- An emitter of the transistor Q 3 is grounded.
- a collector of the transistor Q 3 is connected to the cathode of the diode D 1 through the resistor R 8 .
- a voltage received by the standby power terminal +5 VSB is increased from 0 volt to 5 volts.
- the voltage received by the standby power terminal +5 VSB is less than 4.3 volts, according to the resistances of the resistors R 1 , R 2 , and R 3 , a voltage at the base of the transistor Q 1 is less than a turn-on voltage of the transistor Q 1 (which is equal to 0.65 volts) such that the transistor Q 1 is turned off.
- the transistors Q 2 and Q 3 are turned on.
- the collector of the transistor Q 2 outputs a low level signal, namely the signal PWROK is at a low level.
- the voltage received by the standby power terminal +5 VSB is 4.7 volts
- the voltage at the base of the transistor Q 1 is 0.65 volts.
- the transistor Q 1 is turned on, and the transistors Q 2 and Q 3 are turned off.
- the collector of the transistor Q 2 outputs a high level signal, that is to say the signal PWROK is then at a high level and has become the power good signal.
- the power good signal PWROK is maintained at a high level.
- the voltage received by the standby power terminal +5 VSB is decreased from 5 volts to 0 volts. As long as the voltage received by the standby power terminal +5 VSB is greater than 4.7 volts, the power good signal PWROK is maintained at a high level.
- the base of the transistor Q 1 is less than 0.65 volts, such that the transistor Q 1 is turned off. At this time, the collector of the transistor Q 1 is at a high level.
- the transistor Q 3 is turned on.
- the transistor Q 2 is turned on, such that the collector of the transistor Q 2 is at a low level. In other words, the high level signal indicating PWROK drops instantly to a low level signal.
- the power good signal PWROK changes over a period of time from a low level to a high level.
- the power good signal PWROK changes suddenly from a high level to a low level signal. In other words, the PWROK signal can be changed from a low level to a high level slowly, and changed from a high level to a low level rapidly.
- the transistors Q 1 -Q 3 function as electronic switches.
Abstract
Description
- 1. Technical Field
- The present disclosure relates to a signal generating circuit.
- 2. Description of Related Art
- In motherboards, the period of time within which signals change needs to be specially designed. For example, a power good signal needs to be changed from a low level to a high level gradually, and changed from a high level to a low level rapidly. It is costly to design and manufacture circuitry to achieve these working parameters.
- Many aspects of the embodiments can be better understood with reference to the following drawing. The components in the drawings are not necessarily drawn to scale, the emphasis instead being placed upon clearly illustrating the principles of the present embodiments.
- The FIGURE is a circuit diagram of an exemplary embodiment of a signal generating circuit.
- The disclosure, including the accompanying drawing, is illustrated by way of examples and not by way of limitation. It should be noted that references to “an” or “one” embodiment in this disclosure are not necessarily to the same embodiment, and such references mean “at least one.”
- Referring to the FIGURE, an exemplary embodiment of the signal generating circuit is illustrated, the signal generating circuit outputs a power good signal PWROK. The signal generating circuit is set on a motherboard. The signal generating circuit processes a signal to be output as a PWROK signal developing gradually from a low level to a high level, and to output a reverse signal (from a high level to a low level) rapidly.
- The signal generating circuit includes resistors R1-R8, a capacitor C1, a diode D1, and transistors Q1-Q3. A standby power terminal +5 VSB on the motherboard is grounded through the resistors R1 and R2 connected in series. A node between the resistors R1 and R2 is grounded through the resistor R3 and the capacitor C1 connected in series. A cathode of the diode D1 is connected to the node between the resistors R1 and R2. An anode of the diode D1 is connected to a node between the resistor R3 and the capacitor C1. The resistors R1 and R2 make up a voltage divider circuit.
- Abase of the transistor Q1 is connected to the node between the resistor R3 and the capacitor C1. An emitter of the transistor Q1 is grounded. A collector of the transistor Q1 is connected to the standby power terminal +5 VSB through the resistor R4. The collector of the transistor Q1 is further connected to a base of the transistor Q2 through the resistor R5. An emitter of the transistor Q2 is grounded. A collector of the transistor Q2 is connected to a dual power terminal +3V_DUAL on the motherboard through the resistor R6. The collector of the transistor Q2 outputs a signal PWROK as a power good signal.
- A base of the transistor Q3 is connected to the collector of the transistor Q1 through the resistor R7. An emitter of the transistor Q3 is grounded. A collector of the transistor Q3 is connected to the cathode of the diode D1 through the resistor R8.
- When an external power supply is connected to the motherboard, a voltage received by the standby power terminal +5 VSB is increased from 0 volt to 5 volts. When the voltage received by the standby power terminal +5 VSB is less than 4.3 volts, according to the resistances of the resistors R1, R2, and R3, a voltage at the base of the transistor Q1 is less than a turn-on voltage of the transistor Q1 (which is equal to 0.65 volts) such that the transistor Q1 is turned off. The transistors Q2 and Q3 are turned on. The collector of the transistor Q2 outputs a low level signal, namely the signal PWROK is at a low level.
- When the voltage received by the standby power terminal +5 VSB is 4.7 volts, the voltage at the base of the transistor Q1 is 0.65 volts. The transistor Q1 is turned on, and the transistors Q2 and Q3 are turned off. The collector of the transistor Q2 outputs a high level signal, that is to say the signal PWROK is then at a high level and has become the power good signal.
- When the voltage received by the standby power terminal +5 VSB is stable, namely the voltage received by the standby power terminal +5 VSB is 4.7 volts to 5 volts, the power good signal PWROK is maintained at a high level.
- When the external power supply is disconnected from the motherboard, the voltage received by the standby power terminal +5 VSB is decreased from 5 volts to 0 volts. As long as the voltage received by the standby power terminal +5 VSB is greater than 4.7 volts, the power good signal PWROK is maintained at a high level. When the voltage being received by the standby power terminal +5 VSB is less than 4.7 volts, the base of the transistor Q1 is less than 0.65 volts, such that the transistor Q1 is turned off. At this time, the collector of the transistor Q1 is at a high level. The transistor Q3 is turned on. The transistor Q2 is turned on, such that the collector of the transistor Q2 is at a low level. In other words, the high level signal indicating PWROK drops instantly to a low level signal.
- From the above description, when the voltage received by the standby power terminal +5 VSB is increased to at least 4.7 volts from 0 volts, the power good signal PWROK changes over a period of time from a low level to a high level. When the voltage received by the standby power terminal +5 VSB is reduced to at least 4.7 volts from 5 volts, the power good signal PWROK changes suddenly from a high level to a low level signal. In other words, the PWROK signal can be changed from a low level to a high level slowly, and changed from a high level to a low level rapidly.
- In the embodiment, the transistors Q1-Q3 function as electronic switches.
- The foregoing description of the exemplary embodiments of the disclosure has been presented only for the purposes of illustration and description and is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. Many modifications and variations are possible. The embodiments were chosen and described in order to explain the principles of the disclosure and their practical application so as to enable others of ordinary skill in the art to utilize the disclosure and various embodiments and with various modifications as are suited to the particular use contemplated. Alternative embodiments will become apparent to those of ordinary skills in the art to which the present disclosure pertains without departing from its spirit and scope. Accordingly, the scope of the present disclosure is defined by the appended claims rather than by the foregoing description and the exemplary embodiments described therein.
Claims (7)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201210083901 | 2012-03-27 | ||
CN201210083901.2 | 2012-03-27 | ||
CN2012100839012A CN103365335A (en) | 2012-03-27 | 2012-03-27 | Signal processing circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
US8536909B1 US8536909B1 (en) | 2013-09-17 |
US20130257511A1 true US20130257511A1 (en) | 2013-10-03 |
Family
ID=49122356
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US13/656,545 Expired - Fee Related US8536909B1 (en) | 2012-03-27 | 2012-10-19 | Power good signal generating circuit |
Country Status (3)
Country | Link |
---|---|
US (1) | US8536909B1 (en) |
CN (1) | CN103365335A (en) |
TW (1) | TW201340608A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20190130855A1 (en) * | 2017-10-26 | 2019-05-02 | HKC Corporation Limited | Display apparatus, and circuit and method for driving display apparatus |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103901998A (en) * | 2012-12-29 | 2014-07-02 | 鸿富锦精密工业(深圳)有限公司 | Power supply sequential circuit |
CN106155179A (en) * | 2015-04-23 | 2016-11-23 | 鸿富锦精密工业(武汉)有限公司 | Noise signal filtering circuit |
CN105212750B (en) * | 2015-11-03 | 2018-07-10 | 佛山市嘉沃农业科技合伙企业(有限合伙) | Effluent control device |
US20170170821A1 (en) * | 2015-12-11 | 2017-06-15 | Freebird Semiconductor Corporation | Voltage detection circuit |
Citations (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3590275A (en) * | 1968-10-11 | 1971-06-29 | Rca Corp | Control circuits |
US3725675A (en) * | 1971-03-29 | 1973-04-03 | Honeywell Inf Systems | Power sequencing control circuit |
US4159431A (en) * | 1977-02-18 | 1979-06-26 | Robert Bosch Gmbh | Electronic switch maintaining a predetermined state independent of supply voltage variation |
US4254347A (en) * | 1978-11-01 | 1981-03-03 | Motorola, Inc. | Power-on reset circuit for monolithic I.C.'s |
US4754166A (en) * | 1982-04-21 | 1988-06-28 | Tokyo Shibaura Denki Kabushiki Kaisha | Reset circuit for integrated injection logic |
US5081625A (en) * | 1988-10-05 | 1992-01-14 | Ford Motor Company | Watchdog circuit for use with a microprocessor |
US5313112A (en) * | 1991-12-23 | 1994-05-17 | Ford Motor Company | Low voltage inhibiting circuit for a microcomputer |
US5442312A (en) * | 1992-09-30 | 1995-08-15 | Siemens Ag | Integrated circuit for generating a reset signal |
US5617048A (en) * | 1994-09-19 | 1997-04-01 | National Semiconductor Corporation | Hysteretic power-up circuit |
US5704038A (en) * | 1994-09-30 | 1997-12-30 | Itt Automotive Electrical Systems, Inc. | Power-on-reset and watchdog circuit and method |
US5852377A (en) * | 1996-11-14 | 1998-12-22 | Thomson Consumer Electronics, Inc. | Reset circuit for ensuring proper reset when used with decaying power supplies |
US6456108B1 (en) * | 1998-09-23 | 2002-09-24 | Robert Bosch Gmbh | Input circuit for an output stage |
US7205808B2 (en) * | 2004-06-28 | 2007-04-17 | Hong Fu Jin Precision Industry (Shenzhen) Co., Ltd. | Power supply switching circuit and method |
US20070096786A1 (en) * | 2005-10-28 | 2007-05-03 | Hon Hai Precision Industry Co., Ltd. | Reset circuit |
US7586346B2 (en) * | 2007-10-19 | 2009-09-08 | Hong Fu Jin Precision Industry (Shenzhen) Co., Ltd. | Power good signal generating circuit |
US7616031B2 (en) * | 2008-01-03 | 2009-11-10 | Universal Scientific Industrial Co., Ltd. | Hard reset and manual reset circuit assembly |
US20100156478A1 (en) * | 2008-12-18 | 2010-06-24 | Hong Fu Jin Precision Industry (Shenzhen)Co., Ltd. | Electronic device and signal generator thereof |
US20100223485A1 (en) * | 2009-03-02 | 2010-09-02 | Hong Fu Jin Precision Industry (Shenzhen)Co., Ltd. | Computer system and operating method thereof |
US8283954B2 (en) * | 2010-10-19 | 2012-10-09 | Hon Hai Precision Industry Co., Ltd. | RSMRST signal output circuit |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN100504801C (en) * | 2004-06-25 | 2009-06-24 | 联想(北京)有限公司 | Method and device for detecting and diagnosing fault of computer hardware |
CN100375054C (en) * | 2004-09-23 | 2008-03-12 | 联想(北京)有限公司 | Monitoring diagnosis device of computer main board failure |
CN101211210A (en) * | 2006-12-27 | 2008-07-02 | 鸿富锦精密工业(深圳)有限公司 | Sequence control circuit |
-
2012
- 2012-03-27 CN CN2012100839012A patent/CN103365335A/en active Pending
- 2012-04-09 TW TW101112430A patent/TW201340608A/en unknown
- 2012-10-19 US US13/656,545 patent/US8536909B1/en not_active Expired - Fee Related
Patent Citations (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3590275A (en) * | 1968-10-11 | 1971-06-29 | Rca Corp | Control circuits |
US3725675A (en) * | 1971-03-29 | 1973-04-03 | Honeywell Inf Systems | Power sequencing control circuit |
US4159431A (en) * | 1977-02-18 | 1979-06-26 | Robert Bosch Gmbh | Electronic switch maintaining a predetermined state independent of supply voltage variation |
US4254347A (en) * | 1978-11-01 | 1981-03-03 | Motorola, Inc. | Power-on reset circuit for monolithic I.C.'s |
US4754166A (en) * | 1982-04-21 | 1988-06-28 | Tokyo Shibaura Denki Kabushiki Kaisha | Reset circuit for integrated injection logic |
US5081625A (en) * | 1988-10-05 | 1992-01-14 | Ford Motor Company | Watchdog circuit for use with a microprocessor |
US5313112A (en) * | 1991-12-23 | 1994-05-17 | Ford Motor Company | Low voltage inhibiting circuit for a microcomputer |
US5442312A (en) * | 1992-09-30 | 1995-08-15 | Siemens Ag | Integrated circuit for generating a reset signal |
US5617048A (en) * | 1994-09-19 | 1997-04-01 | National Semiconductor Corporation | Hysteretic power-up circuit |
US5704038A (en) * | 1994-09-30 | 1997-12-30 | Itt Automotive Electrical Systems, Inc. | Power-on-reset and watchdog circuit and method |
US5852377A (en) * | 1996-11-14 | 1998-12-22 | Thomson Consumer Electronics, Inc. | Reset circuit for ensuring proper reset when used with decaying power supplies |
US6456108B1 (en) * | 1998-09-23 | 2002-09-24 | Robert Bosch Gmbh | Input circuit for an output stage |
US7205808B2 (en) * | 2004-06-28 | 2007-04-17 | Hong Fu Jin Precision Industry (Shenzhen) Co., Ltd. | Power supply switching circuit and method |
US20070096786A1 (en) * | 2005-10-28 | 2007-05-03 | Hon Hai Precision Industry Co., Ltd. | Reset circuit |
US7586346B2 (en) * | 2007-10-19 | 2009-09-08 | Hong Fu Jin Precision Industry (Shenzhen) Co., Ltd. | Power good signal generating circuit |
US7616031B2 (en) * | 2008-01-03 | 2009-11-10 | Universal Scientific Industrial Co., Ltd. | Hard reset and manual reset circuit assembly |
US20100156478A1 (en) * | 2008-12-18 | 2010-06-24 | Hong Fu Jin Precision Industry (Shenzhen)Co., Ltd. | Electronic device and signal generator thereof |
US20100223485A1 (en) * | 2009-03-02 | 2010-09-02 | Hong Fu Jin Precision Industry (Shenzhen)Co., Ltd. | Computer system and operating method thereof |
US8283954B2 (en) * | 2010-10-19 | 2012-10-09 | Hon Hai Precision Industry Co., Ltd. | RSMRST signal output circuit |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20190130855A1 (en) * | 2017-10-26 | 2019-05-02 | HKC Corporation Limited | Display apparatus, and circuit and method for driving display apparatus |
US10431173B2 (en) * | 2017-10-26 | 2019-10-01 | HKC Corporation Limited | Display apparatus, and circuit and method for driving display apparatus |
Also Published As
Publication number | Publication date |
---|---|
US8536909B1 (en) | 2013-09-17 |
TW201340608A (en) | 2013-10-01 |
CN103365335A (en) | 2013-10-23 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US8536909B1 (en) | Power good signal generating circuit | |
US20090102543A1 (en) | Negative voltage generating circuit | |
US9317088B2 (en) | Power on circuit | |
US20120242487A1 (en) | Electronic device with high temperature alarm function | |
US20130017097A1 (en) | Alarm circuit | |
US20140211353A1 (en) | Protection circuit for fan control chip | |
US9356471B2 (en) | Power supply circuit | |
US20150317969A1 (en) | Buzzer circuit | |
US7639063B2 (en) | Circuit for turning on motherboard | |
US20160170457A1 (en) | Power control circuit and electronic device | |
US8767365B2 (en) | Protection circuit | |
US20190019446A1 (en) | Trigger circuit of discharge signals, and display device | |
US20130241521A1 (en) | Voltage stabilizing circuit and electronic device | |
US20130283077A1 (en) | Wake-up circuit and electronic device | |
US20130154722A1 (en) | Voltage-stabilizing circuit | |
US20130127439A1 (en) | Voltage adjustment circuit | |
US20160344179A1 (en) | Inrush current protection circuit | |
CN108111150B (en) | Power-on reset circuit, integrated circuit and EEPROM system | |
US8242816B2 (en) | Restart circuit of server | |
CN103869146A (en) | Battery voltage detection circuit | |
US20120274308A1 (en) | Voltage detection circuit | |
CN108776501B (en) | Multiplexing circuit of LDO and POR | |
US20160164523A1 (en) | Interface supply circuit | |
CN107342757B (en) | Power-on reset circuit based on improved band-gap reference structure | |
US20150036249A1 (en) | Protection circuit for power supply unit |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: HON HAI PRECISION INDUSTRY CO., LTD., TAIWAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:CHEN, CHUN-SHENG;ZOU, HUA;REEL/FRAME:029162/0435 Effective date: 20121008 Owner name: HONG FU JIN PRECISION INDUSTRY (WUHAN) CO., LTD., Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:CHEN, CHUN-SHENG;ZOU, HUA;REEL/FRAME:029162/0435 Effective date: 20121008 |
|
REMI | Maintenance fee reminder mailed | ||
LAPS | Lapse for failure to pay maintenance fees |
Free format text: PATENT EXPIRED FOR FAILURE TO PAY MAINTENANCE FEES (ORIGINAL EVENT CODE: EXP.) |
|
STCH | Information on status: patent discontinuation |
Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362 |
|
FP | Lapsed due to failure to pay maintenance fee |
Effective date: 20170917 |