CN107947768A - Mechanical switch electric pulse anti-shaking method - Google Patents
Mechanical switch electric pulse anti-shaking method Download PDFInfo
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- CN107947768A CN107947768A CN201711134004.9A CN201711134004A CN107947768A CN 107947768 A CN107947768 A CN 107947768A CN 201711134004 A CN201711134004 A CN 201711134004A CN 107947768 A CN107947768 A CN 107947768A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/125—Discriminating pulses
- H03K5/1252—Suppression or limitation of noise or interference
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K21/00—Details of pulse counters or frequency dividers
- H03K21/38—Starting, stopping or resetting the counter
Abstract
A kind of mechanical switch electric pulse anti-shaking method, mechanical switch pulse is sampled by sample clock pulse to obtain mechanical switch impulse sampling value, controlled reversible clip counting unit to carry out plus count to sample clock pulse by mechanical switch impulse sampling value or subtracted counting, the output of reversible clip counting unit is amplitude limit stored counts value；The anti-interference threshold value of amplitude limit stored counts value and setting is judged by ROM memory, the signal for producing control output impulse level state goes putting 1 or setting to 0 for control output pulse.The method can filter out edge trembling interference and Stochastic narrow pulse interference in mechanical switch pulse automatically；Filtering out the effect of impulse disturbances can be adjusted by varying the size of amplitude limit stored counts value upper limit magnitude, or the size of the anti-interference threshold value of change.
Description
Technical field
The present invention relates to impulse circuit field of signal processing, especially a kind of mechanical switch electric pulse anti-shaking method.
Background technology
In digital signal circuit, often require that and acted using mechanical switch such as button, relay, contactor, limit switches
Caused electric pulse.Mechanical switch can be done in closure or disconnection because the shake of contact shakes output pulses generation
Disturb pulse.The working time of consuming CPU is needed when eliminating switch from fluttering using software, wastes system resource significantly.Work as needs
Using circuit for eliminating mechanical switch switch from fluttering pulse influence when, common method is rest-set flip-flop and RC filter circuits.Adopt
During with rest-set flip-flop, it is desirable to which mechanical switch has normally closed switch and normal open switch at the same time, its application is restricted.Filtered using RC
Circuit, when shaking interference is continuous narrow pulse interference, it is necessary to increase time constant filter, influences the quick response energy of circuit
Power；For either mechanical switch impulse circuit there are during continuous narrow pulse interference, RC filter circuits are preceding there are direct current memory effect
The burst pulse in face can influence the filtering of burst pulse below.
The content of the invention
To solve the above-mentioned problems, the present invention provides a kind of mechanical switch electric pulse anti-shaking method, including：
Sample clock pulse samples mechanical switch pulse to obtain mechanical switch impulse sampling value；Reversible clip counting
Unit is in by the control of mechanical switch impulse sampling value level state plus count status either subtracts count status；Reversible amplitude limit
The output of counting unit is amplitude limit stored counts value；The amplitude limit stored counts value is binary count value；The amplitude limit accumulation
The Lower Limit Amplitude of count value is 0, upper limit magnitude N；The N is the integer more than or equal to 2；Amplitude limit is accumulated by ROM memory
Count value whether is more than or equal to N-M (N subtracts M) and whether amplitude limit stored counts value is differentiated less than or equal to M, and produces control
The signal of system output impulse level state removes the level state of control output pulse；The M is anti-interference threshold value, M be more than etc.
In 0 and less than N/2 (N divided by 2) integer.
The anti-interference threshold value M is binary data；The address input of the ROM memory by amplitude limit stored counts value and
Anti-interference bis- parts of threshold value M composition；The signal for controlling output impulse level state of ROM memory generation is the first set signal
With the second set signal, the level state for exporting pulse is controlled by the first set signal and the second set signal；First set is believed
Number and the second set signal exported respectively from two bit data ends of ROM memory.
If the first set signal and the second equal high level of set signal are effectively and respectively by the data output end of ROM memory
D1 and D0 is exported, and the definite method of memory cell content D1 and D0 are in the ROM memory,
1. the anti-interference threshold value M importations in memory unit address determine M；
2. the amplitude limit stored counts value part in memory unit address determines amplitude limit stored counts value；
3. when amplitude limit stored counts value is more than or equal to N-M, D1=1, otherwise, D1=0；When less than or equal to M, D0=1,
Otherwise, D0=0.
If the first set signal and the second equal low level of set signal are effectively and respectively by the data output end of ROM memory
D1 and D0 outputs, in the ROM memory the definite method of memory cell content D1 and D0 either,
(1) the anti-interference threshold value M importations in memory unit address determine M；
(2) the amplitude limit stored counts value part in memory unit address determines amplitude limit stored counts value；
(3) when amplitude limit stored counts value is more than or equal to N-M, D1=0, otherwise, D1=1；When less than or equal to M, D0=0,
Otherwise, D0=1.
Method by the first set signal and the second set signal control output impulse level state is that the first of input puts
Position signal is set to 1 effectively and during the second set invalidating signal, by output pulse；The the first set invalidating signal and second of input are put
When position signal is effective, output pulse is set to 0；When the first set signal and invalid the second set signal of input, arteries and veins is exported
It is constant to rush state.By the method for the first set signal and the second set signal control output impulse level state either, input
The first set signal effectively and during the second set invalidating signal, output pulse is set to 0；First set invalidating signal of input
And second set signal it is effective when, will output pulse be set to 1；The the first set signal and the second set signal of input are invalid
When, output pulse condition is constant.
When reversible clip counting unit is in plus count status and amplitude limit stored counts value are more than or equal to upper limit magnitude N, no
Sample clock pulse is carried out plus is counted；Reversible clip counting unit, which is in, subtracts count status and under amplitude limit stored counts value is equal to
During amplitude limit value 0, sample clock pulse is not carried out to subtract counting.
Reversible clip counting unit is made of the forward-backward counter and amplitude limit and add-subtract control circuit inputted with doubleclocking.
The beneficial effects of the invention are as follows：Edge trembling disturbing pulse in mechanical switch pulse and random can be filtered out automatically
Narrow disturbing pulse；Filtering out the effect of impulse disturbances can either be changed by adjusting the size of amplitude limit stored counts value upper limit magnitude
The size for becoming anti-interference threshold value is adjusted.
Brief description of the drawings
Fig. 1 is mechanical switch impulse circuit and mechanical switch pulse filter circuit embodiments；
Fig. 2 reversible clip counting unit embodiments when being N=6；
Fig. 3 anti-interference threshold value selection unit and ROM memory embodiments when being N=6；
Fig. 4 is output control unit embodiment；
Fig. 5 is oscillator unit embodiment；
Machinery switching pulse filtering circuit anti-jamming effectiveness schematic diagram when Fig. 6 is N=6；
Fig. 7 is mechanical switch impulse circuit embodiment.
Embodiment
Below in conjunction with attached drawing, the invention will be further described.The mechanical switch electric pulse anti-shaking method is by including can
Inverse clip counting unit, anti-interference threshold value selection unit, ROM memory, output control unit, the mechanical switch of oscillator unit
Pulse filter circuit is realized.
It is as shown in Figure 1 mechanical switch impulse circuit and mechanical switch pulse filter circuit embodiments.In Fig. 1, machinery is opened
Close impulse circuit 10 and export mechanical switch pulse P；The input of sampling unit 100 is mechanical switch pulse P1 and sample clock pulse
CP1, output mechanical switch impulse sampling value P1*；The input of reversible clip counting unit 101 is mechanical switch impulse sampling value
P1* and sample clock pulse CP1, exports and distinguishes for amplitude limit stored counts value X1, the upper and lower limit amplitude of amplitude limit stored counts value X1
For N, 0；Anti-interference threshold value selection unit 103 exports anti-interference threshold value M；The input of ROM memory 102 is amplitude limit stored counts value
X1 and anti-interference threshold value M, exports as the first set signal SE1 and the second set signal RE1；The input of output control unit 104
For the first set signal SE1 and the second set signal RE1, the output pulse P2 for mechanical switch pulse filter circuit is exported；Shake
Swing device unit 105 and export sample clock pulse CP1.
In following mechanical switch pulse filter circuit embodiments, N=6.
The embodiment of sampling unit and reversible clip counting unit when Fig. 2 is N=6.Sampling unit is by d type flip flop FF1 groups
Into.In Fig. 2, the CP trigger signals of d type flip flop FF1 are effective for rising edge, and sampling instant is the rising edge of sample clock pulse；
The rising edge of sample clock pulse CP1, d type flip flop FF1 sample mechanical switch pulse P1, are obtained in its in-phase output end Q
Sample clock pulse next time is remained to mechanical switch impulse sampling value P1* and by this mechanical switch impulse sampling value P1*
The rising edge of CP1, sampling obtain new mechanical switch impulse sampling value P1*.Sampling unit can also be in sample clock pulse CP1
Trailing edge mechanical switch pulse P1 is sampled.Mechanical switch impulse sampling value P1* has 2 kinds of shapes of high level and low level
State, i.e. P1* have 1 and 0 this 2 kinds of states, and the reversible clip counting unit of two states control of P1*, which is in, adds count status either
Subtract count status, sample clock pulse CP1 is carried out plus is counted or subtracts counting respectively.In Fig. 2, the high level of P1*, low level
State controls reversible clip counting unit to be in plus count status, subtract count status respectively.The high level, low of P1* can also be made
Level controls reversible clip counting unit to be in subtract count status, plus count status respectively.
In Fig. 2, FC1 is 4 up/down binary counter 74HC193, for the forward-backward counter inputted with doubleclocking；
The clear input MR inputs 0 of FC1, set control signal PL input 1, FC1 and are operated in reversible counting state.NAND gate FA1,
FA2, FA3, FA4 form amplitude limit and add-subtract control circuit, FC1 and amplitude limit and add-subtract control circuit collectively constitutes reversible clip counting
Unit.In Fig. 2,2 kinds of states of P1* control FC1 to carry out plus count or subtract counting by NAND gate FA3, FA4 respectively.Work as P1*
When=1, subtracting to count pulse input end CPD and be equal to 1, CP1 and being connected to FC1's by FA3 plus count pulse for FC1 is made by FA4
Input terminal CPU.FC1 has 4 binary systems output Q3, Q2, Q1, Q0, and upper limit width is may make up using low 3 Q2, Q1, Q0 therein
It is worth the counter for 6, Q2, Q1, Q0 are respectively x13, x12, the x11 for forming amplitude limit stored counts value X1.Counting output x13,
X12, x11 add 1 in the trailing edge of CP1, i.e. during P1*=1, reversible clip counting unit is carried out plus counted.As P1*=0, pass through
FA3 makes FC1's plus counts pulse input end CPU and be equal to 1, CP1 and be connected to subtracting for FC1 by FA4 to count pulse input end CPD,
The trailing edge in CP1 of counting output x13, x12, x11 of FC1 subtracts 1, i.e. during P1*=0, reversible clip counting unit carries out subtracting meter
Number.
In Fig. 2, NAND gate FA1 realizes plus counts amplitude limit control；When x13, x12 are at the same time 1, NAND gate FA1 outputs are low
Level, NAND gate FA3 are blocked, and CP1 can not be by the way that adding for FC1 counts pulse input end CPU without pulse input is counted, in P1*
When=1, trailing edge maintenance output states of the FC1 in sample clock pulse CP1 is constant, and reversible clip counting unit is in upper limit value
Clipping state, counts without adding；X13, x12 include 2 kinds of situations for 1 at the same time, during x13, x12, x11 1,1,0, reversible amplitude limit
The output of counting unit is equal to upper limit magnitude 6；During x13, x12, x11 1,1,1, the output of reversible clip counting unit is equal to 7,
In the state of transfiniting, original state of the situation only when system starts is possible to occur, and reversible clip counting unit is through subtracting
Count after entering normal clip counting section, the state of transfiniting of output will not occur again.NAND gate FA2, which realizes to subtract, counts amplitude limit control
System；When counting output x13, x12, x11 of FC1 are at the same time 0, NAND gate FA2 output low levels, NAND gate FA4 is blocked,
CP1 can not be by the way that FC1's subtracts counting input end CPD without counting pulse input；In P1*=0, FC1 is in sample clock pulse
The trailing edge maintenance output state of CP1 is constant, and reversible clip counting unit is in lower limit clipping state, is counted without subtracting.
When the N of reversible clip counting unit is other numerical value, the NAND gate for carrying out counting amplitude limit control in Fig. 2 can be increased and decreased
Quantity, and the input signal quantity of each NAND gate of increase and decrease are realized.The function of reversible clip counting unit can also use it
His device either circuit is realized, for example, replacing 74HC193 using 74HC192, or uses trigger combination gate circuit
Synchronous reversible counter is formed to realize.
Fig. 3 anti-interference threshold value selection unit and ROM memory embodiments when being N=6.Anti-interference threshold value selection unit is by electricity
Hinder R91, R90 and threshold value selecting switch K91, K90 composition；+ VCC is power supply, and GND is publicly.In Fig. 3, anti-interference threshold
The anti-interference threshold value M of value selecting unit output is made of y11, y10；Since anti-interference threshold value M is nonnegative integer less than N/2, N
When=6, M values among 0,1,2, the i.e. value of y11, y10 can only be 0,0, or 0,1, or 1,0, pass through threshold value
Selecting switch K91, K90 makes choice setting.Anti-interference threshold value selection unit can be by multidigit binary system toggle switch, either
BCD toggle switch, or multiple regular taps add pull-up resistor, or the multiple pull-up resistors and electricity of the output of control 0,1
Short out contact, and other circuits that can export multidigit binary system setting value form.
In Fig. 3, ROM device FR1 composition ROM memories.The function of ROM memory is, when the amplitude limit stored counts of input
When value is more than or equal to N-M, the first set signal of output is effective；When the amplitude limit stored counts value of input is less than or equal to M, output
The second set signal it is effective.Specific method is, anti-interference threshold value M and amplitude limit stored counts value X1 is defeated as address signal
Enter, the first set signal SE1 and the second set signal RE1 are exported as data；ROM memory is anti-interference according to what is currently inputted
Threshold value M, and the size of amplitude limit stored counts value X1, determine RE1 points of the first set signal SE1 and the second set signal of output
It is whether ineffective.
During N=6, it is desirable to which FR1 has 5 bit address to input, i.e. the address input end A4-A0 of FR1 in Fig. 3；It is required that FR1 has 2
Data output end D1, D0 of FR1 in data output end, i.e. Fig. 3.If address input end A2, A1, A0 difference input saturation of FR1
X13, x12, x11 of stored counts value X1, address input end A4, A3 input y11, y10 of anti-interference threshold value M, the number of FR1 respectively
It is respectively the first set signal SE1 and the second set signal RE1 according to output terminal D1, D0, then the content of each address location is shown in FR1
Table 1.
ROM memory memory cell content during table 1N=6
In table 1, N=6, the first set signal SE1 and the second set signal RE1 of D1, D0 output are that high level is effective.
By taking storage unit in ROM memory 01001 as an example, the anti-interference threshold value M parts in memory unit address are 01, therefore the numerical value of M
It is 1；Amplitude limit stored counts value part in memory unit address is 001, therefore amplitude limit stored counts value X1 is 1；Since amplitude limit tires out
Product count value X1 is unsatisfactory for the condition more than or equal to N-M, therefore D1=0；Since amplitude limit stored counts value X1 meets to be less than or equal to M
Condition, therefore D0=1.Again by taking storage unit in ROM memory 10101 as an example, the numerical value of M is 2, amplitude limit stored counts value X1
Equal to 5；Since amplitude limit stored counts value X1 meets the condition more than or equal to N-M, D1=1；Due to amplitude limit stored counts value
X1 is unsatisfactory for the condition less than or equal to M, therefore D0=0.
When anti-interference threshold value M is 0, y11, y10 0,0 of address A4, A3 input, at this time, when amplitude limit stored counts value
When X1 is less than or equal to 0, output RE1 be high level, and otherwise RE1 is low level, in table 1, only address A4-A0 for 00000 when
Meet this condition；When amplitude limit stored counts value X1 is more than or equal to 6, output SE1 is high level, and otherwise SE1 is low level, table 1
In, address A4-A0 meets this condition when being 00110；In addition, transfinite when amplitude limit stored counts value X1 is exported, i.e. when X1 is equal to 7,
Also it is high level to export SE1.
When anti-interference threshold value M is 1, y11, y10 0,1 of address A4, A3 input, at this time, includes the state that transfinites of X1,
When amplitude limit stored counts value X1 is more than or equal to 5, output SE1 is high level, and otherwise SE1 is low level；In table 1, address A4-A0
For 01101,01110,01111 when meet this condition；When amplitude limit stored counts value X1 is less than or equal to 1, output RE1 is high electricity
Flat, otherwise RE1 be low level, in table 1, address A4-A0 for 010000,01001 when meet this condition.
When anti-interference threshold value M is 2, y11, y10 1,0 of address A4, A3 input, at this time, when amplitude limit stored counts value
When X1 is more than or equal to 4, output SE1 is high level, and otherwise SE1 is low level, in table 1, share 10100 in the A4-A0 of address,
10101st, 10110,10111 etc. 4 inputs meet this condition；When amplitude limit stored counts value X1 is less than or equal to 2, output RE1 is
High level, otherwise RE1 is low level, in table 1,10000,10001,10010 etc. 3 inputs is shared in the A4-A0 of address and meet this
Condition.
Under normal circumstances, the M values among 0,1,2.To avoid, when setting M mistimings that M is arranged to 3, to disturb
When threshold value selecting switch K91, K90 in threshold value selection unit is all off, there is unpredictable situation in system, is determining
In ROM memory during memory cell content, it is 0 that M can be arranged to 3 situation as M by mistake, in being either 1 or being 2
One kind be determined.For example, M is arranged to 3 by mistake when, handled as the situation of M=2；To be deposited in ROM memory
Exemplified by storage unit 11010, the anti-interference threshold value M parts in memory unit address are the 2 high of address, therefore the numerical value of M is set to by mistake
3, take M=2；Amplitude limit stored counts value part in memory unit address is low 2 of address, X1 2；Accumulated and counted due to amplitude limit
Numerical value X1 is unsatisfactory for the condition more than or equal to N-M, therefore D1=0；Due to meeting that amplitude limit stored counts value X1 is less than or equal to the bar of M
Part, therefore D0=1.When the mistake facilities for considering M, high 2 of ROM memory include 00,01,10,11 kind of situation when, make altogether
With 32 storage units in ROM memory, include 5 corresponding all units of binary address input.
D1, D0 content of each storage unit storage in table 1 is anti-phase, i.e., when 0 change 1,1 becomes 0, the first set signal of output
SE1 and the second set signal RE1 is that low level is effective.
Each binary digit and each binary digit of amplitude limit stored counts value of anti-interference threshold value M and the two of ROM memory into
Correspondence of the address processed between everybody can use arbitrary one-to-one relationship., can be by M by taking the embodiment of N=6 as an example
Y11, y10 it is corresponding respectively with address input end A1, A0, x13, x12, x11 and address input end A4, A3, A2 of X1 difference one
One corresponds to；Either that y11, y10 of M is corresponding respectively with address input end A1, A0, x11, x12, x13 of X1 and address input
A4, A3, A2 are corresponded respectively at end；Either by y11, x11, x12, y10, x13 and address input end A4, A3, A2, A1, A0
Correspond respectively, etc..Simply still need at this time and the value of M is determined according to binary sequence y11, y10 of input, according to
Binary sequence x13, x12, x11 of input determines the value of X1, and the content of respective memory unit is determined further according to M, X1.
Fig. 4 is output control unit embodiment, and the function of output control unit is realized by rest-set flip-flop.In Fig. 4, or it is non-
Door FO1, FO2 composition rest-set flip-flop, the first set signal SE1 and the second equal high level of set signal RE1 are effective；First set is believed
Number SE1 is the set signal of rest-set flip-flop, and the second set signal RE1 is the reset signal of rest-set flip-flop；Pulse P2 is exported from RS
The in-phase output end output of trigger.When SE1 is effective, RE1 is invalid, the output pulse P2 that will be exported from in-phase output end FO2
It is set to 1；When SE1 is invalid, RE1 is effective, output pulse P2 is set to 0；As SE1 and RE1 invalid, the state of output pulse P2
It is constant.Exporting pulse P2 can also export from reversed-phase output, the i.e. output terminal of nor gate FO1.Output control unit can also
Using the rest-set flip-flop of other forms.
As it can be seen from table 1 since anti-interference threshold value M is nonnegative integer less than N/2, the first set signal SE1 and the
Two set signal RE1 can not possibly at the same time effectively, and therefore, the output of output control unit is not in the uncertain feelings of logic state
Condition.
Fig. 5 is oscillator unit embodiment.In Fig. 5, FO3 is 14 grades of binary string column split/oscillator CD4060, electricity
One end parallel connection of R92, resistance R93, capacitance C91 are hindered, other end is respectively connected to signal input part CK1, the signal of CD4060
Inverse output terminalSignal forward direction output terminal CK0；The reset signal input terminal input signal 0 of CD4060, CD4060 is operated in
Vibration and dividing states；Sample clock pulse CP1 is exported from the Q10 frequency division output terminals of CD4060.In Fig. 5, CP1 can also basis
The frequency of oscillation and the required sample frequency of mechanical switch pulse filter circuit of CD4060, it is defeated from other frequency dividings of CD4060
Outlet exports；The frequency of CP1 can also change by adjusting the value of resistance R93, capacitance C91 to realize.Oscillator unit may be used also
To be realized using other kinds of multivibrator.
Machinery switching pulse filtering circuit anti-jamming effectiveness schematic diagram when Fig. 6 is N=6.If anti-interference threshold value M selections 1, when
When amplitude limit stored counts value X1 is more than or equal to 5, SE1 is effective, and output pulse P2 is set to 1；When amplitude limit stored counts value X1 is less than
During equal to 1, RE1 is effective, and output pulse P2 is set to 0；When amplitude limit stored counts value X1 is more than 1 and is less than 5, SE1 and RE1 are equal
Invalid, output pulse P2 maintains state constant.
Mechanical switch pulse P1 corresponding with 15 sample clock pulse CP1 is given in Fig. 6, to mechanical switch pulse P1
Sampled value P1*, the FC1 controlled by P1* add count pulse CPU and subtract count pulse CPD, the amplitude limit that FC1 is counted to get
Stored counts value X1, and corresponding output pulse P2.The change of amplitude limit stored counts value X1 and output pulse P2 lag behind machine
The change of tool switching pulse sampled value P1*, precisely, is sampled in each CP1 rising edges after each sampled point of P1*
P1* is obtained, the CP1 trailing edges after sampling obtains P1*, amplitude limit stored counts value X1 and corresponding output pulse P2 just change
Become, than the high level spaced time for sampling one CP1 of time lag for obtaining P1*.In analysis below, to the lag time not
Specifically mentioned again and explanation.
Add and count pulse CPU when P1* is less than upper limit amplitude limit value 6 equal to 1 and X1, be the rp state of CP1, be otherwise height
Level；Subtract and count pulse CPD when P1* is more than lower limit amplitude limit value 0 equal to 0 and X1, be the rp state of CP1, be otherwise high electricity
It is flat.Since P1* is to be controlled triggering to produce by CP1 rising edges, when P1* is changed into low level from high level, counting pulse CPU is added to have
There may be the output of sharp cutting edge of a knife or a sword；When P1* is changed into high level from low level, subtracts counting pulse CPD and be possible to produce sharp cutting edge of a knife or a sword output；It is defeated
Go out CPU, CPD signal device output capacitance and circuit board on distribution capacity would generally filter out the point cutting edge of a knife or a sword output, can also people
For ground, parallel connection small capacitances filter out point cutting edge of a knife or a sword output at CPU, CPD signal.Make the d type flip flop FF1 of sampling unit into trailing edges
Triggering, samples to obtain P1*, FC1 is in CP1 trailing edges, the P1* sampled by last CP1 trailing edges in each CP1 trailing edges
Control the amplitude limit stored counts value X1 that counts to get, and corresponding output pulse P2, i.e. amplitude limit stored counts value X1 and accordingly
Output pulse P2 change, the cycle time than one CP1 of time lag that sampling obtains P1*, increased lag time, but at this time
It can avoid adding counting pulse CPU, subtracting the sharp cutting edge of a knife or a sword output of generation on counting pulse CPD.Do not use P1 signals directly, but with sampling
The sampled value P1* of unit output removes FA1, FA2 in control figure 2, is in order to avoid the change between CP1 high periods because of P1 produces
The CPU or CPD signal of mistake, cause the error count of amplitude limit stored counts value X1.
If the 6 P1* sampled values obtained in figure 6 before the sampled point 1 of CP1 are 0, output pulse P2 is 0.In Fig. 6,
There is positive pulse interference in sampled points 2 of the mechanical switch pulse P1 in CP1, causes P1* to obtain interference sample in the sampling of sampled point 2
Value 1；Mechanical switch pulse P1 CP1 sampled point 4 to occurring positive narrow pulse interference random disturbances between sampled point 5, but should
Positive narrow pulse width is less than the sampling period and between 2 sampled point, does not influence the sampled result of P1*, i.e. sampling process certainly
It is dynamic to have filtered out the positive narrow pulse interference；Mechanical switch pulse P1 starts to become 1 from 0 in the sampled point 7 of CP1, becomes during 1 from 0
2 edge tremblings are showed, sampled point 7, the value of sampled point 8 are respectively 1,0, and the 2nd edge trembling therein is also by sampling process
Automatically filter out.In Fig. 6, the sampled value P1* that is obtained in sampled point 1 to the sampled point 15 of Clock pulse CP 1, amplitude limit stored counts value
X1 and output pulse P2 are shown in Table 2.
Sampled value P1*, the amplitude limit stored counts value X1 and output pulse P2 of 2 sampled point 1-15 of table
The situation of sampled point in table 2 is observed, in sampled point 1-9, X1 is effective less than or equal to 1, RE1, and SE1 is invalid, and P2 is set to
For 0；In sampled point 10-12, X1 is more than 1 and less than 5, and SE1, RE1 are invalid, and P2 is maintained 0；It is more than in sampled point 13-15, X1
Effective equal to 5, SE1, RE1 is invalid, and P2 is set to 1.Obviously, until the sampled point 13 of Fig. 6, amplitude limit stored counts value X1 is just met
Condition more than or equal to 5, the first set signal SE1 is effective, and output pulse P2 becomes 1 by 0.Sampled point 3 in table 2, X1 is
Lower Limit Amplitude 0 is reached, CPD is maintained high level, and in sampled point 4-6, P1*=0, X1 also no longer carry out subtracting counting, and X1 is maintained
For Lower Limit Amplitude 0；Sampled point 14 in table 2, X1 have had reached upper limit magnitude 6, and CPU is maintained high level, in sampled point
15, P1*=1, X1 are also no longer carried out plus counted, and X1 is maintained upper limit magnitude 6.
What Fig. 6 was provided is that anti-positive pulse of the mechanical switch pulse filter circuit when mechanical switch pulse P1 is 0 disturbs effect
Fruit, and mechanical switch pulse P1 are changed into 1 condition and process from 0.Mechanical switch pulse filter circuit is in mechanical switch pulse
Anti- negative pulse interference effect when P1 is 1, and mechanical switch pulse P1 are changed into 0 condition and process from 1, with mechanical switch arteries and veins
Rush P1 be 0 when anti-positive pulse interference effect, and mechanical switch pulse P1 be changed into from 01 condition it is identical with process.When being located at
CP1 is 1 to 6 sampled value P1* of mechanical switch pulse P1 before the sampled point 31 of clock CP1, and output pulse P2 is 1,
Sampled value P1*, the amplitude limit stored counts value X1 and output pulse P2 that sampled point 31 to sampled point 45 obtains are shown in Table 3.
Sampled value P1*, the amplitude limit stored counts value X1 and output pulse P2 of 3 sampled point 31-45 of table
The situation of sampled point in table 3 is observed, in sampled point 31-32, X1 is effective more than or equal to 5, SE1, and RE1 is invalid, P2 quilts
It is set to 1；In sampled point 33, X1 is more than 1 and less than 5, and SE1, RE1 are invalid, and P2 is maintained 1；It is more than in sampled point 34-38, X1
Effective equal to 5, SE1, RE1 is invalid, and P2 is set to 1；In sampled point 39-41, X1 is more than 1 and less than 5, and SE1, RE1 are invalid, P2
It is maintained 1；In sampled point 42-45, X1 is effective less than or equal to 1, RE1, and SE1 is invalid, and P2 is set to 0.Sampled point in table 3
43, X1 have had reached Lower Limit Amplitude 0, and CPD is maintained high level, are also no longer subtracted in sampled point 44 and 45, P1*=0, X1
Count, X1 is maintained Lower Limit Amplitude 0.
It is same phase relation between output pulse P2 and mechanical switch pulse P1 in the embodiment of this N=6.If can
The function of inverse clip counting unit is changed to：During P1=1, reversible clip counting unit carries out subtracting counting；During P1=0, reversible amplitude limit
Counting unit is carried out plus counted, then is inverted relationship between output pulse P2 and mechanical switch pulse P1.Either in Fig. 4 will
Output pulse P2 is changed to export from nor gate FO1, then function is changed into, and when SE1 is effective, RE1 is invalid, output pulse P2 is put
For 0；When SE1 is invalid, RE1 is effective, output pulse P2 is set to 1；As SE1 and RE1 invalid, the state of output pulse P2
It is constant；It is at this time inverted relationship between output pulse P2 and mechanical switch pulse P1.If being carried out at the same time above-mentioned modification, export
It is same phase relation between pulse P2 and mechanical switch pulse P1.
By export be same phase relation between pulse P2 and mechanical switch pulse P1 exemplified by, from the work of table 2, table 3 and circuit
Principle is it may be concluded that since reversible clip counting unit has cumulative effect, when the sampled value of mechanical switch pulse P1 exists
When 1 quantity is more than 0 quantity within a period of time, amplitude limit stored counts value X1 can tend to increase, and X1 is more than or equal to N-M simultaneously
Output pulse P2 is set to 1；When 0 quantity is more than 1 quantity to the sampled value of mechanical switch pulse P1 within a period of time,
Amplitude limit stored counts value X1 can tend to reduce, and X1 is less than or equal to M and output pulse P2 is set to 0；The characteristic makes electricity of the invention
The clip counting unit on road has a self-startup ability, and 0 in amplitude limit effect and mechanical switch pulse P1 sampled values P1*, limit can be made
Width counting unit enters normal clip counting section and carries out amplitude limit plus-minus counting.
Since anti-interference threshold value is the integer more than or equal to 0 and less than N/2, the first set signal SE1 and the second set letter
Number RE1 can not possibly at the same time effectively, and therefore, the output of output control unit is not in the uncertain situation of logic state.
By export be same phase relation between pulse P2 and mechanical switch pulse P1 exemplified by be described further.When machinery is opened
Guan pulse, which rushes P1, makes amplitude limit stored counts value X1 be less than or equal to M, after output pulse P2 is set to 0, as long as amplitude limit stored counts value X1 mono-
Directly it is less than M, then 1 will not be changed into by exporting pulse P2；When mechanical switch pulse P1 makes amplitude limit stored counts value X1 be more than or equal to N-M,
After output pulse P2 is set to 1, as long as amplitude limit stored counts value X1 is more than N-M always, then 0 will not be changed into by exporting pulse P2.When P1,
When P2 is low level, as long as the positive pulse occurred in P1 makes continuous appearance in P1 sampled values be more than or equal to N-M for 1
, either, there is value that N-M+1 are 1, etc. in continuous N-M+2 P1 sampled values, then can be exported and the P1 from P2 in value
The middle corresponding positive pulse of positive pulse；When P1, P2 are high level, as long as the negative pulse occurred in P1 makes in P1 sampled values
The continuous value for occurring being more than or equal to that N-M are 0, either, occurs N-M+1 for 0 in continuous N-M+2 P1 sampled values
Value, etc., then can export and the corresponding negative pulse of negative pulse in the P1 from P2.When mechanical switch pulse P1 is changed into 1 from 0
Afterwards, output pulse P2 needs amplitude limit stored counts value X1 to add count delay by several sampling pulse cycles, can just make amplitude limit
Stored counts value X1 is more than or equal to N-M, and P2 is put 1；After mechanical switch pulse P1 is changed into 0 from 1, output pulse P2 needs amplitude limit
Stored counts value X1 subtracts count delay by several sampling pulse cycles, amplitude limit stored counts value X1 is less than or equal to M,
P2 is set to 0.When M values are smaller, output pulse P2 becomes 1 and harsher, the anti-jamming effectiveness of circuit from the condition of 1 change 0 from 0
More preferably, but output pulse P2 is bigger relative to the time delay of mechanical switch pulse P1；Conversely, when M values become larger, circuit
Anti-jamming effectiveness is deteriorated, but exports pulse P2 and diminish relative to the time delay of mechanical switch pulse P1.When amplitude limit stored counts
When the upper limit magnitude N values of value X1 become larger, mechanical switch pulse filter circuit will export pulse P2 and become 1 from 0, and become 0 from 1
Condition becomes stringent, and anti-jamming effectiveness improves, but exports pulse P2 and become larger relative to the time delay of mechanical switch pulse P1；Work as N
Value become hour, mechanical switch pulse filter circuit will export pulse P2 and become 1 from 0, and become from 10 condition and broaden, and resist dry
Disturb effect to diminish, but export pulse P2 and diminish relative to the time delay of mechanical switch pulse P1.
The cycle of sample clock pulse and high level width will be according to mechanical switch pulse P1 pulse width, pace of change
Determined with the width of disturbing pulse.Conventional push button switchs, miniature relay switchs for example, if mechanical switch pulse P1 comes from,
The switchettes such as microswitch, limit switch control output, due to switchette formed pulse width at least 100ms,
Shaking interference pulse width is less than 10ms, it is thereby possible to select the cycle of sample clock pulse is 10ms or so, N is in 3 to 7 models
Enclose interior value.
Fig. 7 is the embodiment of mechanical switch impulse circuit, is formed by switching S10 and its pull-up resistor R10, and+VCC is power supply
Power supply, GND are publicly output mechanical switch pulse P1.
Reversible clip counting unit in mechanical switch pulse filter circuit, ROM memory, anti-interference threshold value selection unit,
Whole in output control unit, oscillator unit, or partial function can use PAL, GAL, CPLD, FPGA, or
It is that other programmable logic device, logic unit are realized.
It is the routine techniques that those skilled in the art are grasped in addition to the technical characteristic described in specification.
Claims (8)
- A kind of 1. mechanical switch electric pulse anti-shaking method, it is characterised in that：Sample clock pulse samples mechanical switch pulse to obtain mechanical switch impulse sampling value；Reversible clip counting unit It is in by the control of mechanical switch impulse sampling value level state plus count status either subtracts count status；Reversible clip counting The output of unit is the amplitude limit stored counts value counted to sample clock pulse；The amplitude limit stored counts value is binary system Count value；The Lower Limit Amplitude of the amplitude limit stored counts value is 0, upper limit magnitude N；The N is the integer more than or equal to 2；Whether N-M is more than or equal to amplitude limit stored counts value by ROM memory and whether amplitude limit stored counts value is less than or equal to M Differentiated, and the signal for producing control output impulse level state removes the level state of control output pulse；The M is anti-interference threshold value, and M is the integer more than or equal to 0 and less than N/2.
- 2. mechanical switch electric pulse anti-shaking method according to claim 1, it is characterised in that：The anti-interference threshold value M For binary data；The address input of the ROM memory is made of amplitude limit stored counts value and anti-interference bis- parts of threshold value M； The signal for controlling output impulse level state of ROM memory generation is the first set signal and the second set signal, by first Set signal and the level state of the second set signal control output pulse；First set signal and the second set signal are from ROM Two bit data ends of memory export respectively.
- 3. mechanical switch electric pulse anti-shaking method according to claim 2, it is characterised in that：If the first set signal and The second equal high level of set signal effectively and is respectively exported by the data output end D1 and D0 of ROM memory, the ROM memory The definite method of middle memory cell content D1 and D0 is,1. the anti-interference threshold value M importations in memory unit address determine M；2. the amplitude limit stored counts value part in memory unit address determines amplitude limit stored counts value；3. when amplitude limit stored counts value is more than or equal to N-M, D1=1, otherwise, D1=0；When less than or equal to M, D0=1 is no Then, D0=0.
- 4. mechanical switch electric pulse anti-shaking method according to claim 2, it is characterised in that：If the first set signal and The second equal low level of set signal effectively and is respectively exported by the data output end D1 and D0 of ROM memory, the ROM memory The definite method of middle memory cell content D1 and D0 is,(1) the anti-interference threshold value M importations in memory unit address determine M；(2) the amplitude limit stored counts value part in memory unit address determines amplitude limit stored counts value；(3) when amplitude limit stored counts value is more than or equal to N-M, D1=0, otherwise, D1=1；When less than or equal to M, D0=0 is no Then, D0=1.
- 5. the mechanical switch electric pulse anti-shaking method according to any one of claim 2-4, it is characterised in that：By first The method of set signal and the second set signal control output impulse level state is, the first set signal of input is effectively and the During two set invalidating signals, output pulse is set to 1；When the first set invalidating signal and effective the second set signal of input, Output pulse is set to 0；When the first set signal and invalid the second set signal of input, output pulse condition is constant.
- 6. the mechanical switch electric pulse anti-shaking method according to any one of claim 2-4, it is characterised in that：By first The method of set signal and the second set signal control output impulse level state is, the first set signal of input is effectively and the During two set invalidating signals, output pulse is set to 0；When the first set invalidating signal and effective the second set signal of input, Output pulse is set to 1；When the first set signal and invalid the second set signal of input, output pulse condition is constant.
- 7. the mechanical switch electric pulse anti-shaking method according to any one of claim 1-4, it is characterised in that：Reversible limit When width counting unit is in plus count status and amplitude limit stored counts value are more than or equal to upper limit magnitude N, not to sample clock pulse Carry out plus count；Reversible clip counting unit, which is in, subtracts count status and when amplitude limit stored counts value is equal to Lower Limit Amplitude 0, not right Sample clock pulse carries out subtracting counting.
- 8. the mechanical switch electric pulse anti-shaking method according to any one of claim 1-4, it is characterised in that：Reversible limit Width counting unit is made of the forward-backward counter and amplitude limit and add-subtract control circuit inputted with doubleclocking.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110048697A (en) * | 2019-03-28 | 2019-07-23 | 深圳市创维群欣安防科技股份有限公司 | A kind of method filtering out key jitter and relevant device |
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