CN107979358A - Key pulse de-jittering method - Google Patents
Key pulse de-jittering method Download PDFInfo
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- CN107979358A CN107979358A CN201711134005.3A CN201711134005A CN107979358A CN 107979358 A CN107979358 A CN 107979358A CN 201711134005 A CN201711134005 A CN 201711134005A CN 107979358 A CN107979358 A CN 107979358A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
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Abstract
A kind of key pulse de-jittering method, key pulse is sampled at sample clock pulse edge to obtain key pulse sampled value, controlled reversible clip counting unit to carry out plus count to sample clock pulse respectively by 2 kinds of states of key pulse sampled value or subtracted counting, the output of reversible clip counting unit is amplitude limit stored counts value；According to amplitude limit stored counts value, threshold value and lower limit compare the comparative result of threshold value compared with the upper limit, and control output pulse is put 1 or set to 0.The method can filter out edge trembling interference and Stochastic narrow pulse interference in key pulse automatically；The effect for filtering out impulse disturbances can be by adjusting the size of amplitude limit stored counts value upper limit magnitude or changing that the upper limit compare threshold value, lower limit compares the size of threshold value and is adjusted.
Description
Technical field
The present invention relates to impulse circuit field of signal processing, especially a kind of key pulse de-jittering method.
Background technology
In digital signal circuit, pulse is exported when often requiring that mechanical keyswitch push.Mechanical keyswitch exists
, can be because the shake of contact makes key pulse produce shaking interference pulse when pressing or unclamping.Switch is eliminated using software to tremble
The working time of consuming CPU is needed when dynamic, wastes system resource significantly.When needing to use circuit for eliminating jitter of key switch arteries and veins
During the influence of punching, common method is rest-set flip-flop and RC filter circuits.During using rest-set flip-flop, it is desirable to which key switch has at the same time
There are normally closed switch and normal open switch, its application is restricted.Using RC filter circuits, when shaking interference is done for continuous burst pulse
, it is necessary to increase time constant filter when disturbing, the capability of fast response of circuit is influenced；Either there is continuous narrow arteries and veins in key circuit
During punching interference, for RC filter circuits there are direct current memory effect, burst pulse above can influence the filtering of burst pulse below.
The content of the invention
In order to solve the problem above-mentioned, the present invention provides a kind of key pulse de-jittering method, including：
Key pulse is sampled at sample clock pulse edge to obtain key pulse sampled value；Reversible clip counting list
Member is in by the control of key pulse sampled value level state plus count status either subtracts count status；Reversible clip counting list
The output of member is amplitude limit stored counts value；According to amplitude limit stored counts value, threshold value and lower limit compare the comparison of threshold value compared with the upper limit
As a result, the signal for producing control output impulse level state removes the level state of control output pulse；The amplitude limit stored counts
It is worth for binary count value；The Lower Limit Amplitude of the amplitude limit stored counts value is 0, upper limit magnitude N；The N is more than or equal to 2
Integer.It is the integer more than N/2 (N divided by 2) and less than or equal to N that the upper limit, which compares threshold value,；The lower limit compares threshold value
Integer more than or equal to 0 and less than N/2.
It is described control output impulse level state signal be the first set signal and the second set signal, by the first set
Signal and the level state of the second set signal control output pulse；When amplitude limit stored counts value compares threshold value more than or equal to the upper limit
When, make the first set signal effective, otherwise the first set invalidating signal；When amplitude limit stored counts value compares threshold less than or equal to lower limit
During value, make the second set signal effective, otherwise the second set invalidating signal.
Method by the first set signal and the second set signal control output impulse level state is that the first of input puts
Position signal is set to 1 effectively and during the second set invalidating signal, by output pulse；The the first set invalidating signal and second of input are put
When position signal is effective, output pulse is set to 0；When the first set signal and invalid the second set signal of input, arteries and veins is exported
It is constant to rush state.By the method for the first set signal and the second set signal control output impulse level state either, input
The first set signal effectively and during the second set invalidating signal, output pulse is set to 0；First set invalidating signal of input
And second set signal it is effective when, will output pulse be set to 1；The the first set signal and the second set signal of input are invalid
When, output pulse condition is constant.
When reversible clip counting unit is in plus count status and amplitude limit stored counts value are more than or equal to upper limit magnitude N, no
Sample clock pulse is carried out plus is counted；Reversible clip counting unit, which is in, subtracts count status and under amplitude limit stored counts value is equal to
During amplitude limit value 0, sample clock pulse is not carried out to subtract counting.
Reversible clip counting unit is made of the forward-backward counter and amplitude limit and add-subtract control circuit inputted with doubleclocking.
The beneficial effects of the invention are as follows：The interference of the edge trembling in key pulse can be filtered out automatically and Stochastic narrow pulse is done
Disturb；The effect for filtering out impulse disturbances can be by adjusting the size of amplitude limit stored counts value upper limit magnitude or changing upper limit ratio
The size for comparing threshold value compared with threshold value, lower limit is adjusted.
Brief description of the drawings
Fig. 1 is key pulse filtering circuit embodiment；
Sampling unit and reversible clip counting unit embodiment when Fig. 2 is N=6；
Fig. 3 compares threshold setting unit embodiment when being N=6；
The embodiment of upper limit value comparator unit when Fig. 4 is N=6；
The embodiment of lower limit comparator unit when Fig. 5 is N=6；
Fig. 6 is output control unit embodiment；
Fig. 7 is oscillator unit embodiment；
Key pulse filtering circuit anti-jamming effectiveness schematic diagram when Fig. 8 is N=6；
Fig. 9 is key pulse circuit embodiments.
Embodiment
Below in conjunction with attached drawing, the invention will be further described.The key pulse de-jittering method is filtered by key pulse
Circuit implements.
It is as shown in Figure 1 key pulse filtering circuit embodiment.In Fig. 1,10 output key pulse P1 of key pulse circuit,
Key pulse P1 send to by sampling unit 100, reversible clip counting unit 101, compare threshold setting unit 102, upper limit value ratio
The key pulse formed compared with device unit 103, lower limit comparator unit 104, output control unit 105, oscillator unit 106
Circuit is filtered, key pulse filtering circuit exports the output pulse P2 for eliminating Vibrating pulse.
The input of sampling unit 100 is key pulse P1 and sample clock pulse CP1, output key impulse sampling value P1*；
The input of reversible clip counting unit 101 is key pulse sampled value P1* and sample clock pulse CP1, exports and is accumulated for amplitude limit
Count value X1, the upper and lower limit amplitude of amplitude limit stored counts value X1 is respectively N, 0；The output for comparing threshold setting unit 102 is upper
Limit compares threshold value Y1 and lower limit compares threshold value Y2；The input of upper limit value comparator unit 103 is amplitude limit stored counts value X1 and upper
Limit compares threshold value Y1, exports as the first set signal SE1；The input of lower limit comparator unit 104 is amplitude limit stored counts value
X1 and lower limit compare threshold value Y2, export as the second set signal RE1；The input of output control unit 105 is the first set signal
SE1 and the second set signal RE1, exports the output pulse P2 for key pulse filtering circuit；The output sampling of oscillator unit 106
Clock pulse CP 1.
In following key pulse filtering circuit embodiment, N=6.
The embodiment of sampling unit and reversible clip counting unit when Fig. 2 is N=6.Sampling unit is by d type flip flop FF1 groups
Into.In Fig. 2, the CP trigger signals of d type flip flop FF1 are effective for rising edge, and sampling instant is the rising edge of sample clock pulse；
The rising edge of sample clock pulse CP1, d type flip flop FF1 sample key pulse P1, its in-phase output end Q obtain by
Key pulse sampled value P1* and the rising edge that this key pulse sampled value P1* is remained to sample clock pulse CP1 next time,
Sampling obtains new key pulse sampled value P1*；Key pulse sampled value P1* can also be defeated from the reversed-phase output of d type flip flop
Go out.Key pulse sampled value P1* has 2 kinds of states of high level and low level, i.e. P1* has 1 and 0 this 2 kinds of states, two kinds of shapes of P1*
State controls that reversible clip counting unit is in plus count status either subtracts count status, respectively to sample clock pulse CP1 into
Row plus counting subtract counting.In Fig. 2, high level, the low level state of P1* control respectively reversible clip counting unit be in plus
Count status, subtract count status.The high level of P1*, low level can also be made to control reversible clip counting unit to be in respectively to subtract
Count status plus count status.Sampling unit can also sample key pulse P1 in the trailing edge of sample clock pulse.
In Fig. 2, FC1 is 4 up/down binary counter 74HC193, for the forward-backward counter inputted with doubleclocking；
The clear input MR inputs 0 of FC1, set control signal PL input 1, FC1 and are operated in reversible counting state.NAND gate FA1,
FA2, FA3, FA4 form amplitude limit and add-subtract control circuit, FC1 and amplitude limit and add-subtract control circuit collectively constitutes reversible clip counting
Unit.In Fig. 2,2 kinds of states of P1* control FC1 to carry out plus count or subtract counting by NAND gate FA3, FA4 respectively.Work as P1*
When=1, subtracting to count pulse input end CPD and be equal to 1, CP1 and being connected to FC1's by FA3 plus count pulse for FC1 is made by FA4
Input terminal CPU.FC1 has 4 binary systems output Q3, Q2, Q1, Q0, and upper limit width is may make up using low 3 Q2, Q1, Q0 therein
It is worth the counter for 6, Q2, Q1, Q0 are respectively x13, x12, the x11 for forming amplitude limit stored counts value X1.Counting output x13,
X12, x11 add 1 in the trailing edge of CP1, i.e. during P1*=1, reversible clip counting unit is carried out plus counted.As P1*=0, pass through
FA3 makes FC1's plus counts pulse input end CPU and be equal to 1, CP1 and be connected to subtracting for FC1 by FA4 to count pulse input end CPD,
The trailing edge in CP1 of counting output x13, x12, x11 of FC1 subtracts 1, i.e. during P1*=0, reversible clip counting unit carries out subtracting meter
Number.
In Fig. 2, NAND gate FA1 realizes plus counts amplitude limit control；When x13, x12 are at the same time 1, NAND gate FA1 outputs are low
Level, NAND gate FA3 are blocked, and CP1 can not be by the way that adding for FC1 counts pulse input end CPU without pulse input is counted, in P1*
When=1, trailing edge maintenance output states of the FC1 in sample clock pulse CP1 is constant, and reversible clip counting unit is in upper limit value
Clipping state, counts without adding；X13, x12 include 2 kinds of situations for 1 at the same time, during x13, x12, x11 1,1,0, reversible amplitude limit
The output of counting unit is equal to upper limit magnitude 6；During x13, x12, x11 1,1,1, the output of reversible clip counting unit is equal to 7,
In the state of transfiniting, original state of the situation only when system starts is possible to occur, and reversible clip counting unit is through subtracting
Count after entering normal clip counting section, the state of transfiniting of output will not occur again.NAND gate FA2, which realizes to subtract, counts amplitude limit control
System；When counting output x13, x12, x11 of FC1 are at the same time 0, NAND gate FA2 output low levels, NAND gate FA4 is blocked,
CP1 can not be by the way that FC1's subtracts counting input end CPD without counting pulse input；In P1*=0, FC1 is in sample clock pulse
The trailing edge maintenance output state of CP1 is constant, and reversible clip counting unit is in lower limit clipping state, is counted without subtracting.
When N is other numerical value, can increase and decrease carried out in Fig. 2 count amplitude limit control NAND gate quantity, and increase and decrease respectively with
The input signal quantity of NOT gate is realized.The function of reversible clip counting unit can also using other devices either circuit come
Realize, for example, 74HC193 is replaced using 74HC192, or using trigger and gate circuit composition synchronous reversible counter.
Fig. 3 compares the embodiment of threshold setting unit when being N=6.In Fig. 3 ,+VCC is power supply, GND for publicly,
Resistance R91, R92, R93 and switch K91, K92, K93 composition upper limit compare threshold value Y1 initialization circuits；When K91, K92, K93 distinguish
During in disconnection, closure, off-state, it is 5 to compare the upper limit that threshold setting unit exports and compare threshold value Y1, its 3 binary systems
Export y13, y12, y11 1,0,1.Resistance R94, R95, R96 and switch K94, K95, K96 composition lower limit compare threshold value Y2 settings
Circuit；When K94, K95, K96 are respectively at closure, closure, off-state, the lower limit for comparing threshold setting unit output compares
Threshold value Y2 is 1, its 3 binary system output y23, y22, y21 0,0,1.Comparing threshold setting unit can also be dialled by binary system
Code switch, or BCD toggle switch, or multiple pull-up resistor and short circuit points of the output of control 0,1, and other
The circuit composition of multidigit binary system setting value can be exported.
The function of upper limit value comparator unit is, when the amplitude limit stored counts value of input compares threshold value more than or equal to the upper limit
When, make the first set signal effective, otherwise the first set invalidating signal.The implementation of upper limit value comparator unit when Fig. 4 is N=6
Example, upper limit value comparator unit, the model 74HC85 of FC2 are formed by tetrad numerical value comparator FC2 and OR gate FO1.
The output of 3 binary systems x13, x12, x11 of amplitude limit stored counts value X1 are respectively connected to A2, A1, A0 input terminal of FC2, the upper limit
The output of 3 binary systems y13, y12, the y11 for comparing threshold value Y1 are respectively connected to B2, B1, B0 input terminal of FC2, input terminal A3, B3
Input 0.The input terminal A of FC2>B IN and A<B IN input 0, input terminal A=B IN inputs 1.The output terminals A of FC2>B
OUT, A=B OUT are respectively connected to the input terminal of OR gate FO1, and the output terminal of OR gate FO1 is the first set signal SE1.In Fig. 4
The function that upper limit value comparator unit is realized is, when amplitude limit stored counts value X1 compares threshold value Y1 more than or equal to the upper limit, output
SE1 is high level, and otherwise SE1 is low level.SE1 is effective for high level in Fig. 4；OR gate FO1 is changed to nor gate, then SE1 is
Low level is effective.
The function of lower limit comparator unit is, when the amplitude limit stored counts value of input compares threshold value less than or equal to lower limit
When, make the second set signal effective, otherwise the second set invalidating signal.The implementation of lower limit comparator unit when Fig. 5 is N=6
Example, lower limit comparator unit, the model 74HC85 of FC3 are formed by tetrad numerical value comparator FC3 and OR gate FO2.
The output of 3 binary systems x13, x12, x11 of amplitude limit stored counts value X1 are respectively connected to A2, A1, A0 input terminal of FC3, lower limit
The output of 3 binary systems y23, y22, the y21 for comparing threshold value Y2 are respectively connected to B2, B1, B0 input terminal of FC2, input terminal A3, B3
Connect 0.The input terminal A of FC3>B IN and A<B IN connect 0, and input terminal A=B IN connect 1.The output terminals A of FC3<B OUT, A=B
OUT is respectively connected to the input terminal of OR gate FO2, and the output terminal of OR gate FO2 is the second set signal RE1.Fig. 5 lower limit values compare
The function that device unit is realized is, when amplitude limit stored counts value X1 compares threshold value Y2 less than or equal to lower limit, output RE1 is high electricity
Flat, otherwise SE1 is low level.RE1 is effective for high level in Fig. 5；OR gate FO2 is changed to nor gate, then RE1 has for low level
Effect.
When N values are larger, the 2 or multi-disc 74HC85 more bit binary value comparators of composition can be selected to realize the upper limit
It is worth the function of comparator unit or lower limit comparator unit；1 or multi-disc tetrad numerical value ratio can also be used
Patrolled compared with the function that device CD4063 realizes upper limit value comparator unit or lower limit comparator unit, or using other combinations
Circuit is collected to realize the function of upper limit value comparator unit or lower limit comparator unit.
Fig. 6 is output control unit embodiment.In Fig. 6, rest-set flip-flop is formed by nor gate FO3, FO4 and realizes output control
Elementary Function, the first set signal SE1 and the second equal high level of set signal RE1 are effective；First set signal SE1 triggers for RS
The set signal of device, the second set signal RE1 are the reset signal of rest-set flip-flop；Pulse P2 is exported from the same mutually defeated of rest-set flip-flop
Outlet exports.When SE1 is effective, RE1 is invalid, the output pulse P2 exported from in-phase output end FO4 is set to 1；SE1 is invalid,
When RE1 is effective, output pulse P2 is set to 0；As SE1 and RE1 invalid, the state of output pulse P2 is constant.Export pulse
P2 can also be exported from reversed-phase output from nor gate FO3 output terminals.Output control unit can also use other forms
Rest-set flip-flop.
Fig. 7 is oscillator unit embodiment.In Fig. 7, CMOS NOT gates FN1 and FN2, resistance R97, capacitance C97 composition multi resonants
Oscillator, sample clock pulse CP1 are exported from FN2 output terminals.The frequency of CP1 is come by adjusting the value of resistance R97, capacitance C97
Change.Oscillator unit can also use other kinds of multivibrator.
In the key pulse filtering circuit embodiment of above-mentioned N=6, it is 5 that the upper limit, which compares threshold value Y1 values, and lower limit compares threshold value
Y2 values are 1.When amplitude limit stored counts value X1 is more than or equal to 5, output SE1 is high level, and output pulse P2 is set to 1；When
When amplitude limit stored counts value X1 is less than or equal to 1, output RE1 is high level, and output pulse P2 is set to 0.
Key pulse filtering circuit anti-jamming effectiveness schematic diagram when Fig. 8 is N=6.Given in Fig. 8 and 15 sampling clocks
The corresponding key pulse P1 of pulse CP1, to the sampled value P1* of key pulse P1, the FC1 controlled by P1* adds counting pulse
CPU and subtract and count pulse CPD, the amplitude limit stored counts value X1 that FC1 is counted to get, and corresponding output pulse P2.Amplitude limit tires out
The change of product count value X1 and output pulse P2 lag behind the change of sampled value P1*, after each sampled point of P1*, exactly
Say, be to sample to obtain P1* in each CP1 rising edges, the CP1 trailing edges after sampling obtains P1*, amplitude limit stored counts value X1
And corresponding output pulse P2 just changes, than the high level spaced time for sampling one CP1 of time lag for obtaining P1*.Below
Analysis in, it is no longer specifically mentioned with explanation to the lag time.
Add and count pulse CPU when P1* is less than upper limit amplitude limit value 6 equal to 1 and X1, be the rp state of CP1, be otherwise height
Level；Subtract and count pulse CPD when P1* is more than lower limit amplitude limit value 0 equal to 0 and X1, be the rp state of CP1, be otherwise high electricity
It is flat.Since P1* is to be controlled triggering to produce by CP1 rising edges, when P1* is changed into low level from high level, counting pulse CPU is added to have
There may be the output of sharp cutting edge of a knife or a sword；When P1* is changed into high level from low level, subtracts counting pulse CPD and be possible to produce sharp cutting edge of a knife or a sword output；It is defeated
Go out CPU, CPD signal device output capacitance and circuit board on distribution capacity would generally filter out the point cutting edge of a knife or a sword output, can also people
For ground, parallel connection small capacitances filter out point cutting edge of a knife or a sword output at CPU, CPD signal.Make the d type flip flop FF1 of sampling unit into trailing edges
Triggering, samples to obtain P1*, FC1 is in CP1 trailing edges, the P1* sampled by last CP1 trailing edges in each CP1 trailing edges
Control the amplitude limit stored counts value X1 that counts to get, and corresponding output pulse P2, i.e. amplitude limit stored counts value X1 and accordingly
Output pulse P2 change, the cycle time than one CP1 of time lag that sampling obtains P1*, increased lag time, but at this time
It can avoid adding counting pulse CPU, subtracting the sharp cutting edge of a knife or a sword output of generation on counting pulse CPD.Do not use P1 signals directly, but with sampling
The sampled value P1* of unit output removes FA3, FA4 in control figure 2, is in order to avoid the change between CP1 high periods because of P1 produces
The CPU or CPD signal of mistake, cause the error count of amplitude limit stored counts value X1.
If CP1 is 0 to 6 sampled value P1* of key pulse P1 before the sampled point 1 of CP1 in fig. 8, pulse is exported
P2 is 0.In Fig. 8, key pulse P1, to there is positive pulse interference after sampled point 3, causes X1 adopting before the sampled point 2 of CP1
Sampling point 2, the sampling of sampled point 3 obtain the interference value 1 of P1*；Sampled points 4 of the key pulse P1 in CP1 occurs between sampled point 5
Positive burst pulse random disturbances, but the positive narrow pulse width is less than the sampling period and between 2 sampled points, does not influence sampling knot
Fruit P1*, i.e. sampling process have filtered out the positive narrow pulse interference automatically.Key pulse P1 starts from 0 after the sampled point 6 of CP1
Become 1, become from 0 during 1 and 2 edge tremblings occur, 2nd therein positive burst pulse shaking interference is filtered automatically by sampling process
Remove, sampled point 7, the value of sampled point 8 are respectively 1,0.In Fig. 8, obtained in the sampled point 1 of Clock pulse CP 1 to sampled point 15
Key pulse sampled value P1*, output pulse P2 and amplitude limit stored counts value X1 are shown in Table 1.
Key pulse sampled value P1*, the amplitude limit stored counts value X1 and output pulse P2 of 1 sampled point 1-15 of table
The situation of sampled point in table 1 is observed, is less than or equal to Y2 in sampled point 1-2, X1, RE1 is effective, and SE1 is invalid, and P2 is set to
0；In sampled point 3, X1 is more than Y2 and is less than Y1, and SE1, RE1 are invalid, and P2 is maintained 0；It is less than or equal in sampled point 4-9, X1
Y2, RE1 are effective, and SE1 is invalid, and P2 is set to 0；In sampled point 10-12, X1 is more than Y2 and is less than Y1, and SE1, RE1 are invalid, P2 dimensions
Hold as 0；It is more than or equal to Y1 in sampled point 13-15, X1, SE1 is effective, and RE1 is invalid, and P2 is set to 1.During N=6, reversible clip counting
The counting section of unit is 0-N；Sampled point 5 in table 1, X1 have had reached Lower Limit Amplitude 0, and CPD is maintained high level,
Sampled point 6, P1*=0, X1 also no longer carry out subtracting counting, and X1 is maintained Lower Limit Amplitude 0；In sampled point 14, on X1 has had reached
Amplitude limit value 6, CPU is maintained high level, and in sampled point 15, P1*=1, X1 is also no longer carried out plus counted, and X1 is maintained upper limit magnitude
6。
What Fig. 8 was provided is anti-positive pulse interference effect of the key pulse filtering circuit when key pulse P1 is 0, and is pressed
Key pulse P1 is changed into 1 condition and process from 0.Anti- negative pulse interference of the key pulse filtering circuit when key pulse P1 is 1
Effect, and key pulse P1 are changed into 0 condition and process from 1, with key pulse P1 be 0 when anti-positive pulse interference effect,
And key pulse P1 be changed into from 01 condition it is identical with process.
CP1 is 1 to 6 sampled value P1* of key pulse P1 before being located at the sampled point 31 of Clock pulse CP 1, output
Pulse P2 is 1.Key pulse sampled value P1*, the amplitude limit stored counts value X1 and output arteries and veins that sampled point 31 to sampled point 45 obtains
Rush P2 and be shown in Table 2.
Key pulse sampled value P1*, the amplitude limit stored counts value X1 and output pulse P2 of 2 sampled point 31-45 of table
The situation of sampled point in table 2 is observed, is more than or equal to Y1 in sampled point 31-32, X1, SE1 is effective, and RE1 is invalid, and P2 is put
For 1；In sampled point 33, X1 is more than Y2 and is less than Y1, and SE1, RE1 are invalid, and P2 is maintained 1；In sampled point 34, X1 is more than or equal to
Y1, SE1 are effective, and RE1 is invalid, and P2 is set to 1；In sampled point 35-39, X1 is more than Y2 and is less than Y1, and SE1, RE1 are invalid, P2 dimensions
Hold as 1；Since between sampled point 31-40, sampled value P1* is in more than 01 few states, reversible clip counting unit stored counts
The result is that amplitude limit stored counts value X1 is intended to reduce, to sampled point 40, X1 is less than or equal to Y2, and RE1 is effective, and SE1 is invalid, P2
It is set to 0；In sampled point 41, X1 is more than Y2 and is less than Y1, and SE1, RE1 are invalid, and P2 is maintained 0；It is small in sampled point 42-45, X1
In equal to Y2, RE1 is effective, and SE1 is invalid, and P2 is set to 0.Sampled point 43 in table 2, X1 have had reached Lower Limit Amplitude 0, are adopting
Sampling point 44-45, P1*=0, X1 also no longer carry out subtracting counting, and X1 is maintained Lower Limit Amplitude 0.
It is with related between output pulse P2 and key pulse P1 in the key pulse filtering circuit embodiment of this N=6
System.If the function of reversible clip counting unit is changed to：During P1=1, key pulse sampled value P1* controls reversible clip counting
Unit carries out subtracting counting；During P1=0, key pulse sampled value P1* controls reversible clip counting unit to carry out plus count, then exports
It is inverted relationship between pulse P2 and key pulse P1.Either output pulse P2 is changed in figure 6 defeated from nor gate FO3
Go out, then function is changed into, and when SE1 is effective, RE1 is invalid, output pulse P2 is set to 0；, will when SE1 is invalid, RE1 is effective
Output pulse P2 is set to 1；As SE1 and RE1 invalid, the state of output pulse P2 is constant；Pulse P2 and button are exported at this time
It is inverted relationship between pulse P1.It is same phase between output pulse P2 and key pulse P1 if being carried out at the same time above-mentioned modification
Relation.
By export be same phase relation between pulse P2 and key pulse P1 exemplified by, from the operation principle of table 1, table 2 and circuit
It may be concluded that since reversible clip counting unit has cumulative effect, when the sampled value P1* of key pulse P1 is at one section
Between within 1 quantity be more than 0 quantity when, amplitude limit stored counts value X1 can tend to increase, make X1 be more than or equal to Y1 and will output
Pulse P2 is set to 1；When 0 quantity is more than 1 quantity to the sampled value P1* of key pulse P1 within a period of time, amplitude limit tires out
Product count value X1 can tend to reduce, and X1 is less than or equal to Y2 and output pulse P2 is set to 0；The characteristic makes the limit of circuit of the present invention
Width counting unit has a self-startup ability, 0 in amplitude limit effect and key pulse sampled value P1*, can make clip counting unit into
Enter normal clip counting section and carry out amplitude limit plus-minus counting.When initial amplitude limit stored counts value X1 is more than N, in the shape that transfinites
During state, X1 compares threshold value Y1 more than or equal to the upper limit, and the SE1 of upper limit value comparator unit output is effective, lower limit comparator unit
The invalid of RE1 is exported, P2 is set to 1.
Due to the upper limit compare threshold value Y1 be more than N/2 and less than or equal to N integer, lower limit compare threshold value Y2 be more than or equal to
0 and the integer less than N/2, the first set signal SE1 and the second set signal RE1 can not possibly at the same time effectively, therefore, output control
The output of unit is not in the uncertain situation of logic state.
By export be same phase relation between pulse P2 and key pulse P1 exemplified by be described further.As key pulse P1
Amplitude limit stored counts value X1 is set to compare threshold value Y2 less than or equal to lower limit, after output pulse P2 is set to 0, as long as amplitude limit stored counts value
X1 compares threshold value Y1 less than the upper limit always, then 1 will not be changed into by exporting pulse P2；When key pulse P1 makes amplitude limit stored counts value X1
Compare threshold value Y1 more than or equal to the upper limit, after output pulse P2 is set to 1, as long as amplitude limit stored counts value X1 compares more than lower limit always
Threshold value Y2, then 0 will not be changed into by exporting pulse P2.When P1, P2 are low level, as long as the positive pulse occurred in P1 adopts P1
The continuous value for occurring being more than or equal to that Y1 are 1 in sample value, either, it is 1 to occur Y1+1 in continuous Y1+2 P1 sampled values
Value, etc., then can be exported from P2 and the corresponding positive pulse of positive pulse in the P1；When P1, P2 are high level, as long as
The negative pulse occurred in P1 makes the continuous value for occurring being more than or equal to that N-Y2 are 0 in P1 sampled values, either, in continuous N-Y2
Occur value that N-Y2+1 are 0, etc. in+2 P1 sampled values, then can be exported from P2 corresponding negative with negative pulse in the P1
Pulse.After key pulse P1 is changed into 1 from 0, output pulse P2 needs amplitude limit stored counts value X1 by several sampling pulses week
Phase adds count delay, amplitude limit stored counts value X1 is compared threshold value Y1 more than or equal to the upper limit, P2 is put 1；When button arteries and veins
Rush after P1 is changed into 0 from 1, output pulse P2 needs amplitude limit stored counts value X1 to prolong by the counting that subtracts in several sampling pulse cycles
Late, it amplitude limit stored counts value X1 is compared threshold value Y2 less than or equal to lower limit, P2 is set to 0.When the upper limit compares taking for threshold value Y1
When value is bigger, the condition that output pulse P2 becomes 1 from 0 is harsher, and the anti-positive pulse interference effect of low level of circuit is more preferable；Instantly
The value that limit compares threshold value Y2 is got over hour, and the condition that output pulse P2 becomes 0 from 1 is harsher, the anti-negative pulse of high level of circuit
Interference effect is more preferable.When the value of N becomes larger, key pulse filtering circuit will export pulse P2 and become 1 from 0, and become 0 from 1
Condition becomes stringent, and anti-jamming effectiveness improves, but exports pulse P2 and become larger relative to the time delay of key pulse P1；When taking for N
It is worth and becomes hour, key pulse filtering circuit will exports pulse P2 and become 1 from 0, and broaden from the condition of 1 change 0, and anti-jamming effectiveness becomes
It is small, but export pulse P2 and diminish relative to the time delay of key pulse P1.
The cycle of sample clock pulse and high level width will be according to the pulse width of key pulse P1, paces of change and dry
The width for disturbing pulse determines.For example, if key pulse P1 comes from the control output of conventional push button switch, since conventional push button is opened
The pulse width of the formation of pass at least 100ms, the shaking interference pulse width of conventional push button switch are less than 10ms, therefore, can
To select the cycle of sample clock pulse as 10ms or so, N values in the range of 3 to 7.
Fig. 9 is the embodiment of key pulse circuit, is made of button S10 and its pull-up resistor R10, and+VCC is power supply electricity
Source, GND are publicly output key pulse P1.
Reversible clip counting unit in key pulse filtering circuit, compare threshold setting unit, upper limit value comparator unit,
Whole in lower limit comparator unit, output control unit, oscillator unit, or partial function can use PAL,
GAL, CPLD, FPGA, or other programmable logic device, logic unit are realized.
It is the routine techniques that those skilled in the art are grasped in addition to the technical characteristic described in specification.
Claims (7)
- A kind of 1. key pulse de-jittering method, it is characterised in that：Key pulse is sampled at sample clock pulse edge to obtain key pulse sampled value；Reversible clip counting unit by The control of key pulse sampled value level state is in plus count status either subtracts count status, is exported as to sampling clock arteries and veins Rush in the amplitude limit stored counts value of row counting；Threshold value is compared according to amplitude limit stored counts value and the upper limit and lower limit compares the ratio of threshold value Compared with as a result, the signal for producing control output impulse level state removes the level state of control output pulse；The amplitude limit stored counts value is binary count value；The Lower Limit Amplitude of the amplitude limit stored counts value is 0, upper limit magnitude For N；The N is the integer more than or equal to 2.
- 2. key pulse de-jittering method according to claim 1, it is characterised in that：The upper limit compare threshold value be more than N/2 and the integer less than or equal to N；The lower limit compares threshold value for the integer more than or equal to 0 and less than N/2.
- 3. key pulse de-jittering method according to claim 2, it is characterised in that：The control output impulse level shape The signal of state is the first set signal and the second set signal, by the first set signal and the control output pulse of the second set signal Level state；When amplitude limit stored counts value compares threshold value more than or equal to the upper limit, make the first set signal effective, otherwise first Set invalidating signal；When amplitude limit stored counts value compares threshold value less than or equal to lower limit, make the second set signal effective, otherwise Two set invalidating signals.
- 4. key pulse de-jittering method according to claim 3, it is characterised in that：Put by the first set signal and second The method of position signal control output impulse level state is, the first set signal of input is effectively and the second set invalidating signal When, output pulse is set to 1；When the first set invalidating signal and effective the second set signal of input, output pulse is set to 0；When the first set signal and invalid the second set signal of input, output pulse condition is constant.
- 5. key pulse de-jittering method according to claim 3, it is characterised in that：Put by the first set signal and second The method of position signal control output impulse level state is, the first set signal of input is effectively and the second set invalidating signal When, output pulse is set to 0；When the first set invalidating signal and effective the second set signal of input, output pulse is set to 1；When the first set signal and invalid the second set signal of input, output pulse condition is constant.
- 6. the key pulse de-jittering method according to any one of claim 1-5, it is characterised in that：Reversible clip counting Unit does not add sample clock pulse in when adding count status and amplitude limit stored counts value is more than or equal to upper limit magnitude N Count；Reversible clip counting unit, which is in, subtracts count status and when amplitude limit stored counts value is equal to Lower Limit Amplitude 0, not to sampling when Clock carries out subtracting counting.
- 7. the key pulse de-jittering method according to any one of claim 1-5, it is characterised in that：Reversible clip counting Unit is made of the forward-backward counter and amplitude limit and add-subtract control circuit inputted with doubleclocking.
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| US4667338A (en) * | 1984-06-01 | 1987-05-19 | Sanyo Electric Co., Ltd. | Noise elimination circuit for eliminating noise signals from binary data |
| US4961014A (en) * | 1988-05-26 | 1990-10-02 | Toshiro Kasahara | Filter circuit utilizing reversible counter for generating a satisfactory hysteresis |
| EP1330031A1 (en) * | 2002-01-21 | 2003-07-23 | Mitsubishi Electric Information Technology Centre Europe B.V. | Generation of a sequence of pulse trains |
| CN101568237A (en) * | 2009-05-19 | 2009-10-28 | 中兴通讯股份有限公司 | Method and device for eliminating signal noise |
| CN201388187Y (en) * | 2008-11-26 | 2010-01-20 | 苏州市华芯微电子有限公司 | Circuit of wireless receiving decoding chip for judging burrs |
| CN103647548A (en) * | 2013-11-22 | 2014-03-19 | 简玉君 | Programmable counting circuit for photoelectric encoder |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4667338A (en) * | 1984-06-01 | 1987-05-19 | Sanyo Electric Co., Ltd. | Noise elimination circuit for eliminating noise signals from binary data |
| US4961014A (en) * | 1988-05-26 | 1990-10-02 | Toshiro Kasahara | Filter circuit utilizing reversible counter for generating a satisfactory hysteresis |
| EP1330031A1 (en) * | 2002-01-21 | 2003-07-23 | Mitsubishi Electric Information Technology Centre Europe B.V. | Generation of a sequence of pulse trains |
| CN201388187Y (en) * | 2008-11-26 | 2010-01-20 | 苏州市华芯微电子有限公司 | Circuit of wireless receiving decoding chip for judging burrs |
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Application publication date: 20180501 |