CN107979358A - Key pulse de-jittering method - Google Patents

Abstract

A kind of key pulse de-jittering method, key pulse is sampled at sample clock pulse edge to obtain key pulse sampled value, controlled reversible clip counting unit to carry out plus count to sample clock pulse respectively by 2 kinds of states of key pulse sampled value or subtracted counting, the output of reversible clip counting unit is amplitude limit stored counts value；According to amplitude limit stored counts value, threshold value and lower limit compare the comparative result of threshold value compared with the upper limit, and control output pulse is put 1 or set to 0.The method can filter out edge trembling interference and Stochastic narrow pulse interference in key pulse automatically；The effect for filtering out impulse disturbances can be by adjusting the size of amplitude limit stored counts value upper limit magnitude or changing that the upper limit compare threshold value, lower limit compares the size of threshold value and is adjusted.

Description

Key pulse debounce method

technical field

The invention relates to the field of pulse circuit signal processing, in particular to a key pulse debounce method.

Background technique

In digital signal circuits, it is often required to output pulses when the mechanical key switch is pressed. When the mechanical key switch is pressed or released, the key pulse will generate a jitter interference pulse due to the jitter of the contact. Using software to eliminate switch jitter needs to consume CPU working time, which greatly wastes system resources. When it is necessary to use a circuit to eliminate the influence of the jitter pulse of the key switch, the commonly used methods are RS flip-flop and RC filter circuit. When the RS trigger is used, the key switch is required to have a normally closed switch and a normally open switch at the same time, and its application is limited. When the RC filter circuit is used, when the jitter interference is continuous narrow pulse interference, the filter time constant needs to be increased to affect the rapid response capability of the circuit; or when there is continuous narrow pulse interference in the button circuit, the RC filter circuit has a DC memory effect. The previous narrow pulse will affect the filtering of the following narrow pulse.

Contents of the invention

In order to solve the above problems, the present invention provides a key pulse debounce method, comprising:

On the edge of the sampling clock pulse, the key pulse is sampled to obtain the key pulse sampling value; the reversible limiter counting unit is in the counting up state or the counting down state under the control of the level state of the key pulse sampling value; the output of the reversible limiter counting unit is limited Amplitude cumulative count value; According to the comparison result of the limit cumulative count value and the upper limit comparison threshold and the lower limit comparison threshold, a signal for controlling the output pulse level state is generated to control the level state of the output pulse; the limit limit cumulative count value is binary A count value; the lower limit value of the limiting cumulative count value is 0, and the upper limit value is N; the N is an integer greater than or equal to 2. The upper limit comparison threshold is an integer greater than or equal to N/2 (N divided by 2) and less than or equal to N; the lower limit comparison threshold is an integer greater than or equal to 0 and less than N/2.

The signal for controlling the level state of the output pulse is a first set signal and a second set signal, and the level state of the output pulse is controlled by the first set signal and the second set signal; when the limiting cumulative count value is greater than or equal to When the upper limit comparison threshold is reached, the first set signal is valid, otherwise the first set signal is invalid; when the clipping cumulative count value is less than or equal to the lower limit comparison threshold, the second set signal is valid, otherwise the second set signal is invalid.

The method of controlling the output pulse level state by the first set signal and the second set signal is that when the input first set signal is valid and the second set signal is invalid, the output pulse is set to 1; When the set signal is invalid and the second set signal is valid, the output pulse is set to 0; when both the input first set signal and the second set signal are invalid, the state of the output pulse remains unchanged. The method of controlling the output pulse level state by the first set signal and the second set signal or, when the input first set signal is valid and the second set signal is invalid, the output pulse is set to 0; When the first setting signal is invalid and the second setting signal is valid, the output pulse is set to 1; when both the input first setting signal and the second setting signal are invalid, the state of the output pulse remains unchanged.

When the reversible limiting counting unit is in the counting state and the limiting cumulative counting value is greater than or equal to the upper limit value N, the sampling clock pulse is not counted up; the reversible limiting counting unit is in the counting down state and the limiting cumulative counting value is equal to the lower limiting value When 0, do not count down the sampling clock pulse.

The reversible limiting and counting unit is composed of a reversible counter with double clock input and limiting and adding and subtracting control circuits.

The beneficial effect of the present invention is: can automatically filter out the edge jitter interference and the random narrow pulse interference in key pulse; The lower limit is adjusted by comparing the size of the threshold.

Description of drawings

Fig. 1 is an embodiment of a key pulse filtering circuit;

Fig. 2 is an embodiment of sampling unit and reversible limit counting unit when N=6;

Fig. 3 compares the threshold value setting unit embodiment when N=6;

Fig. 4 is the embodiment of upper limit value comparator unit when N=6;

Fig. 5 is the embodiment of lower limit value comparator unit when N=6;

Fig. 6 is an embodiment of an output control unit;

Fig. 7 is an oscillator unit embodiment;

Figure 8 is a schematic diagram of the anti-interference effect of the key pulse filter circuit when N=6;

FIG. 9 is an embodiment of a key pulse circuit.

Detailed ways

The present invention will be further described below in conjunction with accompanying drawing. The key pulse debounce method is specifically implemented by a key pulse filter circuit.

Figure 1 shows an embodiment of a key pulse filter circuit. In Fig. 1, the key pulse circuit 10 outputs the key pulse P1, and the key pulse P1 is sent to the sampling unit 100, the reversible limit counting unit 101, the comparison threshold setting unit 102, the upper limit comparator unit 103, and the lower limit comparator The key pulse filtering circuit composed of the unit 104 , the output control unit 105 and the oscillator unit 106 , the key pulse filtering circuit outputs the output pulse P2 with the shaking pulse removed.

The input of the sampling unit 100 is the key pulse P1 and the sampling clock pulse CP1, and the output key pulse sampling value P1*; the input of the reversible limiter counting unit 101 is the key pulse sampling value P1* and the sampling clock pulse CP1, and the output is the limiting cumulative counting Value X1, the upper and lower limit amplitude values of the limit cumulative count value X1 are N, 0 respectively; The output of the comparison threshold setting unit 102 is the upper limit comparison threshold Y1 and the lower limit comparison threshold Y2; the input of the upper limit comparator unit 103 is The limited cumulative count value X1 and the upper limit comparison threshold Y1 are output as the first set signal SE1; the input of the lower limit comparator unit 104 is the limited limited cumulative count value X1 and the lower limit comparison threshold Y2, and the output is the second set signal RE1; the input of the output control unit 105 is the first set signal SE1 and the second set signal RE1, and the output is the output pulse P2 of the key pulse filter circuit; the oscillator unit 106 outputs the sampling clock pulse CP1.

In the following key pulse filtering circuit embodiment, N=6.

Fig. 2 is an embodiment of the sampling unit and the reversible clipping and counting unit when N=6. The sampling unit is composed of D flip-flop FF1. In Figure 2, the CP trigger signal of D flip-flop FF1 is valid on the rising edge, and the sampling time is the rising edge of the sampling clock pulse; on the rising edge of the sampling clock pulse CP1, D flip-flop FF1 samples the key pulse P1, and in its in-phase The output terminal Q obtains the key pulse sampling value P1* and holds the key pulse sampling value P1* until the rising edge of the next sampling clock pulse CP1, and obtains a new key pulse sampling value P1* by sampling; the key pulse sampling value P1* also Can be output from the inverting output of the D flip-flop. The key pulse sampling value P1* has two states of high level and low level, that is, P1* has two states of 1 and 0, and the two states of P1* control the reversible limiter counting unit to be in the counting state or counting down state , to count up or down the sampling clock pulse CP1 respectively. In Fig. 2, the high level and low level states of P1* respectively control the reversible limiter counting unit to be in the counting up state and the counting down state. It is also possible to make the high level and low level of P1* respectively control the reversible limiter counting unit to be in the down counting state and the up counting state. The sampling unit can also sample the key pulse P1 at the falling edge of the sampling clock pulse.

In Figure 2, FC1 is a 4-bit binary reversible counter 74HC193, which is a reversible counter with dual clock inputs; FC1's clear input terminal MR inputs 0, and the set control input terminal PL input 1, FC1 works in the reversible counting state. The NAND gates FA1, FA2, FA3 and FA4 form a limiting and addition and subtraction control circuit, and FC1 and the limiting and addition and subtraction control circuit together form a reversible limiting and counting unit. In Fig. 2, the two states of P1* control FC1 to count up or count down through NAND gates FA3 and FA4 respectively. When P1*=1, the down-counting pulse input terminal CPD of FC1 is equal to 1 through FA4, and CP1 is connected to the up-counting pulse input terminal CPU of FC1 through FA3. FC1 has 4-bit binary outputs Q3, Q2, Q1, and Q0. The lower 3 bits of Q2, Q1, and Q0 can be used to form a counter with an upper limit value of 6, and Q2, Q1, and Q0 are respectively composed of the limiting cumulative count value X1. x13, x12, x11. The counting outputs x13, x12, and x11 add 1 at the falling edge of CP1, that is, when P1*=1, the reversible limiter counting unit performs counting up. When P1*=0, the up-counting pulse input terminal CPU of FC1 is equal to 1 through FA3, CP1 is connected to the down-counting pulse input terminal CPD of FC1 through FA4, and the counting outputs x13, x12 and x11 of FC1 decrease at the falling edge of CP1. 1, that is, when P1*=0, the reversible limiter counting unit performs down counting.

In Figure 2, the NAND gate FA1 realizes the up-counting limit control; when x13 and x12 are 1 at the same time, the NAND gate FA1 outputs low level, the NAND gate FA3 is blocked, CP1 cannot pass through, and the up-counting pulse input of FC1 End CPU has no counting pulse input, when P1*=1, FC1 maintains the output state unchanged at the falling edge of sampling clock pulse CP1, and the reversible limiting counting unit is in the upper limit limit state, and does not count up; x13, x12 Simultaneously 1 includes two cases, when x13, x12, x11 are 1, 1, 0, the output of the reversible limiter counting unit is equal to the upper limit value 6; when x13, x12, x11 are 1, 1, 1, the reversible limiter The output of the counting unit is equal to 7, and it is in an over-limit state. This situation may only occur in the initial state when the system is started. Appear. NAND gate FA2 realizes down-counting limit control; when the counting outputs x13, x12, and x11 of FC1 are 0 at the same time, NAND gate FA2 outputs low level, NAND gate FA4 is blocked, CP1 cannot pass, and FC1's down-counting The input terminal CPD has no counting pulse input; when P1*=0, FC1 maintains the output state unchanged at the falling edge of the sampling clock pulse CP1, and the reversible limiter counting unit is in the lower limit limiter state, and does not count down.

When N is other values, it can be realized by increasing or decreasing the number of NAND gates for counting and limiting control in FIG. 2 , and increasing or decreasing the number of input signals of each NAND gate. The function of the reversible limiting counting unit can also be realized by other devices or circuits, for example, 74HC193 is replaced by 74HC192, or a synchronous reversible counter is formed by using flip-flops and gate circuits.

FIG. 3 is an embodiment of the comparison threshold setting unit when N=6. In Fig. 3, +VCC is the power supply, GND is the common ground, resistors R91, R92, R93 and switches K91, K92, K93 form the upper limit comparison threshold Y1 setting circuit; In the off state, the upper limit comparison threshold Y1 output by the comparison threshold setting unit is 5, and its 3-bit binary outputs y13, y12, y11 are 1, 0, 1. Resistors R94, R95, R96 and switches K94, K95, K96 form a lower limit comparison threshold Y2 setting circuit; when K94, K95, K96 are in the closed, closed, and disconnected states respectively, the lower limit comparison threshold Y2 output by the comparison threshold setting unit is 1, its 3-bit binary output y23, y22, y21 is 0, 0, 1. The comparison threshold setting unit can also be composed of a binary dial switch, or a BCD dial switch, or a plurality of pull-up resistors and circuit short contacts for controlling 0, 1 output, and other circuits capable of outputting multi-bit binary set values composition.

The function of the upper limit comparator unit is to enable the first set signal to be valid when the input limiting cumulative count value is greater than or equal to the upper limit comparison threshold, otherwise the first set signal is invalid. Fig. 4 is the embodiment of the upper limit comparator unit when N=6, the upper limit comparator unit is composed of four-bit binary value comparator FC2 and OR gate FO1, the model of FC2 is 74HC85. The 3-bit binary outputs x13, x12, and x11 of the limited cumulative count value X1 are respectively connected to the A2, A1, and A0 input terminals of FC2, and the 3-bit binary outputs y13, y12, and y11 of the upper limit comparison threshold Y1 are respectively connected to B2, y11 of FC2. B1, B0 input terminals, input terminals A3, B3 all input 0. The input terminals A>B IN and A<B IN of FC2 both input 0, and the input terminal A=B IN inputs 1. The output terminals A>BOUT and A=B OUT of FC2 are respectively connected to the input terminals of the OR gate FO1, and the output terminal of the OR gate FO1 is the first set signal SE1. The function realized by the upper limit comparator unit in Fig. 4 is that when the limited cumulative count value X1 is greater than or equal to the upper limit comparison threshold Y1, the output SE1 is high level, otherwise SE1 is low level. In Figure 4, SE1 is active at high level; if the OR gate FO1 is changed to a NOR gate, SE1 is active at low level.

The function of the lower limit comparator unit is to enable the second setting signal to be valid when the input limiting accumulated count value is less than or equal to the lower limit comparison threshold, otherwise the second setting signal is invalid. Figure 5 is an embodiment of the lower limit comparator unit when N=6, the lower limit comparator unit is composed of a four-bit binary value comparator FC3 and an OR gate FO2, and the model of FC3 is 74HC85. The 3-bit binary outputs x13, x12, and x11 of the limited cumulative count value X1 are respectively connected to the A2, A1, and A0 input terminals of FC3, and the 3-bit binary outputs y23, y22, and y21 of the lower limit comparison threshold Y2 are respectively connected to B2, y21 of FC2. B1, B0 input terminals, input terminals A3, B3 are all connected to 0. The input terminals A>B IN and A<B IN of FC3 are both connected to 0, and the input terminal A=B IN is connected to 1. The output terminals A<B OUT and A=BOUT of FC3 are respectively connected to the input terminals of the OR gate FO2, and the output terminal of the OR gate FO2 is the second set signal RE1. The function realized by the lower limit comparator unit in Fig. 5 is that when the limited cumulative count value X1 is less than or equal to the lower limit comparison threshold Y2, the output RE1 is high level, otherwise SE1 is low level. In Figure 5, RE1 is active at high level; if the OR gate FO2 is changed to NOR gate, RE1 is active at low level.

When the value of N is large, you can choose two or more pieces of 74HC85 to form a multi-bit binary value comparator to realize the function of the upper limit comparator unit or the lower limit value comparator unit; you can also use one or more pieces of four-bit binary The numerical comparator CD4063 implements the function of the upper limit comparator unit or the lower limit comparator unit, or uses other combinational logic circuits to realize the function of the upper limit comparator unit or the lower limit comparator unit.

Fig. 6 is an embodiment of an output control unit. In Figure 6, the RS flip-flop is composed of NOR gates FO3 and FO4 to realize the function of the output control unit, the first set signal SE1 and the second set signal RE1 are both active at high level; the first set signal SE1 is an RS flip-flop The set signal, the second set signal RE1 is the reset signal of the RS flip-flop; the output pulse P2 is output from the non-inverting output terminal of the RS flip-flop. When SE1 is valid and RE1 is invalid, the output pulse P2 output from the non-inverting output terminal FO4 is set to 1; when SE1 is invalid and RE1 is valid, the output pulse P2 is set to 0; when both SE1 and RE1 are invalid, the output pulse P2 is The state is unchanged. The output pulse P2 can also be output from the inverting output terminal, that is, the output terminal of the NOR gate FO3. The output control unit can also adopt other forms of RS flip-flops.

Fig. 7 is an embodiment of an oscillator unit. In Fig. 7, CMOS NOT gates FN1 and FN2, resistor R97 and capacitor C97 form a multivibrator, and the sampling clock pulse CP1 is output from the output terminal of FN2. The frequency of CP1 is changed by adjusting the value of resistor R97 and capacitor C97. The oscillator unit can also use other types of multivibrator.

In the above N=6 key pulse filtering circuit embodiment, the upper limit comparison threshold Y1 takes a value of 5, and the lower limit comparison threshold Y2 takes a value of 1. When the limiting cumulative count value X1 is greater than or equal to 5, the output SE1 is high level, and the output pulse P2 is set to 1; when the limiting cumulative count value X1 is less than or equal to 1, the output RE1 is high level, and the output pulse P2 is set to 0.

FIG. 8 is a schematic diagram of the anti-interference effect of the key pulse filter circuit when N=6. Figure 8 shows the key pulse P1 corresponding to 15 sampling clock pulses CP1, the sampling value P1* of the key pulse P1, the FC1 counting pulse CPU and the counting down pulse CPD obtained by the control of P1*, and the FC1 counting obtained Limiting cumulative count value X1, and the corresponding output pulse P2. The change of the limiting cumulative count value X1 and the output pulse P2 lags behind the change of the sampling value P1*. After each sampling point of P1*, to be precise, P1* is obtained by sampling at each rising edge of CP1. After sampling, P1* is obtained. On the falling edge of CP1 after P1*, the limiting cumulative count value X1 and the corresponding output pulse P2 will change, which is one CP1 high-level width time later than the time when P1* is obtained by sampling. In the following analysis, the lag time will not be specifically mentioned or explained.

When the counting pulse CPU is equal to 1 and X1 is less than the upper limit value 6, it is the inversion state of CP1, otherwise it is high level; the counting pulse CPD is equal to 0 when P1* is equal to 0 and X1 is greater than the lower limit value 0. , is the inversion state of CP1, otherwise it is high level. Since P1* is triggered by the rising edge of CP1, when P1* changes from high level to low level, the counting pulse CPU may generate a sharp output; when P1* changes from low level to high level, the decrement The counting pulse CPD may produce a sharp output; the output capacitance of the device that outputs the CPU and CPD signals and the distributed capacitance on the circuit board usually filter out the sharp output, or artificially connect a small capacitor in parallel at the CPU and CPD signals to filter out The spike output. Change the D flip-flop FF1 of the sampling unit to a falling edge trigger, and obtain P1* by sampling on each CP1 falling edge, and FC1 is on the CP1 falling edge, and is controlled by the P1* control count obtained by the last CP1 falling edge sampling. Value X1, and the corresponding output pulse P2, that is, the limited cumulative count value X1 and the corresponding output pulse P2 change, lagging behind the time of sampling P1* by a cycle time of CP1, the lag time is extended, but at this time can avoid The counting pulse CPU and the down counting pulse CPD generate sharp output. Instead of directly using the P1 signal, use the sampling value P1* output by the sampling unit to control FA3 and FA4 in Figure 2, in order to avoid the wrong CPU or CPD signal due to the change of P1 during the high level period of CP1, resulting in clipping Error count of cumulative count value X1.

Assuming that the six sampling values P1* of the key pulse P1 by CP1 before the sampling point 1 of CP1 in FIG. 8 are all 0, the output pulse P2 is 0. In Figure 8, the key pulse P1 has a positive pulse interference before the sampling point 2 of CP1 and after the sampling point 3, resulting in X1 sampling at sampling points 2 and 3 to obtain the interference value 1 of P1*; the key pulse P1 is at the CP1 There is positive narrow pulse random interference between sampling point 4 and sampling point 5, but the positive narrow pulse width is smaller than the sampling period and is between two sampling points, which does not affect the sampling result P1*, that is, the sampling process automatically filters out the positive narrow pulse. Narrow pulse interference. The key pulse P1 starts to change from 0 to 1 after sampling point 6 of CP1, and there are 2 edge jitters in the process of changing from 0 to 1, and the second positive narrow pulse jitter interference is automatically filtered out by the sampling process. Sampling points 7, The values of sampling point 8 are 1 and 0 respectively. In FIG. 8 , see Table 1 for the key pulse sampling value P1*, output pulse P2 and clipping cumulative count value X1 obtained at sampling point 1 to sampling point 15 of the clock pulse CP1.

Table 1 Key pulse sampling value P1*, limiting cumulative count value X1 and output pulse P2 of sampling points 1-15

Observe the sampling points in Table 1. At sampling points 1-2, X1 is less than or equal to Y2, RE1 is valid, SE1 is invalid, and P2 is set to 0; at sampling point 3, X1 is greater than Y2 and smaller than Y1, SE1 and RE1 are invalid. P2 remains at 0; at sampling points 4-9, X1 is less than or equal to Y2, RE1 is valid, SE1 is invalid, and P2 is set to 0; at sampling points 10-12, X1 is greater than Y2 and less than Y1, SE1 and RE1 are invalid, and P2 remains is 0; at sampling point 13-15, X1 is greater than or equal to Y1, SE1 is valid, RE1 is invalid, and P2 is set to 1. When N=6, the counting interval of the reversible limiter counting unit is 0-N; at sampling point 5 in Table 1, X1 has reached the lower limit amplitude value 0, CPD remains high, and at sampling point 6, P1* = 0, X1 does not count down anymore, and X1 maintains the lower limit amplitude value of 0; at sampling point 14, X1 has reached the upper limit amplitude value of 6, and the CPU maintains a high level; at sampling point 15, P1*=1, X1 is no longer counting up, and X1 remains at the upper limit value of 6.

Figure 8 shows the anti-positive pulse interference effect of the key pulse filter circuit when the key pulse P1 is 0, and the conditions and process of the key pulse P1 changing from 0 to 1. The anti-negative pulse interference effect of the key pulse filter circuit when the key pulse P1 is 1, and the conditions and process of the key pulse P1 changing from 1 to 0, and the anti-positive pulse interference effect when the key pulse P1 is 0, and the key pulse P1 The conditions for changing from 0 to 1 are the same as the process.

It is assumed that the six sampling values P1 * of the key pulse P1 by CP1 before the sampling point 31 of the clock pulse CP1 are all 1, and the output pulse P2 is 1. See Table 2 for the key pulse sampling value P1*, limiter cumulative count value X1 and output pulse P2 obtained from sampling point 31 to sampling point 45.

Table 2 Key pulse sampling value P1*, limiting cumulative count value X1 and output pulse P2 of sampling points 31-45

Observe the sampling points in Table 2. At sampling points 31-32, X1 is greater than or equal to Y1, SE1 is valid, RE1 is invalid, and P2 is set to 1; at sampling point 33, X1 is greater than Y2 and less than Y1, SE1 and RE1 are invalid. P2 remains at 1; at sampling point 34, X1 is greater than or equal to Y1, SE1 is valid, RE1 is invalid, and P2 is set to 1; at sampling point 35-39, X1 is greater than Y2 and less than Y1, SE1 and RE1 are invalid, and P2 remains at 1 ;Because between the sampling points 31-40, the sampling value P1* is in the state of more than 0 and less than 1, the result of the cumulative counting of the reversible limiter counting unit is that the limiter cumulative count value X1 tends to decrease, and at the sampling point 40, X1 is less than Equal to Y2, RE1 is valid, SE1 is invalid, and P2 is set to 0; at sampling point 41, X1 is greater than Y2 and smaller than Y1, SE1 and RE1 are invalid, and P2 remains 0; at sampling point 42-45, X1 is less than or equal to Y2, RE1 Valid, SE1 is invalid, P2 is set to 0. At sampling point 43 in Table 2, X1 has reached the lower limit amplitude value of 0, and at sampling points 44-45, P1*=0, X1 does not count down any more, and X1 remains at the lower limit amplitude value of 0.

In this embodiment of the key pulse filter circuit where N=6, the output pulse P2 and the key pulse P1 are in-phase. If the function of the reversible limit counting unit is changed to: when P1=1, the key pulse sampling value P1* controls the reversible limit counting unit to count down; when P1=0, the key pulse sampling value P1* controls the reversible limit counting unit When counting up, the relationship between the output pulse P2 and the key pulse P1 is inverse. Or change the output pulse P2 to output from the NOR gate FO3 in Figure 6, then the function is changed to, when SE1 is valid and RE1 is invalid, the output pulse P2 is set to 0; when SE1 is invalid and RE1 is valid, the output The pulse P2 is set to 1; when both SE1 and RE1 are invalid, the state of the output pulse P2 remains unchanged; at this time, the relationship between the output pulse P2 and the key pulse P1 is inverse. If the above modification is carried out at the same time, the output pulse P2 and the key pulse P1 are in-phase.

Taking the in-phase relationship between the output pulse P2 and the key pulse P1 as an example, it can be concluded from Table 1, Table 2 and the working principle of the circuit that due to the cumulative effect of the reversible limiter counting unit, when the sampling value of the key pulse P1 P1* When the number of 1s is greater than the number of 0s within a period of time, the limiting cumulative count value X1 will tend to increase, making X1 greater than or equal to Y1 and setting the output pulse P2 to 1; when the sampling value of the key pulse P1 is P1 * When the quantity of 0 is more than the quantity of 1 within a period of time, the limiting cumulative count value X1 will tend to decrease, so that X1 is less than or equal to Y2 and the output pulse P2 is set to 0; this characteristic makes the limiter of the circuit of the present invention The counting unit has self-starting capability, and the limit function and 0 in the key pulse sampling value P1* will cause the limit count unit to enter the normal limit count interval for limit addition and subtraction counting. When the initial limiting cumulative count value X1 is greater than N and is in an over-limit state, X1 is greater than or equal to the upper limit comparison threshold Y1, SE1 output by the upper limit comparator unit is valid, RE1 output by the lower limit comparator unit is invalid, and P2 is set to 1.

Since the upper limit comparison threshold Y1 is an integer greater than N/2 and less than or equal to N, and the lower limit comparison threshold Y2 is an integer greater than or equal to 0 and less than N/2, the first set signal SE1 and the second set signal RE1 cannot be valid at the same time , therefore, the output of the output control unit will not have an uncertain logic state.

Taking the in-phase relationship between the output pulse P2 and the key pulse P1 as an example for further description. When the key pulse P1 makes the limiter cumulative count value X1 less than or equal to the lower limit comparison threshold Y2, after the output pulse P2 is set to 0, as long as the limiter cumulative count value X1 is always smaller than the upper limit comparison threshold Y1, the output pulse P2 will not become 1; When the key pulse P1 makes the limiting cumulative count value X1 greater than or equal to the upper limit comparison threshold Y1, after the output pulse P2 is set to 1, as long as the limiting limit cumulative count value X1 is always greater than the lower limit comparison threshold Y2, the output pulse P2 will not become 0. When both P1 and P2 are at low level, as long as the positive pulse that appears in P1 makes P1 sampled values greater than or equal to Y1 values of 1 appear continuously, or Y1+ appears in consecutive Y1+2 P1 sampled values One value is 1, etc., then the positive pulse corresponding to the positive pulse in P1 can be output from P2; when both P1 and P2 are high level, as long as the negative pulse appearing in P1 makes the sampling value of P1 continuous If there are more than or equal to N-Y2 values of 0, or, in consecutive N-Y2+2 P1 sampling values, N-Y2+1 values of 0 appear, etc., then it can be output from P2 and the P1 Negative pulses corresponding to negative pulses. When the key pulse P1 changes from 0 to 1, the output pulse P2 requires the limiter cumulative count value X1 to be counted up and delayed by several sampling pulse cycles, so that the limiter cumulative count value X1 is greater than or equal to the upper limit comparison threshold Y1, and P2 is set to 1; When the key pulse P1 changes from 1 to 0, the output pulse P2 requires the limiter cumulative count value X1 to go through a countdown delay of several sampling pulse cycles, so that the limiter cumulative count value X1 is less than or equal to the lower limit comparison threshold Y2, and will P2 is set to 0. When the value of the upper limit comparison threshold Y1 is larger, the condition for the output pulse P2 to change from 0 to 1 is more severe, and the low level of the circuit has a better anti-positive pulse interference effect; the smaller the value of the lower limit comparison threshold Y2, the output pulse The conditions for P2 to change from 1 to 0 are more severe, and the high level of the circuit has a better anti-negative pulse interference effect. When the value of N becomes larger, the key pulse filter circuit will change the output pulse P2 from 0 to 1, and the conditions from 1 to 0 will become stricter, and the anti-interference effect will become better, but the delay time of the output pulse P2 relative to the key pulse P1 become larger; when the value of N becomes smaller, the key pulse filter circuit will change the output pulse P2 from 0 to 1, and the condition from 1 to 0 will be widened, and the anti-interference effect will become smaller, but the output pulse P2 is relatively smaller than the key pulse P1 The delay time becomes smaller.

The period and high-level width of the sampling clock pulse are determined according to the pulse width, change speed and width of the interference pulse of the key pulse P1. For example, if the key pulse P1 comes from the control output of an ordinary button switch, since the pulse width formed by the ordinary button switch is at least 100ms, the jitter interference pulse width of the ordinary button switch is less than 10ms, so the period of the sampling clock pulse can be selected as 10ms Around, N takes a value in the range of 3 to 7.

Fig. 9 is an embodiment of the key pulse circuit, which is composed of key S10 and its pull-up resistor R10, +VCC is the power supply, GND is the common ground, and the key pulse P1 is output.

All of the reversible limiter counting unit, comparison threshold setting unit, upper limit comparator unit, lower limit comparator unit, output control unit, oscillator unit, or some of the functions in the key pulse filter circuit can use PAL, GAL, CPLD, FPGA, or other programmable logic devices and logic units.

Except for the technical features described in the description, all are conventional techniques mastered by those skilled in the art.

Claims (7)

1. A kind of 1. key pulse de-jittering method, it is characterised in that：

   Key pulse is sampled at sample clock pulse edge to obtain key pulse sampled value；Reversible clip counting unit by The control of key pulse sampled value level state is in plus count status either subtracts count status, is exported as to sampling clock arteries and veins Rush in the amplitude limit stored counts value of row counting；Threshold value is compared according to amplitude limit stored counts value and the upper limit and lower limit compares the ratio of threshold value Compared with as a result, the signal for producing control output impulse level state removes the level state of control output pulse；

   The amplitude limit stored counts value is binary count value；The Lower Limit Amplitude of the amplitude limit stored counts value is 0, upper limit magnitude For N；The N is the integer more than or equal to 2.
2. 2. key pulse de-jittering method according to claim 1, it is characterised in that：The upper limit compare threshold value be more than N/2 and the integer less than or equal to N；The lower limit compares threshold value for the integer more than or equal to 0 and less than N/2.
3. 3. key pulse de-jittering method according to claim 2, it is characterised in that：The control output impulse level shape The signal of state is the first set signal and the second set signal, by the first set signal and the control output pulse of the second set signal Level state；When amplitude limit stored counts value compares threshold value more than or equal to the upper limit, make the first set signal effective, otherwise first Set invalidating signal；When amplitude limit stored counts value compares threshold value less than or equal to lower limit, make the second set signal effective, otherwise Two set invalidating signals.
4. 4. key pulse de-jittering method according to claim 3, it is characterised in that：Put by the first set signal and second The method of position signal control output impulse level state is, the first set signal of input is effectively and the second set invalidating signal When, output pulse is set to 1；When the first set invalidating signal and effective the second set signal of input, output pulse is set to 0；When the first set signal and invalid the second set signal of input, output pulse condition is constant.
5. 5. key pulse de-jittering method according to claim 3, it is characterised in that：Put by the first set signal and second The method of position signal control output impulse level state is, the first set signal of input is effectively and the second set invalidating signal When, output pulse is set to 0；When the first set invalidating signal and effective the second set signal of input, output pulse is set to 1；When the first set signal and invalid the second set signal of input, output pulse condition is constant.
6. 6. the key pulse de-jittering method according to any one of claim 1-5, it is characterised in that：Reversible clip counting Unit does not add sample clock pulse in when adding count status and amplitude limit stored counts value is more than or equal to upper limit magnitude N Count；Reversible clip counting unit, which is in, subtracts count status and when amplitude limit stored counts value is equal to Lower Limit Amplitude 0, not to sampling when Clock carries out subtracting counting.
7. 7. the key pulse de-jittering method according to any one of claim 1-5, it is characterised in that：Reversible clip counting Unit is made of the forward-backward counter and amplitude limit and add-subtract control circuit inputted with doubleclocking.