CN107800409B

CN107800409B - Accumulation type interference pulse filtering method

Info

Publication number: CN107800409B
Application number: CN201711133965.8A
Authority: CN
Inventors: 聂辉; 凌云; 文定都; 罗学明; 何丽平
Original assignee: Hunan University of Technology
Current assignee: Shanxian Qiuge Agricultural Products Co ltd
Priority date: 2017-11-16
Filing date: 2017-11-16
Publication date: 2020-11-06
Anticipated expiration: 2037-11-16
Also published as: CN107800409A

Abstract

An accumulation type interference pulse filtering method is characterized in that 2 states of input pulses respectively control a reversible amplitude limiting counting unit to count up or count down sampling clock pulses, and the output of the reversible amplitude limiting counting unit is an amplitude limiting accumulated count value; and decoding the amplitude limiting accumulated count value to obtain a decoding output signal, and controlling the output pulse to be set to 1 or 0 according to the decoding output signal according to the upper limit comparison threshold and the lower limit comparison threshold. The method can filter out positive narrow pulse interference or negative narrow pulse interference; the effect of resisting pulse interference can be adjusted by changing the magnitude of the upper limit amplitude of the amplitude limiting accumulated count value or changing the magnitude of the upper limit comparison threshold value and the lower limit comparison threshold value; the method can be applied to occasions where various narrow pulse interference signals need to be filtered in a digital signal circuit.

Description

Accumulation type interference pulse filtering method

Technical Field

The invention relates to the field of pulse circuit signal processing, in particular to an accumulation type interference pulse filtering method.

Background

In digital signal circuits, it is often necessary to filter the interference pulses in the pulse signal, for example, to filter out single or consecutive narrow interference pulses, to filter out jittering pulses of mechanical switches, and so on. The current common method adopts a filter circuit to filter or adopts MCU to sample and then carry out algorithm processing. When the frequency of narrow pulses to be filtered is high, the filter circuit has a direct-current memory effect, and the front narrow pulses can influence the filtering of the rear narrow pulses. When the algorithm processing is carried out after the sampling by the MCU, the MCU occupies the processing time of the MCU, and the MCU is also easily influenced by various interferences, thereby influencing the filtering of narrow pulses.

Disclosure of Invention

In order to solve the problem of filtering interference pulses in the existing digital pulse signal processing, the invention provides an accumulation type interference pulse filtering method, which comprises the following steps:

the level state of the input pulse controls the reversible amplitude limiting counting unit to be in an up-counting state or a down-counting state, and the output of the reversible amplitude limiting counting unit is an amplitude limiting accumulated count value for counting sampling clock pulses; and decoding the amplitude limiting accumulated count value to obtain a decoding output signal, and generating a signal for controlling the level state of the output pulse according to the decoding output signal to control the level state of the output pulse. The amplitude limiting accumulated count value is a binary count value; the lower limit amplitude of the amplitude limiting accumulated count value is 0, and the upper limit amplitude is N; and N is an integer greater than or equal to 2.

When the reversible amplitude limiting counting unit is in an up-counting state and the amplitude limiting accumulated count value is greater than or equal to the upper limit amplitude value N, the reversible amplitude limiting counting unit does not count the sampling clock pulse; when the reversible amplitude limiting counting unit is in a count-down state and the amplitude limiting accumulated count value is equal to the lower limit amplitude value 0, the reversible amplitude limiting counting unit does not count down the sampling clock pulse.

And decoding the amplitude limiting accumulated count value to obtain N +1 decoding output signals corresponding to the amplitude limiting accumulated count value. The N +1 decoded output signals are composed of y0, y1, … …, yN, and only one of y0, y1, … …, yN is valid; valid signals in y0, y1, … … and yN correspond to 0, 1, … … and N in the clipping accumulated count value in a one-to-one mode, namely when the clipping accumulated count value is i, the decoding output signal yi is valid.

Generating a signal for controlling the output pulse state according to the decoded output signal by using a first set signal and a second set signal as the signal for controlling the output pulse state; the first set signal is asserted when yN and one of N-XU1(N minus XU1) decoded output signals adjacent to yN are asserted, otherwise the first set signal is deasserted; when one of y0 and XD1 decoded output signals adjacent to y0 is valid, the second set signal is valid, otherwise the second set signal is invalid; the XU1 is an anti-interference upper threshold, and the XD1 is an anti-interference lower threshold. The upper anti-interference threshold is an integer which is greater than N/2(N is divided by 2) and less than or equal to N; the lower anti-interference threshold is an integer which is greater than or equal to 0 and less than N/2.

The method for controlling the state of the output pulse by the first setting signal and the second setting signal is that when the input first setting signal is effective and the second setting signal is ineffective, the output pulse is set to be 1; setting the output pulse to 0 when the input first setting signal is invalid and the second setting signal is valid; when the input first set signal and the second set signal are both invalid, the output pulse state is unchanged. The method for controlling the output pulse state by the first setting signal and the second setting signal is that when the input first setting signal is effective and the second setting signal is ineffective, the output pulse is set to be 0; when the input first setting signal is invalid and the second setting signal is valid, setting the output pulse to be 1; when the input first set signal and the second set signal are both invalid, the output pulse state is unchanged.

When the output of the reversible slice count unit is greater than N, yN in the N +1 decoded output signals is valid. Or, when the output of the reversible amplitude-limiting counting unit is greater than N, the number of decoded output signals is more than N + 1; when the decoded output signals other than y0, y1, … …, yN among the more than N +1 decoded output signals are valid, the first set signal is made valid.

The reversible amplitude limiting counting unit consists of a reversible counter with single clock input and an amplitude limiting and adding and subtracting control circuit; the up-down counter has an up-down control input and an enable input.

The invention has the beneficial effects that: the positive narrow pulse interference and the negative narrow pulse interference can be automatically filtered; the effect of filtering the pulse interference can be adjusted by changing the magnitude of the upper limit amplitude of the amplitude limiting accumulated count value or changing the magnitude of the upper limit comparison threshold value and the lower limit comparison threshold value; the method can be applied to occasions where positive and negative narrow pulse interference signals need to be filtered in a digital signal circuit.

Drawings

FIG. 1 is an embodiment of an integrated glitch filter circuit;

fig. 2 shows an embodiment of an invertible slice count unit when N is 6;

fig. 3 shows decoder unit embodiment 1 when N is 6;

fig. 4 shows an embodiment of an interference rejection threshold selection unit when N is 6;

fig. 5 shows decoder unit embodiment 2 when N is 6;

FIG. 6 is an embodiment of an output control unit;

FIG. 7 is an oscillator cell embodiment;

fig. 8 is a schematic diagram of the interference rejection effect of the accumulation-type interference pulse filtering circuit when N is 6.

Detailed Description

The invention is further described below with reference to the accompanying drawings. The accumulation type interference pulse filtering method is realized by an accumulation type interference pulse filtering circuit comprising a reversible amplitude limiting counting unit, a decoder unit, an anti-interference threshold value selection unit, an output control unit and an oscillator unit. The oscillator unit may be omitted when the application of the integrating glitch filter circuit has a suitable clock pulse as the sampling clock pulse.

Fig. 1 shows an embodiment of an accumulative interference pulse filtering circuit. In fig. 1, the reversible slice count unit 101 has inputs of an input pulse P1 and a sampling clock CP1, and outputs of a slice accumulated count value X1, where the upper and lower limit amplitudes of the slice accumulated count value X1 are N and 0, respectively; the decoder unit 102 inputs the sliced accumulated count value X1 and outputs a decoded output signal X2; the input of the anti-interference threshold selection unit 103 is a decoding output signal X2, and the output is a first set signal SE1 and a second set signal RE 1; the input of the output control unit 104 is a first set signal SE1 and a second set signal RE1, and the output is an output pulse P2 of the accumulation interference pulse filter circuit; the oscillator unit 105 outputs a sampling clock pulse CP 1.

In the following examples, N is 6.

Fig. 2 shows an embodiment of the reversible slice count unit when N is 6. In fig. 2, FC1 is a 4-bit binary up-down counter 74HC191, the set control input LD input 1 of FC1, FC1 operates in a controllable up-down counting state, and is an up-down counter with a single clock input; the M input of FC1 is the add-subtract control input and the CE input is the enable control input. The NAND gates FA1, FA2, FA3 and FA4 form an amplitude limiting and adding and subtracting control circuit. The level state of the input pulse includes a high level and a low level, in the embodiment of fig. 2, P1 is inverted and then connected to the add/subtract control input end M, and the high level and the low level state of the input pulse respectively control the reversible slice-limited counting unit to be in the add-count state and the subtract-count state. When P1 is directly connected to the add/subtract control input terminal M, the high level and the low level of the input pulse can control the reversible slice-counting unit to be in the down-counting state and the up-counting state, respectively.

When P1 is 1, and x13 and x12 are 1 at the same time, the nand gate FA1 outputs low level, the nand gate FA3 outputs high level, the enable control end CE of FC1 inputs high level, and 74HC191 operates in a hold state, that is, the inverse slice counting unit maintains the output state unchanged at the rising edge of the sampling clock pulse CP1, and the inverse slice counting unit is in an upper limit value slice state and does not count up; the condition that x13 and x12 are 1 simultaneously comprises 2 conditions, and when x13, x12 and x11 are 1, 1 and 0, the output of the reversible amplitude limiting counting unit is equal to the upper limit amplitude value of 6; when x13, x12 and x11 are 1, 1 and 1, the output of the reversible amplitude limiting counting unit is equal to 7 and is in an over-limit state, the situation is possible to occur only in an initial state when the system is started, and after the reversible amplitude limiting counting unit enters a normal amplitude limiting counting interval through counting down, the output over-limit state cannot occur any more. When P1 is 0 and x13, x12 and x11 are 0 at the same time, the nand gate FA2 outputs low level, the nand gate FA3 outputs high level, the enable control end CE of FC1 inputs high level, and 74HC191 operates in a hold state, that is, the inverse slice counting unit maintains the output state unchanged at the rising edge of the sampling clock CP1, the reversible slice counting unit is in a lower limit slice state, and the count reduction is not performed. The input pulse P1 has 2 states of high level and low level, i.e. the input pulse P1 has 2 states of 1 and 0, and the two states of the input pulse P1 control the reversible slice count unit to count up or down the sampling clock pulse CP1, respectively. When P1 is 1 and x13 and x12 are not 1 at the same time, both the nand gates FA1 and FA2 output high level, the nand gate FA3 outputs low level, the enable control end CE of FC1 inputs low level, the P1 enables the add-subtract control end M to input low level through the nand gate FA4, the 74HC191 works in an up-counting state, and the reversible slice counting unit performs up-counting on the rising edge of the sampling clock pulse CP 1. When the P1 is 0 and x13, x12 and x11 are not 0 at the same time, the nand gates FA1 and FA2 both output high level, the nand gate FA3 outputs low level, the enable control end CE of the FC1 inputs low level, the add-subtract control end M inputs high level, the 74HC191 operates in a count-down state, and the reversible slice counting unit performs count-down on the rising edge of the sampling clock CP 1. 74HC191 is a synchronous binary counter, which controls whether to count and whether to count up or down only in the state of the rising edge time P1 of the sampling clock pulse CP1 inputted from its clock input end CP; at the non-rising edge time of the CP1, the P1 causes the change of the enable control terminal CE and the add-subtract control terminal M to not affect the x13, x12, and x11 output by the 74HC 191. During the period when the clock input end CP is low, the P1 causes the change of the enable control end CE and the add/subtract control end M to affect the carry/borrow signal of the 74HC191, and in the embodiment of fig. 2, the carry/borrow signal of the 74HC191 is not used, so that the effect is not affected. The output of the reversible amplitude limiting counting unit is controlled and changed by the P1 value at the rising edge moment of the sampling clock pulse, namely the output of the reversible amplitude limiting counting unit is related to the sampling value at the rising edge moment P1 of the sampling clock pulse and is controlled by the sampling value at the rising edge moment P1 of the sampling clock pulse. The output of the reversible slice count unit may also be controlled to change by the value of P1 at the time of the falling edge of the sampling clock pulse.

When N is other number, the number of nand gates for performing count and slice control in fig. 2 can be increased or decreased, and the number of input signals of each nand gate can be increased or decreased. The function of the reversible limit counting unit can also be realized by other devices or circuits, for example, 74HC191 is replaced by 74HC190, CD4516 and the like, or a synchronous reversible counter is formed by a flip-flop and a gate circuit.

The decoder unit is used for decoding the input amplitude limiting accumulated count value to obtain N +1 decoding output signals; the N +1 decoding output signals consist of y0, y1, … … and yN, and only one of y0, y1, … … and yN is valid; valid signals in the y0, y1, … … and yN correspond to 0, 1, … … and N in the clipping accumulated count value in a one-to-one mode. Fig. 3 shows decoder unit embodiment 1 when N is 6, and FD1 is 3-line-8-line decoder 74HC 138. The 3-bit binary outputs X13, X12 and X11 of the clipped accumulated count value X1 are respectively connected to the 3-bit address inputs A2, A1 and A0 of the FD1 and the 3 enable inputs of the

FD1

E3 inputs

0, 1, FD1 respectivelyThe decoding state is performed. 7 decoded output signals X2 are output from the decoded output terminal of FD1, the decoded output terminal of FD1

The signals y0, y1, y2, y3, y4, y5, y6 are output, respectively. Y0, y1, y2, y3, y4, y5 and y6 which are all active low constitute decoded output signals X2, y0, y1, y2, y3, y4, y5 and y6 which are respectively in one-to-one correspondence with 0, 1, 2, 3, 4, 5 and 6 of the sliced accumulated count value X1. When N is 6, the over-limit output state of the clipped accumulated count value X1 is only X1 is 7, and the decoded output end of FD1

The output signal y7 corresponds. The function of the decoder unit can be realized by 1 or more decoder chips or a combinational logic circuit composed of gates.

The anti-interference threshold selection unit has the function of enabling the first setting signal to be effective when one of the input yN and 1 decoding output signals adjacent to the yN is effective; the second set signal is asserted when one of the input y0 and XD1 decoded output signals adjacent to y0 are asserted. Fig. 4 is an embodiment of an anti-interference threshold selection unit when N is 6, which is composed of nand gates FA5 and FA6, resistors R91, R92, R93 and R94, anti-interference upper limit threshold selection switches KS5 and KS4, and anti-interference lower limit threshold selection switches KR1 and KR 2; + VCC is power supply; the interference resistance upper limit threshold XU1 has the value ranges of 4, 5 and 6, and the interference resistance lower limit threshold XD1 has the value ranges of 0, 1 and 2. The anti-interference upper limit threshold XU1 in fig. 4 is selected by the selection switches KS5 and KS4, when KS5 and KS4 are all off, y6 is valid only when the amplitude limiting accumulated count value X1 is equal to 6, the first set signal SE1 is valid, and the anti-interference upper limit threshold XU1 is equal to 6; when KS5 is closed and KS4 is opened, as long as the clip accumulated count value X1 is greater than or equal to 5, namely any 1 of y6 and 1 decoding output signal y5 adjacent to y6 is effective, the first set signal SE1 is effective, and the anti-interference upper limit threshold XU1 is equal to 5; when KS5 and KS4 are both closed, as long as the clip accumulated count value X1 is equal to or greater than 4, that is, any 1 of y6 and the 2 decoded output signals y5 and y4 adjacent to y6 is valid, the first set signal SE1 is valid, and the interference rejection upper limit threshold XU1 is equal to 4. In fig. 4, the lower interference resistance threshold XD1 is selected by the selection switches KR1 and KR2, when KR1 and KR2 are all turned off, y0 is valid only when the cumulative amplitude limiting count value X1 is equal to 0, the second set signal RE1 is valid, and the lower interference resistance threshold XD1 is equal to 0; when KR1 is closed and KR2 is open, as long as the clipping accumulated count value X1 is less than or equal to 1, that is, any 1 of y0 and 1 decoding output signal y1 adjacent to y0 is valid, the second set signal RE1 is valid, and the lower interference resistance threshold is equal to 1; when KR1 and KR2 are both closed, as long as the slice accumulated count value X1 is greater than or equal to 4, i.e., any 1 of y0 and the 2 decoded output signals y1 and y2 adjacent to y0 are valid, the second set signal RE1 is valid, and the interference rejection lower limit threshold XD1 is equal to 2. When the initial clipped accumulated count value X1 is greater than N and is in an overrun state, the decoder unit will output a state corresponding to the clipped accumulated count value X1 that is overrun, that is, X1 is equal to 7, and the signal y7 output by the decoder unit is valid; in fig. 4, y7 is the signal that decodes more than N +1 of the output signals when the output of the reversible slice count unit is greater than N. y7 is connected directly to the input of the nand gate FA5 as y6, so that the first set signal SE1 will be asserted as y6 is asserted when y7 is asserted.

In fig. 4, the high levels of the first set signal SE1 and the second set signal RE1 are active; the nand gates FA5 and FA6 are changed to and gates, and the first set signal SE1 and the second set signal RE1 become active low. Selecting one of yN and N-XU1 decoded output signals adjacent to yN to be valid, and then making the first set signal valid, and selecting one of y0 and XD1 decoded output signals adjacent to y0 to be valid, and then making the second set signal valid as or logic; in this embodiment, the output of the decoder unit is active low, and the anti-interference threshold selection unit uses and logic gates to implement the above-mentioned or logic function. When the output of the decoder unit is active at a high level, the antijamming threshold selecting unit may use an or gate or a nor gate to implement the above-mentioned or logic function.

Fig. 5 shows decoder unit embodiment 2 when N is 6, FD2 is 3-line-8-line decoder 74HC138, and FA7 is an and gate. The 3-bit binary outputs X13, X12 and X11 of the clipped accumulated count value X1 are respectively connected to the 3-bit address inputs A2, A1 and A0 of the FD2 and the 3 enable inputs of the

FD2

E3 inputs

0, 0 and 1 respectively, X2 has 7 decoding output signals, wherein y0, y1, y2, y3, y4 and y5 are respectively directly transmitted from the decoding output end of FD2

Output, y6 is output from the output of AND gate FA7, 2 inputs of AND gate FA7 are connected to FD2

An output end; when the clipped accumulated count value X1 is equal to N, i.e., equal to 6, and the clipped accumulated count value X1 is greater than N, i.e., equal to 7, yN, i.e., y6, is valid. If the output of decoder unit embodiment 2 is input as the signal of the immunity threshold selecting unit in fig. 4, there is no y7 signal, and in this case, the FA5 in fig. 5 needs to be changed to a 3-input nand gate, in which the y7 input signal and the y7 input terminal are eliminated.

The output control unit is used for setting the output pulse to be 1 when the input first setting signal is effective and the second setting signal is ineffective; setting the output pulse to 0 when the input first setting signal is invalid and the second setting signal is valid; when the input first set signal and the second set signal are both invalid, the output pulse state is unchanged. The output control unit is used for setting the output pulse to be 0 when the input first setting signal is effective and the second setting signal is ineffective; when the input first setting signal is invalid and the second setting signal is valid, setting the output pulse to be 1; when the input first set signal and the second set signal are both invalid, the output pulse state is unchanged. The function of the output control unit is realized by an RS trigger, and FIG. 6 is an embodiment of the output control unit. In fig. 6, the nor gates FO1 and FO2 constitute RS flip-flops, and the first set signal SE1 and the second set signal RE1 are both active high; the first set signal SE1 is a set signal of an RS flip-flop, and the second set signal RE1 is a reset signal of the RS flip-flop; the output pulse P2 is output from the non-inverting output terminal of the RS flip-flop. When SE1 is active and RE1 is inactive, an output pulse P2 output from the in-phase output terminal FO2 is set to 1; when the SE1 is invalid and the RE1 is valid, the output pulse P2 is set to 0; when both SE1 and RE1 are inactive, the state of the output pulse P2 is unchanged. The output pulse P2 may also be output from the inverting output, i.e., the output of the or gate FO 1. The output control unit may also adopt other forms of RS flip-flops.

Fig. 7 is an oscillator cell embodiment. In fig. 7, the CMOS not gates FN1 and FN2, the resistor R97, and the capacitor C97 constitute a multivibrator, and the sampling clock CP1 is output from the FN2 output terminal. The frequency of CP1 is changed by adjusting the values of resistor R97 and capacitor C97. The oscillator unit may also employ other types of multivibrators.

In the embodiment where N is 6, the interference resistance upper threshold XU1 is 5, and the interference resistance lower threshold XD1 is 0; when the amplitude limiting accumulated count value X1 is greater than or equal to 5, the output SE1 is at high level, and the output pulse P2 is set to 1; when the clip accumulated count value X1 is equal to or less than 0, the output RE1 is at a high level, and the output pulse P2 is set to 0.

Fig. 8 is a schematic diagram of the interference rejection effect of the accumulation-type interference pulse filtering circuit when N is 6. In fig. 8, the sampled value P1 of the input pulse P1, the clipped accumulated count value X1 of each sample point, and the resultant output pulse P2 are shown by 15 sampling clock pulses CP 1. The sampling value P1 is the value of the input pulse P1 when the sampling clock pulse CP1 counts edges; the reversible slice counting unit is controlled by 2 states of the input pulse P1 to count up or count down the sampling clock pulse CP1, and the reversible slice counting unit is controlled by the value of the input pulse P1 when the sampling clock pulse CP1 counts edges to count up or count down the sampling clock pulse CP 1. Before the sampling point 1 of the CP1 in fig. 8, 6 sampling points P1 of the CP1 for the input pulse P1 are all 0, and the output pulse P2 is 0. In fig. 8, positive pulse interference occurs before sampling point 2 of CP1 and after sampling point 3 of input pulse P1, which results in that X1 samples at sampling point 2 and sampling point 3 to obtain interference value 1 of P1 ×; the input pulse P1 shows positive narrow pulse interference between sample point 4 and sample point 5 of CP1, but the positive narrow pulse width is smaller than the sampling period and between 2 sample points, and the sampling result P1 is not affected, i.e. the sampling process automatically filters out the positive narrow pulse interference. The input pulse P1 starts to change from 0 to 1 after the sampling point 6 of the CP1, and 2 times of edge jitter occurs in the process of changing from 0 to 1, wherein 2 nd positive narrow pulse jitter interference is automatically filtered by the sampling process, and the sampling values of the sampling point 7 and the sampling point 8 are 1 and 0 respectively. In fig. 8, the sample value P1, the output pulse P2, and the clip accumulated count value X1 obtained from sample point 1 to sample point 15 of the clock CP1 are shown in table 1.

Table 1 samples P1, clip count X1, and output pulse P2 for samples 1-15

Observing the conditions of the sampling points in the table 1, wherein at the sampling point 1, X1 is less than or equal to XD1, RE1 is effective, SE1 is ineffective, and P2 is set to be 0; at sample points 2-4, X1 is greater than XD1 and less than XU1, both SE1 and RE1 are inactive, and P2 remains 0; at a sampling point of 5-6, X1 is less than or equal to XD1, RE1 is effective, SE1 is ineffective, and P2 is set to be 0; at sample point 7, X1 is greater than XD1 and less than XU1, both SE1 and RE1 are inactive, and P2 remains 0; at a sampling point 8, X1 is less than or equal to XD1, RE1 is effective, SE1 is ineffective, and P2 is set to be 0; at sample points 9-12, X1 is greater than XD1 and less than XU1, both SE1 and RE1 are inactive, and P2 remains 0; at sampling points 13-15, X1 is greater than or equal to XU1, SE1 is active, RE1 is inactive, and P2 is set to 1. When N is 6, the counting interval of the reversible amplitude limiting counting unit is 0-N; at sample 5 in table 1, X1 has reached the lower limit amplitude of 0, at sample 6, P1 ═ 0 (i.e., at this time, P1 ═ 0), X1 is also no longer counted down, and X1 remains at the lower limit amplitude of 0; at sample 14, X1 has reached the upper limit amplitude of 6, at sample 15, P1 ═ 1 (i.e., at this time, P1 ═ 1), X1 is also not counted up, and X1 remains at the upper limit amplitude of 6.

Fig. 8 shows the anti-positive pulse interference effect of the accumulation-type interference pulse filtering circuit when the input pulse P1 is 0, and the condition and process of the input pulse P1 changing from 0 to 1. The accumulative disturbance pulse filtering circuit has the same anti-negative pulse disturbance effect when the input pulse P1 is 1, the same conditions and processes of changing the input pulse P1 from 1 to 0, the same anti-positive pulse disturbance effect when the input pulse P1 is 0, and the same conditions and processes of changing the input pulse P1 from 0 to 1.

Before the sampling point 31 of the clock pulse CP1, the sampling points P1 of the CP1 for the input pulse P1 are all 1, and the output pulse P2 is 1. The sample value P1, the clipped cumulative count value X1 and the output pulse P2 from the sampling point 31 to the sampling point 45 are shown in table 2.

Sample values P1, clipped cumulative count X1 and output pulses P2 of samples 31-45 of table 2

Observing the conditions of the sampling points in the table 2, wherein X1 is more than or equal to XU1, SE1 is effective, RE1 is ineffective, and P2 is set to be 1 at the sampling points 31-32; at sample point 33, X1 is greater than XD1 and less than XU1, both SE1 and RE1 are inactive, and P2 remains 1; at a sampling point 34, X1 is more than or equal to XU1, SE1 is effective, RE1 is ineffective, and P2 is set to be 1; at sample points 35-42, X1 is greater than XD1 and less than XU1, both SE1 and RE1 are inactive, and P2 remains 1; since the sampling value P1 is in a state of more than 0 and less than 1 between the sampling points 31-42, the cumulative count value X1 of the reversible amplitude limiting counting unit tends to decrease as a result of cumulative counting by the amplitude limiting cumulative count value X1, until the sampling point 43, X1 is less than or equal to XD1, RE1 is valid, SE1 is invalid, and P2 is set to 0; at sample points 44-45, X1 is less than or equal to XD1, RE1 is active, SE1 is inactive, and P2 is set to 0. At sample 43 in table 2, X1 has reached the lower limit amplitude of 0, and at samples 44-45, P1 ═ 0 (i.e., at this time, P1 ═ 0), X1 is also not counted down, and X1 is maintained at the lower limit amplitude of 0.

In the present embodiment, where N is 6, the output pulse P2 and the input pulse P1 are in phase relationship. If the function of the reversible slice count unit is changed to: when the P1 is equal to 1, the reversible amplitude limiting counting unit performs count reduction; when P1 is equal to 0, the reversible slice count unit performs count-up, and the output pulse P2 and the input pulse P1 are in an inverse correlation. Or the output pulse P2 is changed to be output from the nor gate FO1 in fig. 6, the function is changed to set the output pulse P2 to 0 when SE1 is active and RE1 is inactive; when the SE1 is invalid and the RE1 is valid, setting the output pulse P2 to be 1; when both SE1 and RE1 are inactive, the state of the output pulse P2 is unchanged; in this case, the output pulse P2 and the input pulse P1 are in an inverse correlation. If the above modifications are performed simultaneously, the output pulse P2 and the input pulse P1 are in phase relationship.

Taking the in-phase relationship between the output pulse P2 and the input pulse P1 as an example, it can be concluded from tables 1 and 2 and the working principle of the circuit that, because the reversible clipping counting unit has an accumulation effect, when the number of 1 s in the sampling value of the input pulse P1 is greater than 0 s within a period of time, the clipping accumulated count value X1 tends to increase, so that X1 is greater than or equal to the interference resistance upper limit threshold XU1 and the output pulse P2 is set to 1; when the number of 0 sampling values of the input pulse P1 is more than 1 within a period of time, the amplitude limiting accumulated count value X1 tends to decrease, so that X1 is less than or equal to the interference resistance lower limit threshold value XD1, and the output pulse P2 is set to 0; the characteristic enables the amplitude limiting counting unit of the circuit of the invention to have self-starting capability, amplitude limiting function and the amplitude limiting counting unit to enter a normal amplitude limiting counting interval to carry out amplitude limiting addition and subtraction counting when 0 in a sampling value P1 of an input pulse P1.

Since the upper interference rejection threshold XU1 is an integer greater than N/2 and equal to or less than N, the lower interference rejection threshold XD1 is an integer greater than or equal to 0 and less than N/2, and the first set signal SE1 and the second set signal RE1 cannot be simultaneously valid, the output of the output control unit is not uncertain in logic state.

The in-phase relationship between the output pulse P2 and the input pulse P1 is further described as an example. When the input pulse P1 makes the clip accumulated count value X1 less than or equal to the interference resistance lower threshold value XD1 and the output pulse P2 is set to 0, the output pulse P2 will not become 1 as long as the clip accumulated count value X1 is always less than the interference resistance upper threshold value XU 1; when the input pulse P1 makes the clip accumulated count value X1 equal to or greater than the interference resistance upper threshold value XU1 and the output pulse P2 is set to 1, the output pulse P2 does not become 0 as long as the clip accumulated count value X1 is always greater than the interference resistance lower threshold value XD 1. When both P1 and P2 are at low level, a positive pulse corresponding to the positive pulse in P1 can be output from P2 as long as the positive pulse in P1 causes values equal to or greater than XU1 to 1 to continuously appear in the P1 sample value, or values XU1+1 to continuously appear in the XU1+ 2P 1 sample values, and so on; when both P1 and P2 are at a high level, a negative pulse corresponding to the negative pulse in P1 can be output from P2 as long as the negative pulse occurring in P1 causes values equal to or greater than N-XD1 to be 0 to continuously occur in P1 sample values, or N-XD1+1 to be 0 to continuously occur in N-XD1+ 2P 1 sample values, or the like. When the input pulse P1 is changed from 0 to 1, the output pulse P2 needs the clipping accumulated count value X1 to be added and counted for a plurality of sampling pulse periods and delayed, so that the clipping accumulated count value X1 is greater than or equal to the anti-interference upper limit threshold XU1, and P2 is set to 1; when the input pulse P1 changes from 1 to 0, the output pulse P2 needs the clip accumulated count value X1 to pass through the countdown delay of several sampling pulse periods, so that the clip accumulated count value X1 is less than or equal to the interference resistance lower limit threshold XD1, and P2 is set to 0. When the value of the anti-interference upper limit threshold XU1 is larger, the condition that the output pulse P2 is changed from 0 to 1 is more rigorous, and the low-level positive pulse interference resisting effect of the circuit is better; when the value of the anti-interference lower limit threshold XD1 is smaller, the condition that the output pulse P2 is changed from 1 to 0 is more rigorous, and the high-level negative pulse interference resisting effect of the circuit is better. When the value of N is larger, the conditions that the output pulse P2 is changed from 0 to 1 and from 1 to 0 are strictly changed by the accumulation interference pulse filtering circuit, the interference resistance effect is better, but the delay time of the output pulse P2 relative to the input pulse P1 is larger; when the value of N is smaller, the conditions for changing the output pulse P2 from 0 to 1 and from 1 to 0 are widened by the integrating interference pulse filter circuit, and the interference suppression effect is smaller, but the delay time of the output pulse P2 with respect to the input pulse P1 is smaller.

The period and the high level width of the sampling clock pulse are determined according to the pulse width of the input pulse P1, the changing speed, and the width of the interference pulse. For example, if the input pulse P1 is from the control output of a normal push button switch, the pulse width of the normal push button switch is at least 100ms, and the jitter interference pulse width of the normal push button switch is less than 10ms, so the period of the sampling clock pulse may be selected to be about 10ms, and N may be selected to be in the range of 3 to 7.

All or part of functions of a reversible amplitude limiting counting unit, an anti-interference threshold selection unit, a decoder unit, an output control unit and an oscillator unit in the accumulation type interference pulse filtering circuit can be realized by adopting PAL, GAL, CPLD and FPGA or other programmable logic devices and logic units.

Except for the technical features described in the specification, the method is the conventional technology which is mastered by a person skilled in the art.

Claims

1. An accumulation interference pulse filtering method, characterized in that:

the level state of the input pulse controls the reversible amplitude limiting counting unit to be in an up-counting state or a down-counting state, and the output of the reversible amplitude limiting counting unit is an amplitude limiting accumulated count value for counting sampling clock pulses; decoding the amplitude limiting accumulated count value to obtain a decoding output signal, and generating a signal for controlling the level state of the output pulse according to the decoding output signal to control the level state of the output pulse;

the amplitude limiting accumulated count value is a binary count value; the lower limit amplitude of the amplitude limiting accumulated count value is 0, and the upper limit amplitude is N; n is an integer greater than or equal to 2;

when the reversible amplitude limiting counting unit is in an up-counting state and the amplitude limiting accumulated count value is greater than or equal to the upper limit amplitude value N, the reversible amplitude limiting counting unit does not count the sampling clock pulse; when the reversible amplitude limiting counting unit is in a count-down state and the amplitude limiting accumulated count value is equal to the lower limit amplitude value 0, the reversible amplitude limiting counting unit does not count down the sampling clock pulse;

decoding the amplitude limiting accumulated count value to obtain N +1 decoding output signals; the N +1 decoded output signals are composed of y0, y1, … …, yN, and only one of y0, y1, … …, yN is valid; valid signals in the y0, y1, … … and yN correspond to the amplitude limiting accumulated count values 0, 1, … … and N one by one;

generating a signal for controlling the output pulse state according to the decoded output signal by using a first set signal and a second set signal as the signal for controlling the output pulse state; enabling the first set signal when one of the yN and 1 decoding output signals adjacent to the yN is valid, and otherwise, disabling the first set signal; when one of y0 and XD1 decoded output signals adjacent to y0 is valid, enabling the second set signal, otherwise, disabling the second set signal; the XU1 is an anti-interference upper threshold, and the XD1 is an anti-interference lower threshold;

the anti-interference upper limit threshold is an integer which is greater than N/2 and less than or equal to N; the lower anti-interference threshold is an integer which is greater than or equal to 0 and less than N/2.

2. The method of cumulative interference pulse filtering according to claim 1, characterized by: the method for controlling the state of the output pulse by the first setting signal and the second setting signal is that when the input first setting signal is effective and the second setting signal is ineffective, the output pulse is set to be 1; setting the output pulse to 0 when the input first setting signal is invalid and the second setting signal is valid; when the input first set signal and the second set signal are both invalid, the output pulse state is unchanged.

3. The method of cumulative interference pulse filtering according to claim 1, characterized by: the method for controlling the state of the output pulse by the first setting signal and the second setting signal is that when the input first setting signal is effective and the second setting signal is ineffective, the output pulse is set to be 0; when the input first setting signal is invalid and the second setting signal is valid, setting the output pulse to be 1; when the input first set signal and the second set signal are both invalid, the output pulse state is unchanged.

4. The accumulative disturbance pulse filtering method according to any one of claims 1 to 3, wherein: when the output of the reversible slice count unit is greater than N, yN in the N +1 decoded output signals is valid.

5. The accumulative disturbance pulse filtering method according to any one of claims 1 to 3, wherein: when the output of the reversible amplitude limiting counting unit is more than N, the number of decoding output signals is more than N + 1; when the decoded output signals other than y0, y1, … …, yN among the more than N +1 decoded output signals are valid, the first set signal is made valid.

6. The accumulative disturbance pulse filtering method according to any one of claims 1 to 3, wherein: the reversible amplitude limiting counting unit consists of a reversible counter with single clock input and an amplitude limiting and adding and subtracting control circuit; the up-down counter has an up-down control input and an enable input.