CN108460448A - Number of package grain signal generating method - Google Patents
Number of package grain signal generating method Download PDFInfo
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- CN108460448A CN108460448A CN201711261034.6A CN201711261034A CN108460448A CN 108460448 A CN108460448 A CN 108460448A CN 201711261034 A CN201711261034 A CN 201711261034A CN 108460448 A CN108460448 A CN 108460448A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06M—COUNTING MECHANISMS; COUNTING OF OBJECTS NOT OTHERWISE PROVIDED FOR
- G06M1/00—Design features of general application
- G06M1/27—Design features of general application for representing the result of count in the form of electric signals, e.g. by sensing markings on the counter drum
- G06M1/272—Design features of general application for representing the result of count in the form of electric signals, e.g. by sensing markings on the counter drum using photoelectric means
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06M—COUNTING MECHANISMS; COUNTING OF OBJECTS NOT OTHERWISE PROVIDED FOR
- G06M11/00—Counting of objects distributed at random, e.g. on a surface
- G06M11/02—Counting of objects distributed at random, e.g. on a surface using an electron beam scanning a surface line by line, e.g. of blood cells on a substrate
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/125—Discriminating pulses
- H03K5/1252—Suppression or limitation of noise or interference
- H03K5/1254—Suppression or limitation of noise or interference specially adapted for pulses generated by closure of switches, i.e. anti-bouncing devices
Abstract
A kind of number of package grain signal generating method, amplitude limit control signal is counted, subtracted to count amplitude limit control signal and count 2 kinds of states of inceptive impulse and control controllable reversible counter respectively and sample clock pulse is carried out plus is counted or subtract countings by adding, the output of controllable reversible counter is amplitude limit stored counts value；Differentiated according to amplitude limit stored counts value and anti-interference threshold value by ROM memory, and sends out the level state of control signal control output pulse.The method can filter out in several signal pulses single either continuous positive narrow pulse interference and can also filter out single or continuously bear narrow pulse interference；Filtering out the effect of disturbing pulse can be adjusted by changing the size of anti-interference threshold value；The method can be applied in the various packaging production lines for needing to carry out the counting of product number.
Description
Technical field
The present invention relates to field of product packaging, especially a kind of number of package grain signal generating method.
Background technology
Photo-electric detection counting technology is mainly that the light launched by infrared sensor detects in sense channel
The particle detections object such as powder, receiving sensor generates pulse signal due to blocking for particle detections object, for being counted
And record.Since the shape of particle detections object is irregular, the shake of translation or slope sliding, due to the overturning etc. of whereabouts, makes
The counting pulse generated at photoelectric sensor contain forward position, after along shaking interference pulse, when by it directly as pulse is counted,
It can cause counting error.
Line array CCD/CMOS technology is a kind of consecutive numbers grain method, and CCD/CMOS cameras can sweep material on channel
Counting is retouched, stops feed when reaching setting quantity, compared with infrared sensor technology, counting precision and speed are improved, but
It is of high cost.
Invention content
In order to solve the problems of existing several signals, the present invention provides a kind of number of package grain signal generation sides
Method, by including several signal transducers, controllable reversible counter, anti-interference threshold selector, ROM memory, rest-set flip-flop, shaking
The circuit for swinging device is realized.
By several inceptive impulses level state and add and count amplitude limit control signal, subtract and count amplitude limit control signal control
Reversible clip counting device be in plus count status, either in subtract count status or be in amplitude limit hold mode；Reversible amplitude limit
The output of counter is the amplitude limit stored counts value counted to sample clock pulse.
Several signal transducers export several inceptive impulses；The input of controllable reversible counter is several inceptive impulses, adopts
Sample clock pulses plus counting amplitude limit, which control signal and subtract, counts amplitude limit control signal, exports to be counted to sample clock pulse
Several amplitude limit stored counts values, amplitude limit stored counts value are 3 bits that Lower Limit Amplitude is 0, upper limit magnitude is 6；It is anti-dry
It disturbs threshold selector and exports anti-interference threshold value, anti-interference threshold value is 2 bits more than or equal to 0 and less than or equal to 2；ROM
The input of memory is amplitude limit stored counts value and anti-interference threshold value, is exported as the first set signal, the second set signal plus meter
Number amplitude limit control signal controls signal with counting amplitude limit is subtracted；The input of rest-set flip-flop is that the first set signal and the second set are believed
Number, export the several counting pulses for number of package grain signal generating circuit；Oscillator exports sample clock pulse.
Controllable reversible counter is made of the forward-backward counter and amplitude limit and add-subtract control circuit inputted with single clock；Institute
Stating forward-backward counter has add-subtract control input terminal and enabled input terminal.Several inceptive impulses are direct or the connection of inverted device
To the add-subtract control input terminal of forward-backward counter, to forward-backward counter plus count status, subtract count status and control.Amplitude limit
And the enabled enabled input terminal for controlling signal and being connected to forward-backward counter of add-subtract control circuit output；Forward-backward counter, which is in, to be added
Count status and add count amplitude limit control signal it is effective when or forward-backward counter be in subtract count status and subtract counting amplitude limit
When controlling signal, the enabled control invalidating signal of amplitude limit and add-subtract control circuit output, otherwise effectively；Enabled control invalidating signal
When, forward-backward counter does not count sample clock pulse.
Whether 6-M is more than or equal to amplitude limit stored counts value by ROM memory and whether amplitude limit stored counts value is less than
The signal for being differentiated equal to M, and generating several counting impulse level states of control goes to control the level shape of several counting pulses
State.ROM memory has 5 bit address input terminals and 4 data output ends；3 in 5 bit address input terminals are connected to controllable reversible
Counter output is used for input saturation stored counts value；Other 2 in 5 bit address input terminals are connected to anti-interference threshold value
Selector output end, for inputting anti-interference threshold value；4 data output ends of ROM memory export respectively the first set signal,
Second set signal and plus count amplitude limit control signal, subtract count amplitude limit control signal.
First set signal is connected to the set input of rest-set flip-flop, and the second set signal is connected to answering for rest-set flip-flop
Position input terminal；Pulse is exported to export from the in-phase output end or reversed-phase output of rest-set flip-flop.
Anti-interference threshold selector is by first threshold selecting switch, second threshold selecting switch, the first pull-up resistor, second
Pull-up resistor forms.First threshold selecting switch connect with the first pull-up resistor and second threshold selecting switch and second on
After pull-up resistor series connection, then it is connected in parallel to power supply；From first threshold selecting switch and the first pull-up resistor series connection node and second
Threshold value selecting switch exports anti-interference threshold value with the second pull-up resistor series connection node.
The beneficial effects of the invention are as follows：The positive narrow pulse interference in several pulse signals and negative burst pulse can be filtered out automatically
Interference can also filter out continuous positive narrow pulse interference or be continuous negative narrow pulse interference；Filter out the effect of impulse disturbances
It can be adjusted by changing the size of anti-interference threshold value.
Description of the drawings
Fig. 1 is number of package grain signal generating circuit embodiment；
Fig. 2 is several signal transducer embodiments；
Fig. 3 is controllable reversible counter embodiment；
Fig. 4 is anti-interference threshold selector and ROM memory embodiment；
Fig. 5 is rest-set flip-flop embodiment；
Fig. 6 is oscillator embodiment；
Fig. 7 is the anti-jamming effectiveness schematic diagram of number of package grain signal generating circuit.
Specific implementation mode
Below in conjunction with attached drawing, the invention will be further described.
It is number of package grain signal generating circuit embodiment as shown in Figure 1.In Fig. 1, several signal transducers 100 export several
Inceptive impulse P1；The input of controllable reversible counter 101 is several inceptive impulse P1, sample clock pulse CLK, adds counting amplitude limit
Control signal KU and subtract and count amplitude limit control signal KD, export as amplitude limit stored counts value X1, amplitude limit stored counts value X1 it is upper,
Lower Limit Amplitude is respectively 6,0；Anti-interference threshold selector 103 exports anti-interference threshold value M；The input of ROM memory 102 is amplitude limit
Stored counts value X1 and anti-interference threshold value M is exported as the first set signal SE1, the second set signal RE1 plus is counted amplitude limit control
Signal KU processed controls signal KD with counting amplitude limit is subtracted；The input of rest-set flip-flop 104 is the first set signal SE1 and the second set is believed
Number RE1 exports several for number of package grain signal generating circuit and counts pulse P2；Oscillator 105 exports sample clock pulse
CLK。
Fig. 2 is several signal transducer embodiments, using Omron correlation optoelectronic switch, the model of light projector 201
E3ZG-T61-S；The model E3ZG-T61-S of light-receiving device 202, output end OUT1 are defeated using NPN triode open collector
Go out, resistance R201 is its collector resistance, and several inceptive impulse P1 are exported from the ends OUT1 of light-receiving device 202.In Fig. 2 ,+VCC is
The power supply of optoelectronic switch, GND are publicly.Several signal transducers can also use other correlation optoelectronic switches or light
The pulse output form of curtain sensor, optoelectronic switch or picking sensor can also be the output type of other forms.Several letters
Number sensor, which is mounted on, to be counted by several on the channel that products pass through；The channel can be single-row object conveying tape channel,
Can be that slope before object packaging tumbles channel or falls channel, etc..
Fig. 3 is the embodiment of controllable reversible counter.In Fig. 3, T triggers FF1, FF2, FF3 and NOT gate FN1, with door
FA4, FA5, FA6, FA7 or door FO1, FO2 form forward-backward counter, and NAND gate FA1, FA2, FA3 form amplitude limit control circuit,
They collectively constitute controllable reversible counter；The triggering input CP of T triggers FF1, FF2, FF3 are that failing edge is effective.Several
The level state of inceptive impulse P1 includes high level and low level, in Fig. 3 embodiments, the high level of P1, low level state difference
To add tally control state, subtracting tally control state.It is respectively to subtract tally control that the high level of P1, low level state, which can also be enabled,
State plus tally control state.
In the forward-backward counter input of Fig. 3, CE is exported from amplitude limit control circuit, x11, x12 and its rp input signal
Same phase from T triggers FF1, FF2 and reversed-phase output；Several inceptive impulse P1 and sample clock pulse CLK are from controllable
Outside forward-backward counter；CE is the enabled input terminal of forward-backward counter, and the input terminal that P1 is connected to is the plus-minus control of forward-backward counter
Input terminal processed.As CE=0, all output is 0 with door FA4, FA5, FA6, FA7, makes or door FO1, FO2 whole output is 0,
The T input terminals all 0 of FF1, FF2, FF3, forward-backward counter keep output constant.When CE=1, P1 are 1, T triggers FF1
T input terminals be 1, become T ' triggers；P1 makes to open with door FA4, FA6, and the T input terminals of FF2 are 1, FF3 when x11 is equal to 1
T input terminals x11, x12 simultaneously equal to 1 when be 1, forward-backward counter is operated in synchronous addition count status, you can control it is reversible
Counter is carried out plus is counted in the failing edge of sample clock pulse CLK.When CE=1, P1 are 0, the T input terminals of T triggers FF1
It is 1, becomes T ' triggers；P1 makes to open with door FA5, FA7 by NOT gate FN1, the T input terminals of FF2 are 1 when x11 is equal to 0,
The T input terminals of FF3 are 1 when x11, x12 are equal to 0 simultaneously, and forward-backward counter is operated in synchronous subtraction count state, you can control can
Inverse counter carries out subtracting counting in the failing edge of sample clock pulse CLK.P1 is enabled to be connected to the reversible counting in Fig. 3 by phase inverter
When the add-subtract control input terminal of device, then the high level of P1, low level control respectively controllable reversible counter be in subtract count status,
Add count status.
The input signal of Fig. 3 amplitude limit control circuits add count amplitude limit control signal KU, subtract count amplitude limit control signal KD and
It counts inceptive impulse P1 all to be from outside controllable reversible counter, adds and count amplitude limit control signal KU and subtract counting amplitude limit control
The equal high level of signal KD is effective, i.e. KU carries out plus count amplitude limit when being 1, and KD carries out subtracting counting amplitude limit when being 1.When P1 is 1, KU is
When 1, NAND gate FA1 exports low level, and low level, CE=0 are exported with door FA3；Either when P1 is 0, KD is 1, NAND gate
FA2 exports low level, and low level, CE=0 are exported with door FA3.When CE is 0, controllable reversible counter is in amplitude limit and preserves shape
State, sample clock pulse CLK failing edge without counting.
In Fig. 3, T triggers FF3, FF2, FF1 are only the sample clock pulse CLK's of their input end of clock CP inputs
Whether the failing edge moment is counted and is carried out plus counted still to subtract counting by the state of P1 to control it；CLK it is non-under
For drop along the moment, the variation of P1 does not influence x13, x12, x11 of FF3, FF2, FF1 output.The output of controllable reversible counter is by adopting
The P1 values at sample clock pulses failing edge moment change to control, you can the output and sample clock pulse for controlling forward-backward counter decline
Sampled value along moment P1 is related, is controlled by the sampled value of sample clock pulse failing edge moment P1.Controllable reversible counter
Output can also be changed by the P1 values of sample clock pulse rising edge time to control.
T triggers in Fig. 3 can use JK flip-flop or d type flip flop to constitute, for example, J, K by JK flip-flop are defeated
It is in parallel as T input terminals to enter end.Controllable reversible counter can also use the forward-backward counters combination doors such as 74HC191, CD4516
Circuit forms.
Fig. 4 is anti-interference threshold selector and ROM memory embodiment.Anti-interference threshold selector is by resistance R91, R90
It is formed with threshold value selecting switch K91, K90；+ VCC is power supply, and GND is publicly.In Fig. 4, anti-interference threshold selector is defeated
The anti-interference threshold value M gone out is made of y11, y10；Anti-interference threshold value M values among 0,1,2, the i.e. value of y11, y10 can only be
0,00,1 or 1,0, selection setting is carried out by threshold value selecting switch K91, K90.Anti-interference threshold selector
Can pull-up resistor be added by multidigit binary system toggle switch BCD toggle switch or multiple regular taps, or
It is multiple pull-up resistors and short circuit point that control 0,1 exports and other can export the electricity of multidigit binary system setting value
Road forms.
In Fig. 4, ROM device FR1 forms ROM memory.The function of ROM memory is to tire out anti-interference threshold value M and amplitude limit
Product count value X1 is inputted as address signal, and the first set signal SE1 and the second set signal RE1 are exported as data；ROM is deposited
Reservoir determines the first set letter of output according to the anti-interference threshold value M currently inputted and the size of amplitude limit stored counts value X1
Whether number SE1 and the second set signal RE1 are effective respectively；According to the size of amplitude limit stored counts value X1, amplitude limit is determined plus counted
Control signal KU and subtract whether count amplitude limit control signal KD effective respectively.
FR1 has 5 bit address to input, i.e. the address input end A4-A0 of FR1 in Fig. 4；FR1 has 4 data output ends, i.e. Fig. 4
Data output end D3, D2, D1, D0 of middle FR1.If address input end A2, A1, A0 of FR1 distinguish input saturation stored counts value
X13, x12, x11 of X1, address input end A4, A3 input y11, y10 of anti-interference threshold value M, the data output end of FR1 respectively
D3, D2, D1, D0 be respectively plus count amplitude limit control signal KU, subtract count amplitude limit control signal KD, the first set signal SE1 and
Second set signal RE1, then the content of each address location is shown in Table 1 in FR1.
Table 1ROM Memory Storage Unit contents
In table 1, the first set signal SE1 and the second set signal RE1 of D1, D0 output are that high level is effective.With ROM
In memory for storage unit 01010, the parts anti-interference threshold value M in memory unit address are 01, therefore the numerical value of M is 1；It deposits
Amplitude limit stored counts value part in storage unit address is 010, therefore amplitude limit stored counts value X1 is 2；Due to amplitude limit stored counts
Value X1 is unsatisfactory for the condition more than or equal to 6-M, therefore D1=0；Since amplitude limit stored counts value X1 is unsatisfactory for the item less than or equal to M
Part, therefore D0=0.Again by taking storage unit in ROM memory 10101 as an example, the numerical value of M is 2, and amplitude limit stored counts value X1 is equal to
5；Since amplitude limit stored counts value X1 meets the condition more than or equal to 6-M, D1=1；Not due to amplitude limit stored counts value X1
Meet the condition less than or equal to M, therefore D0=0.
When anti-interference threshold value M is 0, y11, y10 0,0 of address A4, A3 input, at this point, working as amplitude limit stored counts value
When X1 is less than or equal to 0, output RE1 is high level, and otherwise RE1 is low level, in table 1, ability when only address A4-A0 is 00000
Meet this condition；When amplitude limit stored counts value X1 is more than or equal to 6, output SE1 is high level, and otherwise SE1 is low level, table 1
In, address A4-A0 meets this condition when being 00110；In addition, when the X1 outputs of amplitude limit stored counts value are transfinited, i.e. when X1 is equal to 7,
Also output SE1 is high level.
When anti-interference threshold value M is 1, y11, y10 0,1 of address A4, A3 input, at this point, include the state that transfinites of X1,
When amplitude limit stored counts value X1 is more than or equal to 5, output SE1 is high level, and otherwise SE1 is low level；In table 1, address A4-A0
Meet this condition when being 01101,01110,01111；When amplitude limit stored counts value X1 is less than or equal to 1, output RE1 is high electricity
Flat, otherwise RE1 is low level, and in table 1, address A4-A0 meets this condition when being 010000,01001.
When anti-interference threshold value M is 2, y11, y10 1,0 of address A4, A3 input, at this point, working as amplitude limit stored counts value
When X1 is more than or equal to 4, output SE1 is high level, and otherwise SE1 is low level, in table 1, share 10100 in the A4-A0 of address,
10101,10110,10111 etc. 4 inputs meet this condition；When amplitude limit stored counts value X1 is less than or equal to 2, output RE1 is
High level, otherwise RE1 is low level, in table 1,10000,10001,10010 etc. 3 inputs is shared in the A4-A0 of address and meet this
Condition.
Under normal circumstances, the M values among 0,1,2.It, i.e., will be anti-dry to avoid when M is set as 3 by setting M mistimings
Disturb threshold value selecting switch K91, K90 in threshold selector it is all off when, there is unpredictable situation in system, in determination
In ROM memory when memory cell content, the case where can M being accidentally set as 3 is 0 as M, in being either 1 or being 2
One kind be determined.For example, when M is accidentally set as 3, handled as the case where M=2；To be deposited in ROM memory
For storage unit 11010, the parts anti-interference threshold value M in memory unit address are the 2 high of address, therefore the numerical value of M is accidentally set as
3, take M=2；Amplitude limit stored counts value part in memory unit address is low 2 of address, X1 2；It is accumulated and is counted due to amplitude limit
Numerical value X1 is unsatisfactory for the condition more than or equal to 6-M, therefore D1=0；It is less than or equal to the item of M due to meeting amplitude limit stored counts value X1
Part, therefore D0=1.When the mistake facilities for considering M, high 2 of ROM memory include 00,01,10,11 kind of situation when, make altogether
With 32 storage units in ROM memory, that is, include 5 corresponding all units of binary address input.
When D1, D0 content reverse phase of each storage unit storage in table 1, i.e., 0 is become 1,1 change 0, the first set signal of output
SE1 and the second set signal RE1 is that low level is effective.
The D3 of ROM outputs is plus counts amplitude limit control signal KU, and the KU high level of embodiment is effective, when amplitude limit stored counts
When value X1 is more than or equal to 6, the content of corresponding storage element is 1, is otherwise 0；The D2 of ROM outputs is to subtract to count amplitude limit control signal
KD, KD high level are effective, and when amplitude limit stored counts value X1 is equal to 0, the content of corresponding storage element is 1, is otherwise 0.When KU,
It, only need to be by the content reverse phase of each storage unit storage of corresponding D3, D2 when KD low levels are effective.
The two of each binary digit of anti-interference threshold value M and each binary digit of amplitude limit stored counts value and ROM memory into
Arbitrary one-to-one relationship may be used in correspondence of the address processed between everybody.Taking the embodiment as an example, can by the y11 of M,
Y10 and address input end A1, A0 are corresponding respectively, and x13, x12, x11 and address input end A4, A3, A2 of X1 are corresponded respectively；
It is either that y11, y10 of M and address input end A1, A0 is corresponding respectively, x11, x12, x13 and address input end A4, A3 of X1,
A2 is corresponded respectively；Either one by one by y11, x11, x12, y10, x13 and address input end A4, A3, A2, A1, A0 difference
It is corresponding, etc..Only still need binary sequence y11, y10 according to input at this time to determine the value of M, according to the two of input
System sequence x13, x12, x11 determines the value of X1, determines the content of respective memory unit further according to M, X1.
Fig. 5 is rest-set flip-flop embodiment.In Fig. 5, nor gate FO3, FO4 forms rest-set flip-flop, the first set signal SE1 and
The second equal high level of set signal RE1 is effective；First set signal SE1 is the set signal of rest-set flip-flop, the second set signal
RE1 is the reset signal of rest-set flip-flop；Several count pulse and are exported from the in-phase output end or reversed-phase output of rest-set flip-flop.
When SE1 is effective, RE1 is invalid, several exported from in-phase output end FO4 counting pulse P2 are set to 1；SE1 is invalid, RE1 has
When effect, several counting pulse P2 are set to 0；As SE1 and RE1 invalid, the several states for counting pulse P2 are constant.Several meters
Rapid pulse rushes P2 and can also be exported from reversed-phase output, i.e. nor gate FO3 output ends.Rest-set flip-flop can also use other forms
Rest-set flip-flop.
As it can be seen from table 1 since anti-interference threshold value M is the nonnegative integer less than 3, the first set signal SE1 and second
Set signal RE1 is it is not possible that while effectively, therefore, the output of rest-set flip-flop is not in the uncertain situation of logic state.
Fig. 6 is oscillator embodiment.In Fig. 6, CMOS NOT gates FN2 and FN3, resistance R97, capacitance C97 form multi-harmonic-oscillations
Device, sample clock pulse CLK export from FN3 output ends, and the frequency of CLK changes by adjusting the value of resistance R97, capacitance C97.
Oscillator can also use other kinds of multivibrator.
Fig. 7 is the anti-jamming effectiveness schematic diagram of number of package grain signal generating circuit.If anti-interference threshold value M selections 1, work as amplitude limit
When stored counts value X1 is more than or equal to 5, SE1 is effective, and several counting pulse P2 are set to 1；When amplitude limit stored counts value X1 is less than
When equal to 1, RE1 is effective, and several counting pulse P2 are set to 0；When amplitude limit stored counts value X1 be more than 1 and less than 5 when, SE1 and
RE1 is invalid, and several count pulse P2 and maintain state constant.It is initial that 15 sample clock pulse CLK logarithm grains are given in Fig. 7
The sampled value P1* of pulse P1, and obtain several count pulse P2.Sampled value P1* is sample clock pulse CLK counted edges
When number inceptive impulse P1 value；Controllable reversible counter is controlled respectively to sampling clock by 2 kinds of states of several inceptive impulses
Pulse CLK is carried out plus is counted or subtract counting, is substantially by number inceptive impulse P1 when sample clock pulse CLK counted edges
Value controls controllable reversible counter and carries out plus count or subtract counting to sample clock pulse CLK respectively.If CLK in the figure 7
The 6 P1* sampled values obtained before sampled point 1 are 0, and it is 0 that several, which count pulse P2,.In Fig. 7, several inceptive impulse P1 exist
To there is positive pulse interference after sampled point 3 before the sampled point 2 of CLK, P1* is caused to be done in sampled point 2, the sampling of sampled point 3
Disturb sampled value 1；Several inceptive impulse P1 CLK sampled point 4 to occurring positive narrow pulse interference between sampled point 5, but this is just
Narrow pulse width is less than the sampling period and between 2 sampled point, does not influence the sampled result of P1*, i.e. sampling process is automatic
The positive narrow pulse interference is filtered out；Several inceptive impulse P1 start to become 1 from 0 after the sampled point 7 of CLK, become during 1 from 0
There are 2 edge tremblings, sampled point 8, sampled point 9 value be respectively 1,1, the 1st after sampled point 7 time edge trembling also by
Sampling process filters out automatically.It is tired in sampled value P1*, the amplitude limit that sampled point 1 to the sampled point 15 of clock pulses CLK obtains in Fig. 7
Product count value X1 sum number grains count pulse P2 and are shown in Table 2.
Sampled value P1*, the amplitude limit stored counts value X1 sum number grains of 2 sampled point 1-15 of table counts pulse P2
The case where observing sampled point in table 2, in sampled point 1-2, X1 is effective less than or equal to 1, RE1, and SE1 is invalid, and P2 is set to
It is 0；In sampled point 3, X1 is more than 1 and less than 5, and SE1, RE1 are invalid, and P2 is maintained 0；It is less than or equal to 1 in sampled point 4-8, X1,
RE1 is effective, and SE1 is invalid, and P2 is set to 0；It is more than 1 in sampled point 9-11, X1 and less than 5, SE1, RE1 is invalid, and P2 is maintained
0；In sampled point 12-15, X1 is effective more than or equal to 5, SE1, and RE1 is invalid, and P2 is set to 1.Obviously, it is sampled in continuous 6 P1*
In value, until the sampled point 12 of Fig. 7, just meet the condition that amplitude limit stored counts value X1 is more than or equal to 5, the first set signal SE1
Effectively, several count pulse P2 by 0 change 1.Sampled point 5 in table 2, X1 have had reached Lower Limit Amplitude 0, in 6 He of sampled point
7, P1*=0 (P1=0 i.e. at this time), X1 also no longer carry out subtracting counting, and X1 is maintained Lower Limit Amplitude 0；Sampled point in table 2
13, X1 have had reached upper limit magnitude 6, and in sampled point 14 and 15, P1*=1 (P1=1 i.e. at this time), X1 is also no longer added
It counts, X1 is maintained upper limit magnitude 6.
What Fig. 7 was provided is that anti-positive pulse of the number of package grain signal generating circuit when several inceptive impulse P1 are 0 interferes effect
Fruit and several inceptive impulse P1 become 1 condition and process from 0.Number of package grain signal generating circuit is in several inceptive impulses
Anti- negative pulse interference effect and several inceptive impulse P1 when P1 is 1 become 0 condition and process from 1, with several initial arteries and veins
Rush P1 be 0 when anti-positive pulse interference effect and several inceptive impulse P1 become from 01 condition it is identical as process.When being located at
6 sampled values of CLK logarithm grain inceptive impulses P1 are 1 before the sampled point 31 of clock CLK, and it is 1 that several, which count pulse P2,
Sampled value P1*, the amplitude limit stored counts value X1 sum number grains counting pulse P2 that sampled point 31 to sampled point 45 obtains are shown in Table 3.
Sampled value P1*, the amplitude limit stored counts value X1 sum number grains of 3 sampled point 31-45 of table counts pulse P2
The case where observing sampled point in table 3, in sampled point 31-32, X1 is effective more than or equal to 5, SE1, and RE1 is invalid, P2 quilts
It is set to 1；In sampled point 33, X1 is more than 1 and less than 5, and SE1, RE1 are invalid, and P2 is maintained 1；It is more than in sampled point 34-38, X1
Effective equal to 5, SE1, RE1 is invalid, and P2 is set to 1；It is more than 1 in sampled point 39-41, X1 and less than 5, SE1, RE1 is invalid, P2
It is maintained 1；In sampled point 42-45, X1 is effective less than or equal to 1, RE1, and SE1 is invalid, and P2 is set to 0.Sampled point in table 3
43, X1 have had reached Lower Limit Amplitude 0, and in sampled point 44 and 45, P1*=0 (P1=0 i.e. at this time), X1 is also no longer subtracted
It counts, X1 is maintained Lower Limit Amplitude 0.
In the present embodiment, it is same phase relation between several counting pulse P2 and several inceptive impulse P1.If by controllable
The function of forward-backward counter is changed to：When P1=1, controllable reversible counter carries out subtracting counting；When P1=0, controllable reversible counter
It carries out plus counts, be then inverted relationship between several counting pulse P2 and several inceptive impulse P1.Either in Figure 5 by several
It counts pulse P2 to be changed to export from nor gate FO3, then function is changed into, and when SE1 is effective, RE1 is invalid, pulse is counted by several
P2 is set to 0；When SE1 is invalid, RE1 is effective, several counting pulse P2 are set to 1；As SE1 and RE1 invalid, several countings
The state of pulse P2 is constant；It is inverted relationship between several at this time counting pulse P2 and several inceptive impulse P1.If simultaneously into
The above-mentioned modification of row is then same phase relation between several counting pulse P2 and several inceptive impulse P1.
For being same phase relation between several count pulse P2 and several inceptive impulse P1, from table 2, table 3 and circuit
Operation principle is it may be concluded that since controllable reversible counter has cumulative effect, when the sampled value of several inceptive impulse P1
When 1 quantity is more than 0 quantity within a period of time, amplitude limit stored counts value X1 can tend to increase, and X1 is made to be more than or equal to 6-M
And several counting pulse P2 are set to 1；When several inceptive impulse P1 sampled value within a period of time 0 quantity more than 1
When quantity, amplitude limit stored counts value X1 can tend to reduce, and so that X1 is less than or equal to M and several counting pulse P2 are set to 0；The characteristic
Make the controllable reversible counter of circuit of the present invention that there are self-startup ability, amplitude limit effect and several inceptive impulse P1 sampled values P1*
In 0, can make controllable reversible counter enter normal clip counting section carry out amplitude limit plus-minus counting.
Since anti-interference threshold value M is the integer more than or equal to 0 and less than 3, the first set signal SE1 and the second set signal
RE1 is it is not possible that while effectively, therefore, the output of rest-set flip-flop is not in the uncertain situation of logic state.
It is described further for being same phase relation between several count pulse P2 and several inceptive impulse P1.Work as number
Grain inceptive impulse P1 makes amplitude limit stored counts value X1 be less than or equal to M, after several counting pulse P2 are set to 0, as long as amplitude limit accumulation meter
Numerical value X1 is always less than M, then several counting pulse P2 will not become 1；When several inceptive impulse P1 make amplitude limit stored counts value X1
More than or equal to 6-M, after several counting pulse P2 are set to 1, as long as amplitude limit stored counts value X1 is always more than 6-M, then several countings
Pulse P2 will not become 0.When P1, P2 are low level, as long as the positive pulse occurred in P1 makes continuously to go out in P1 sampled values
Now it is more than or equal to the value that 6-M are 1, either, occurs the value, etc. that 6-M+1 are 1 in continuous 6-M+2 P1 sampled values,
Positive pulse corresponding with positive pulse in the P1 then can be exported from P2；When P1, P2 are high level, as long as occurring in P1
Negative pulse make in P1 sampled values continuously to occur being more than or equal to the value that 6-M are 0, either, in continuous 6-M+2 P1 sampled values
It is middle the value, etc. that 6-M+1 are 0 occur, then it can export negative pulse corresponding with negative pulse in the P1 from P2.At the beginning of several
After initial pulse P1 becomes 1 from 0, several count pulse P2 and need amplitude limit stored counts value X1 adding by several sampling pulse periods
Count delay can just make amplitude limit stored counts value X1 be more than or equal to 6-M, P2 is set 1；When several inceptive impulse P1 become 0 from 1
Afterwards, several counting pulse P2 need amplitude limit stored counts value X1 to subtract count delay by several sampling pulse periods, can just make
Amplitude limit stored counts value X1 is less than or equal to M, and P2 is set to 0.When M values are smaller, several count pulse P2 and become 1 from 0 and become 0 from 1
Condition it is harsher, the anti-jamming effectiveness of circuit is more preferable, but several count pulse P2 prolonging relative to several inceptive impulse P1
The slow time is bigger；Conversely, when M values become larger, the anti-jamming effectiveness of circuit is deteriorated, but several count pulse P2 relative to several
The delay time of inceptive impulse P1 becomes smaller.
The period of sample clock pulse will be according to the pulse width of counting inceptive impulse P1, pace of change and disturbing pulse
Width determines.If for example, several inceptive impulse P1 pulse width at least 12ms on certain packaging production line, shaking interference is logical
Often it is no more than 1/10th of several inceptive impulse P1 pulse widths, it is thereby possible to select the period of sample clock pulse is 1ms
Left and right.
Controllable reversible counter, ROM memory, anti-interference threshold selector, RS are touched in number of package grain signal generating circuit
PAL, GAL, CPLD, FPGA may be used in whole partial function in hair device, oscillator or other are programmable
Logical device, logic unit are realized.
It is the routine techniques that those skilled in the art are grasped in addition to the technical characteristic described in specification.
Claims (8)
1. a kind of number of package grain signal generating method, it is characterised in that：
Amplitude limit control signal is counted by the level state and adding of several inceptive impulses, subtracts that count amplitude limit control signal control reversible
Clip counting device be in plus count status, either in subtract count status or be in amplitude limit hold mode；Reversible clip counting
The output of device is the amplitude limit stored counts value counted to sample clock pulse；
Whether 6-M is more than or equal to amplitude limit stored counts value by ROM memory and whether amplitude limit stored counts value is less than or equal to M
The signal for being differentiated, and generating several counting impulse level states of control goes to control the level state of several counting pulses；
The amplitude limit stored counts value is binary count value；The Lower Limit Amplitude of the amplitude limit stored counts value is 0, upper limit magnitude
It is 6；The M is anti-interference threshold value, and M is the integer more than or equal to 0 and less than or equal to 2.
2. number of package grain signal generating method according to claim 1, it is characterised in that：When the level of several inceptive impulses
State is when adding tally control state and counting amplitude limit being added to control invalidating signal, and controllable reversible counter, which is in, adds count status；
When the level state of several inceptive impulses be subtract tally control state and subtract count amplitude limit control invalidating signal when, controllable reversible meter
Number device, which is in, subtracts count status；Otherwise controllable reversible counter is in amplitude limit hold mode.
3. number of package grain signal generating method according to claim 2, it is characterised in that：By ROM memory according to amplitude limit
Whether stored counts value reaches Lower Limit Amplitude counts amplitude limit control signal to generate to subtract, when amplitude limit stored counts value is equal to 0,
It is effective that ROM memory exported subtracts counting amplitude limit control signal；Whether reached according to amplitude limit stored counts value by ROM memory or
Person generates plus is counted more than upper limit magnitude amplitude limit and controls signal, when amplitude limit stored counts value is more than or equal to 6, ROM memory
Output adds counting amplitude limit control signal effective.
4. number of package grain signal generating method according to claim 3, it is characterised in that：The anti-interference threshold value M is two
Binary data；The address input of the ROM memory is made of amplitude limit stored counts value and anti-interference bis- parts threshold value M, four
Data output respectively the first set signal, the second set signal add to count amplitude limit control signal and subtract to count amplitude limit and control and believe
Number；The signal for the several counting impulse level states of control that ROM memory generates is the first set signal and the second set signal.
5. number of package grain signal generating method according to claim 4, it is characterised in that：If the first set signal and second
The equal high level of set signal effectively and is respectively exported by the data output end D1 and D0 of ROM memory, is deposited in the ROM memory
The determination method of storage unit content D1 and D0 is,
1. determining M according to the importations anti-interference threshold value M in memory unit address；
2. determining amplitude limit stored counts value according to the amplitude limit stored counts value part in memory unit address；
3. when amplitude limit stored counts value is more than or equal to 6-M, D1=1, otherwise, D1=0；When less than or equal to M, D0=1 is no
Then, D0=0.
6. number of package grain signal generating method according to claim 4, it is characterised in that：If the first set signal and second
The equal low level of set signal effectively and is respectively exported by the data output end D1 and D0 of ROM memory, is deposited in the ROM memory
The determination method of storage unit content D1 and D0 is,
(1) M is determined according to the importations anti-interference threshold value M in memory unit address；
(2) amplitude limit stored counts value is determined according to the amplitude limit stored counts value part in memory unit address；
(3) when amplitude limit stored counts value is more than or equal to 6-M, D1=0, otherwise, D1=1；When less than or equal to M, D0=0 is no
Then, D0=1.
7. the number of package grain signal generating method according to any one of claim 4-6, it is characterised in that：First set is believed
Number be rest-set flip-flop set signal, the second set signal be rest-set flip-flop reset signal；Several count pulse and are triggered from RS
The in-phase output end or reversed-phase output of device export.
8. the number of package grain signal generating method according to any one of claim 1-6, it is characterised in that：Reversible amplitude limit meter
Number device is made of the forward-backward counter and amplitude limit and add-subtract control circuit inputted with single clock；The forward-backward counter, which has, to be added
Down control input terminal and enabled input terminal.
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