CN107943184A - A kind of power supply generator on intelligent recognition chip - Google Patents
A kind of power supply generator on intelligent recognition chip Download PDFInfo
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- CN107943184A CN107943184A CN201711374826.4A CN201711374826A CN107943184A CN 107943184 A CN107943184 A CN 107943184A CN 201711374826 A CN201711374826 A CN 201711374826A CN 107943184 A CN107943184 A CN 107943184A
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- voltage
- reference voltage
- pmos tube
- drain electrode
- nmos tube
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/561—Voltage to current converters
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- Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Radar, Positioning & Navigation (AREA)
- Automation & Control Theory (AREA)
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Abstract
The invention discloses the power supply generator on a kind of intelligent recognition chip, comprising:Biasing circuit module, it is powered by voltage RFVDD and produces a reference voltage VREF1;LDO modules, its input terminal are connected to biasing circuit module, switch to voltage VDD with by the voltage RFVDD;BGR modules, it is connected to LDO modules, and is powered by voltage VDD and produce a reference voltage VREF2;Voltage comparison module, for comparison reference voltage VREF1 and voltage VREF2, exports corresponding low and high level;Voltage switching module, for exporting corresponding reference voltage according to the corresponding low and high level selection of output, and will export corresponding reference voltage and send into LDO modules.The present invention can ensure that under various operating conditions, stable and accurate supply voltage can be produced, so that other modules provide stable working power to chip.
Description
Technical field
The invention belongs to the technical field of power circuit in Analogous Integrated Electronic Circuits, on more particularly to a kind of intelligent recognition chip
Power supply generator.
Background technology
In traditional power supply structure, it can be set due to power supply structure unreasonable and cause to power on failure, so as to can not produce
Correct supply voltage value.As shown in Figure 1, RFVDD is after the power is turned on, supply voltage VDD is leapt high, so that BGR work produces
VREF, then produces accurately vdd voltage by VREF again.The defects of its is potential is that the time that PM1 pipes are opened falls short of,
Cause BGR not have enough time also producing stable VREF voltages, so as to lead to not produce desired supply voltage value, in addition compare
Two input terminal VREF values and electric resistance partial pressure value compared with device have certain fluctuation, cause the also not steady timing comparator of voltage with regard to defeated
Go out and close PMOS, stable supply voltage value can not be obtained by again resulting in.Traditional this power supply structure can not be complete in a word
Its function is all correct during guarantee powers on, its job stability is also easier to be influenced be subject to technique.
The content of the invention
The object of the present invention is to provide the power supply generator on a kind of intelligent recognition chip, ensure in various operating conditions
Under, stable and accurate supply voltage can be produced, so that other modules provide stable working power to chip.
In order to realize the above object the present invention is achieved by the following technical solutions:
A kind of power supply generator on intelligent recognition chip, its main feature is that, comprising:
Biasing circuit module, it is powered by voltage RFVDD and produces a reference voltage VREF1;
LDO modules, its input terminal are connected to biasing circuit module, switch to voltage VDD with by the voltage RFVDD;
BGR modules, it is connected to LDO modules, and is powered by voltage VDD and produce a reference voltage VREF2;
Voltage comparison module, for comparison reference voltage VREF1 and voltage VREF2, exports corresponding low and high level;
Voltage switching module, for exporting corresponding reference voltage according to the corresponding low and high level selection of output, and will output pair
The reference voltage answered is sent into LDO modules.
The biasing circuit module includes:Capacitance C1, the first NMOS tube, the second NMOS tube, the 3rd NMOS tube, the 4th
NMOS tube, the 5th NMOS tube, the first PMOS tube, the second PMOS tube, the 3rd PMOS tube and resistance R1;
Capacitance C1 one end input voltage RFVDD, the other end are connected to the drain electrode of the first NMOS tube and the second NMOS tube
Grid;
The second NMOS tube drain electrode is connected to the drain electrode of the 4th NMOS tube;
The first PMOS tube source electrode input voltage RFVDD, its drain be connected to the 3rd NMOS tube drain electrode and
Grid;
The grid of second PMOS tube and drain electrode short circuit and the drain electrode of the 4th NMOS tube is connected to, the grid connection of the second PMOS tube
In the first PMOS tube grid, the second PMOS tube source electrode is connected to the first PMOS tube source electrode;
The 4th NMOS tube grid is connected to the 3rd NMOS tube grid, the 4th NMOS tube connection resistance R1;
The 3rd PMOS tube grid is connected to the drain electrode of the second PMOS tube, and the 3rd PMOS tube drain electrode is connected to the 5th
The grid of NMOS tube and drain electrode, the 3rd PMOS tube source electrode are connected to the second NMOS tube source electrode.
Reference voltage VREF1 is produced between the drain electrode of 3rd PMOS tube and the drain electrode of the 5th NMOS tube.
The LDO modules include:First comparator, the 4th PMOS tube, resistance R2, resistance R3 and capacitance C2;
The 4th PMOS tube source electrode input voltage RFVDD, drain electrode are connected to resistance R2 one end, and grid is connected to first and compares
The output terminal of device;
The first comparator normal phase input end is connected to the resistance R2 other ends and resistance R3 one end;
Described capacitance C2 one end is connected to resistance R2 one end.
Described BGR modules one end is connected to capacitance C2 one end.
The voltage comparison module includes the second comparator, the first phase inverter and the second phase inverter being sequentially connected;
The second comparator normal phase input end input reference voltage VREF1, its inverting input input reference voltage
VREF2;
If reference voltage VREF1 is higher than reference voltage VREF2, first phase inverter output low level, described second is anti-
Phase device exports high level;
If reference voltage VREF1 is less than reference voltage VREF2, first phase inverter output high level, described second is anti-
Phase device exports low level.
The voltage switching module includes:
5th PMOS tube, its source electrode input reference voltage VREF2, grid are connected to the second inverter output;
6th PMOS tube, its source electrode input reference voltage VREF1, grid are connected to the first inverter output, drain electrode and the 5th
PMOS tube drain electrode is connected;
A reference voltage VREF3 is produced between the drain electrode of 6th PMOS tube and the drain electrode of the 5th PMOS tube.
Compared with prior art, the present invention has the following advantages:
The present invention first produces a reference voltage using rough biasing circuit, so as to produce supply voltage VDD by LDO, so
BGR modules work and produce more accurately reference voltage afterwards, by switching reference voltage, finally produce accurately power supply electricity again
Pressure, so as to complete the process entirely powered on.
Brief description of the drawings
Fig. 1 is power supply structure schematic diagram in the prior art;
Fig. 2 is biasing circuit module, LDO modules and BGR moulds in the power supply generator on a kind of intelligent recognition chip of the present invention
Block structure schematic diagram;
Fig. 3 is the structure diagram of voltage comparison module;
Fig. 4 is the structure diagram of voltage switching module.
Embodiment
Below in conjunction with attached drawing, by describing a preferable specific embodiment in detail, the present invention is further elaborated.
As shown in Fig. 2, the power supply generator on a kind of intelligent recognition chip, comprising:Biasing circuit module, it is by voltage
RFVDD powers and produces a reference voltage VREF1;LDO modules, its input terminal are connected to biasing circuit module, with will be described
Voltage RFVDD switchs to voltage VDD;BGR modules, it is connected to LDO modules, and is powered by voltage VDD and produce a reference voltage
VREF2;Voltage comparison module, for comparison reference voltage VREF1 and voltage VREF2, exports corresponding low and high level;Voltage is cut
Block is changed the mold, for exporting corresponding reference voltage according to the corresponding low and high level selection of output, and will be exported corresponding with reference to electricity
Force feed is into LDO modules.
Above-mentioned biasing circuit module includes:Capacitance C1, the first NMOS tube NM1, the second NMOS tube NM2, the 3rd NMOS tube
NM3, the 4th NMOS tube NM4, the 5th NMOS tube NM5, the first PMOS tube PM1, the second PMOS tube PM2, the 3rd PMOS tube PM3 and electricity
Hinder R1;Capacitance C1 one end input voltage RFVDD, the other end are connected to the drain electrode of the first NMOS tube and the second NMOS tube
Grid;The second NMOS tube drain electrode is connected to the drain electrode of the 4th NMOS tube;The first PMOS tube source electrode input voltage
RFVDD, it, which drains, is connected to the drain and gate of the 3rd NMOS tube;The grid of second PMOS tube and drain electrode are short
Connect and be connected to the drain electrode of the 4th NMOS tube, the grid of the second PMOS tube is connected to the first PMOS tube grid, second PMOS tube
Source electrode is connected to the first PMOS tube source electrode;The 4th NMOS tube grid is connected to the 3rd NMOS tube grid, and the described the 4th
NMOS tube connection resistance R1;The 3rd PMOS tube grid is connected to the drain electrode of the second PMOS tube, the 3rd PMOS tube leakage
Pole is connected to grid and the drain electrode of the 5th NMOS tube, and the 3rd PMOS tube source electrode is connected to the second NMOS tube source electrode.
Reference voltage VREF1 is produced between the above-mentioned drain electrode of the 3rd PMOS tube and the drain electrode of the 5th NMOS tube.
Above-mentioned LDO modules include:First comparator 1, the 4th PMOS tube PM4, resistance R2, resistance R3 and capacitance C2;Institute
The 4th PMOS tube source electrode input voltage RFVDD stated, drain electrode are connected to resistance R2 one end, and grid is connected to the defeated of first comparator
Outlet;The first comparator normal phase input end is connected to the resistance R2 other ends and resistance R3 one end;The capacitance C2 mono-
End is connected to resistance R2 one end.
Described BGR modules one end is connected to capacitance C2 one end, which is common circuit module, herein no longer
Repeat.
As shown in figure 3, the voltage comparison module includes the second comparator 2 being sequentially connected, the first phase inverter 3 and the
Two phase inverters 4;The second comparator normal phase input end input reference voltage VREF1, the input of its inverting input is with reference to electricity
Press VREF2;If reference voltage VREF1 is higher than reference voltage VREF2, first phase inverter output low level, described the
Two phase inverters export high level;If reference voltage VREF1 is less than reference voltage VREF2, the high electricity of first phase inverter output
Flat, described the second phase inverter output low level.
As shown in figure 4, above-mentioned voltage switching module includes:5th PMOS tube, its source electrode input reference voltage VREF2,
Grid is connected to the second inverter output;6th PMOS tube, its source electrode input reference voltage VREF1, grid are connected to first
Inverter output, drain electrode are connected with the drain electrode of the 5th PMOS tube;The 6th PMOS tube drain electrode drains it with the 5th PMOS tube
Between produce a reference voltage VREF3.
During concrete application of the present invention, biasing circuit module is powered by RFVDD, produces rough reference voltage VREF1, at this time
BGR modules do not work also, and reference voltage VREF2 is zero, therefore the first inverter output K1 is low level, the second reverser
Output terminal K2 is high level, and VREF1 is just transferred to VREF3, and first comparator work, a VDD is produced according to the voltage of VREF3
Voltage.After vdd voltage is stablized, BGR modules start to work and produce an accurate reference voltage VREF2, in circuit design,
Need to ensure that VREF2 is than VREF1 high in normal work.After VREF2 stablizes, by the second comparator, K1 becomes high level,
K2 becomes low level, therefore the voltage of reference voltage VREF2 is transmitted to VREF3 again, and final first comparator is adjusted, finally
Vdd voltage produce and settle out according to VERF2.The sequencing that the present invention is produced by voltage is so as to produce final electricity
Source voltage VDD, avoiding generation VDD needs to rely on reference voltage VREF, produces VREF and again relies on VDD.
In biasing circuit module, using capacitance structure as start-up circuit, consumed after circuit start without extracurrent,
Therefore a constant current can be saved, in this angle, is reduction of the overall power consumption of circuit, improves intelligent recognition chip most
Small work field strength.When RFVDD rises, being coupled by capacitance C1, NM2 pipes are opened and drag down the drain electrode of PM2 pipes, so that
Electric current is produced in biasing circuit and is worked normally.After normal work, a reference voltage VREF1 is produced, which opens NM1 again
Pipe, the grid voltage of NM2 pipes is dragged down, so as to complete whole start-up course.In intelligent recognition, general RFVDD voltage ranges
It is 2V-6V.In the design process, it is necessary to emulation by various conditions so that VREF1 magnitudes of voltage are less than VREF2, while basis
The vdd voltage that VREF1 is produced has can be so that BGR normal works.The final reference voltage for producing VDD should be VREF2, so
Vdd voltage could be more accurate.
In LDO circuit, resistance R2 and R3 carries out partial pressure to VDD, and then rear reference voltage is compared, final to cause
VDD stablizes, such as VREF2 magnitudes of voltage are 0.6V, and vdd voltage value needs to be designed as 1.8V, then according to intrinsic standoff ratio, resistance R2 is just
It is twice of resistance R3, in order to save power consumption, it is necessary to which larger resistance value, such as resistance R2 are 2M ohm, and resistance R3 is 1M
Ohm, then the electric current for flowing through two resistance is exactly 600nA.Capacitance C2 and C3 are storage capacitors, are to ensure that RFVDD exists
When input energy can not be provided during Npause, storage capacitor C2 can also provide certain energy to RFVDD, and capacitance C3 can be
VDD provides certain energy so that whole chip will not be resetted since supply voltage is too low.In whole circuit, the first ratio
Supply voltage compared with 1 and second comparator 2 of device is all to have RFVDD to power.
In conclusion the power supply generator on a kind of intelligent recognition chip of the present invention, ensures under various operating conditions,
Stable and accurate supply voltage can be produced, so that other modules provide stable working power to chip.
Although present disclosure is discussed in detail by above preferred embodiment, but it should be appreciated that above-mentioned
Description is not considered as limitation of the present invention.After those skilled in the art have read the above, for the present invention's
A variety of modifications and substitutions all will be apparent.Therefore, protection scope of the present invention should be limited to the appended claims.
Claims (7)
1. the power supply generator on a kind of intelligent recognition chip, it is characterised in that include:
Biasing circuit module, it is powered by voltage RFVDD and produces a reference voltage VREF1;
LDO modules, its input terminal are connected to biasing circuit module, switch to voltage VDD with by the voltage RFVDD;
BGR modules, it is connected to LDO modules, and is powered by voltage VDD and produce a reference voltage VREF2;
Voltage comparison module, for comparison reference voltage VREF1 and voltage VREF2, exports corresponding low and high level;
Voltage switching module, for exporting corresponding reference voltage according to the corresponding low and high level selection of output, and will output pair
The reference voltage answered is sent into LDO modules.
2. the power supply generator on intelligent recognition chip as claimed in claim 1, it is characterised in that the biasing circuit
Module includes:Capacitance C1, the first NMOS tube, the second NMOS tube, the 3rd NMOS tube, the 4th NMOS tube, the 5th NMOS tube, first
PMOS tube, the second PMOS tube, the 3rd PMOS tube and resistance R1;
Capacitance C1 one end input voltage RFVDD, the other end are connected to the drain electrode of the first NMOS tube and the second NMOS tube
Grid;
The second NMOS tube drain electrode is connected to the drain electrode of the 4th NMOS tube;
The first PMOS tube source electrode input voltage RFVDD, its drain be connected to the 3rd NMOS tube drain electrode and
Grid;
The grid of second PMOS tube and drain electrode short circuit and the drain electrode of the 4th NMOS tube is connected to, the grid connection of the second PMOS tube
In the first PMOS tube grid, the second PMOS tube source electrode is connected to the first PMOS tube source electrode;
The 4th NMOS tube grid is connected to the 3rd NMOS tube grid, the 4th NMOS tube connection resistance R1;
The 3rd PMOS tube grid is connected to the drain electrode of the second PMOS tube, and the 3rd PMOS tube drain electrode is connected to the 5th
The grid of NMOS tube and drain electrode, the 3rd PMOS tube source electrode are connected to the second NMOS tube source electrode.
3. the power supply generator on intelligent recognition chip as claimed in claim 2, it is characterised in that the 3rd PMOS
Pipe drains and produces reference voltage VREF1 between the drain electrode of the 5th NMOS tube.
4. the power supply generator on intelligent recognition chip as claimed in claim 1, it is characterised in that the LDO modules
Comprising:First comparator, the 4th PMOS tube, resistance R2, resistance R3 and capacitance C2;
The 4th PMOS tube source electrode input voltage RFVDD, drain electrode are connected to resistance R2 one end, and grid is connected to first and compares
The output terminal of device;
The first comparator normal phase input end is connected to the resistance R2 other ends and resistance R3 one end;
Described capacitance C2 one end is connected to resistance R2 one end.
5. the power supply generator on intelligent recognition chip as claimed in claim 4, it is characterised in that the BGR modules
One end is connected to capacitance C2 one end.
6. the power supply generator on intelligent recognition chip as claimed in claim 1, it is characterised in that the voltage compares
Module includes the second comparator, the first phase inverter and the second phase inverter being sequentially connected;
The second comparator normal phase input end input reference voltage VREF1, its inverting input input reference voltage
VREF2;
If reference voltage VREF1 is higher than reference voltage VREF2, first phase inverter output low level, described second is anti-
Phase device exports high level;
If reference voltage VREF1 is less than reference voltage VREF2, first phase inverter output high level, described second is anti-
Phase device exports low level.
7. the power supply generator on intelligent recognition chip as claimed in claim 6, it is characterised in that the voltage switching
Module includes:
5th PMOS tube, its source electrode input reference voltage VREF2, grid are connected to the second inverter output;
6th PMOS tube, its source electrode input reference voltage VREF1, grid are connected to the first inverter output, drain electrode and the 5th
PMOS tube drain electrode is connected;
A reference voltage VREF3 is produced between the drain electrode of 6th PMOS tube and the drain electrode of the 5th PMOS tube.
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CN201711374826.4A CN107943184A (en) | 2017-12-19 | 2017-12-19 | A kind of power supply generator on intelligent recognition chip |
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CN201711374826.4A CN107943184A (en) | 2017-12-19 | 2017-12-19 | A kind of power supply generator on intelligent recognition chip |
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Citations (5)
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---|---|---|---|---|
JP2003007837A (en) * | 2001-06-27 | 2003-01-10 | Denso Corp | Reference voltage circuit |
CN101568893A (en) * | 2005-09-19 | 2009-10-28 | 德克萨斯仪器股份有限公司 | Soft-start circuit and method for power-up of an amplifier circuit |
CN101763139A (en) * | 2010-02-05 | 2010-06-30 | 上海宏力半导体制造有限公司 | Band-gap reference voltage-stabilizing circuit |
CN104714591A (en) * | 2015-03-26 | 2015-06-17 | 厦门新页科技有限公司 | Reference voltage circuit |
CN104932601A (en) * | 2015-06-26 | 2015-09-23 | 华南理工大学 | Band-gap reference voltage source having high power supply rejection ratio |
-
2017
- 2017-12-19 CN CN201711374826.4A patent/CN107943184A/en active Pending
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003007837A (en) * | 2001-06-27 | 2003-01-10 | Denso Corp | Reference voltage circuit |
CN101568893A (en) * | 2005-09-19 | 2009-10-28 | 德克萨斯仪器股份有限公司 | Soft-start circuit and method for power-up of an amplifier circuit |
CN101763139A (en) * | 2010-02-05 | 2010-06-30 | 上海宏力半导体制造有限公司 | Band-gap reference voltage-stabilizing circuit |
CN104714591A (en) * | 2015-03-26 | 2015-06-17 | 厦门新页科技有限公司 | Reference voltage circuit |
CN104932601A (en) * | 2015-06-26 | 2015-09-23 | 华南理工大学 | Band-gap reference voltage source having high power supply rejection ratio |
Non-Patent Citations (2)
Title |
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张建华: "《数字电子技术》", 31 October 1999, 机械工业出版社 * |
隋修武: "《机械电子工程原理与系统设计》", 31 January 2014, 国防工业出版社 * |
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Address after: 201203 No. 12, Lane 647, Songtao Road, Shanghai China (Shanghai) Free Trade Pilot Area, Pudong New Area, Shanghai Applicant after: Juchen Semiconductor Co., Ltd. Address before: 201203 No. 12, Lane 647, Songtao Road, Zhangjiang High-tech Park, Pudong New Area, Shanghai Applicant before: Giantec Semiconductor Inc. |
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Application publication date: 20180420 |