CN107888181B - Programmable voltage bias generator and IC chip comprising it - Google Patents
Programmable voltage bias generator and IC chip comprising it Download PDFInfo
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- CN107888181B CN107888181B CN201711088269.XA CN201711088269A CN107888181B CN 107888181 B CN107888181 B CN 107888181B CN 201711088269 A CN201711088269 A CN 201711088269A CN 107888181 B CN107888181 B CN 107888181B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/017581—Coupling arrangements; Interface arrangements programmable
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/017545—Coupling arrangements; Impedance matching circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
- H03K19/018557—Coupling arrangements; Impedance matching circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
- H03K19/018585—Coupling arrangements; Interface arrangements using field effect transistors only programmable
Abstract
The present invention discloses a kind of programmable voltage bias generator and the IC chip including it, the generator includes register group, voltage offset electric circuit, voltage offset electric circuit includes the first power supply, second source, first resistor array, second resistance array, first switch array, second switch array, two electric resistance arrays are connected in series between two power supplys, the output end of register group is connect with the control terminal of two switch arrays respectively, the switch unit of first switch array is connected in parallel on the both ends of the resistance unit of first resistor array respectively, the switch unit of second switch array is connected in parallel on the both ends of the resistance unit of second resistance array respectively, commonly connected place between first resistor array and second resistance array is the output of generator；By above-mentioned bias voltage generator, reduce the quantity of register cell, switch unit and resistance unit, when being applied to IC chip, the area of encapsulation of integrated circuit itself, save the cost can be reduced.
Description
Technical field
The present invention relates to technical field of integrated circuits, in particular to a kind of programmable voltage bias generator and including its
IC chip.
Background technique
It is real that programmable voltage bias generator in existing IC chip generallys use cascade pole amplifier
Existing, according to the digit of programmable binary digital signal, the quantity of the switching tube needed is corresponding with digit, and usual n can
The quantity of register required for program voltage bias generator is n, and the quantity of switching tube is also n, works as programmable voltage
The digit of bias generator is bigger, then the register number and switching tube quantity needed is increase accordingly, this allows for integrated circuit
The package area of chip increases accordingly, and cost is relatively high.
Summary of the invention
The main object of the present invention is to propose a kind of programmable voltage bias generator, it is intended to reduce register and switch
Quantity, so that the area of the IC chip of application reduces.
To achieve the above object, programmable voltage bias generator proposed by the present invention, including register group, voltage bias
Circuit, the voltage offset electric circuit include the first power supply, second source, first resistor array, second resistance array, first switch
Array, second switch array, the first resistor array and second resistance array are connected in series in the first power supply and second source
Between, the output end of the register group is connect with the control terminal of first switch array, second switch array respectively, and described first
The switch unit of switch arrays is connected in parallel on the both ends of the resistance unit of first resistor array respectively, and the second switch array is opened
Close the both ends that unit is connected in parallel on the resistance unit of second resistance array respectively, the first resistor array and second resistance array it
Between commonly connected place be generator output.
Preferably, the register group is made of the register cell of several output binary digital signals.
Preferably, the first resistor array, second resistance array are by several resistance lists being decreased or increased in ratio
Member series connection is formed, and the resistance unit quantity of first resistor, the resistance unit quantity of second resistance and the quantity of register cell
It is all the same.
Preferably, the minimum resistance end of the first resistor array is connected with the output end of the first power supply, and described first
The maximum resistance value end of electric resistance array is connect with the maximum resistance value end of second resistance array, the minimum of the second resistance array
The connection of the output end of resistance value end and second source.
Preferably, it is additionally provided between the minimum resistance end of the first resistor array and the output end of the first power supply
First resistor is additionally provided with the second electricity between the minimum resistance end of the second resistance array and the output end of second source
Resistance.
Preferably, the first switch array, second switch array are sequentially connected with by several metal-oxide-semiconductor units, the
The metal-oxide-semiconductor unit of one switch arrays is corresponding with the resistance unit of first resistor array and quantity is identical, the MOS of second switch array
Pipe unit is corresponding with the resistance unit of second resistance array and quantity is identical；The grid of each metal-oxide-semiconductor unit is posted with corresponding respectively
The output end of storage unit connects, and the source electrode and drain electrode of each metal-oxide-semiconductor unit is connected with the both ends of corresponding resistance unit respectively；The
The on state of the on state of the metal-oxide-semiconductor unit of one switch arrays metal-oxide-semiconductor unit corresponding with second switch array is opposite.
Preferably, the first switch array is made of several PMOS tube units, and second switch array is by several NMOS tubes
Unit is constituted.
Preferably, the NMOS tube unit is deep N-well metal-oxide-semiconductor, and the body end of each deep N-well metal-oxide-semiconductor is connected to second source
Output end, the deep N-well end of each deep N-well metal-oxide-semiconductor links together.
The present invention also provides a kind of IC chip, which includes programmable voltage bias generator, this is programmable
Voltage bias generator includes register group, voltage offset electric circuit, and the voltage offset electric circuit includes the first power supply, the second electricity
Source, first resistor array, second resistance array, first switch array, second switch array, the first resistor array and second
Electric resistance array is connected in series between the first power supply and second source, the output end of the register group respectively with first switch battle array
The control terminal connection of column, second switch array, the switch unit of the first switch array are connected in parallel on first resistor array respectively
Resistance unit both ends, the switch unit of the second switch array is connected in parallel on the resistance unit of second resistance array respectively
Both ends, the commonly connected place between the first resistor array and second resistance array are the output of generator.
The programmable voltage bias generator of technical solution of the present invention and IC chip including it, the voltage bias
Gate leve bias voltage of the generator for the total grid grade of cascade stage power amplifier generates, the exportable position n two of register group
Binary digits signal, n bit binary number signal constitute 2nKind status number signal, two groups of n switch unit structures of corresponding control
At switch arrays have 2nKind open and-shut mode, and then the electric resistance array of two groups of n resistance units composition is controlled in the first power supply
Partial pressure output between second source also has 2nKind voltage.To pass through n group register, 2n group switch unit and resistance list
Member can be realized 2nKind bias voltage output.For traditional bias voltage generator, if 2 must be realizednKind biased electrical
Pressure output, then need 2nReal register, switch unit and resistance unit.Therefore, it by above-mentioned bias voltage generator, realizes same
Sample may be programmed the bias voltage output of number of bits, reduce the quantity of register cell, switch unit and resistance unit, when
When applied to IC chip, the area of encapsulation of integrated circuit itself, save the cost can be reduced.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
Some embodiments of invention for those of ordinary skill in the art without creative efforts, can be with
The structure shown according to these attached drawings obtains other attached drawings.
Fig. 1 is the functional block diagram of one embodiment of programmable voltage bias generator of the present invention；
Fig. 2 is the electrical block diagram of one embodiment of programmable voltage bias generator of the present invention.
Drawing reference numeral explanation:
| Label | Title | Label | Title |
| 100 | Register group | 700, Vss | Second source |
| 200 | First switch array | 110 | Register cell |
| 300 | Second switch array | 210,310 | Switch unit |
| 400 | First resistor array | 410,510 | Resistance unit |
| 500 | Second resistance array | RX1 | First resistor |
| 600, Vdd | First power supply | RX2 | Second resistance |
The embodiments will be further described with reference to the accompanying drawings for the realization, the function and the advantages of the object of the present invention.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiment is only a part of the embodiments of the present invention, instead of all the embodiments.Base
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts it is all its
His embodiment, shall fall within the protection scope of the present invention.
It is to be appreciated that the directional instruction (such as up, down, left, right, before and after ...) of institute is only used in the embodiment of the present invention
In explaining in relative positional relationship, the motion conditions etc. under a certain particular pose (as shown in the picture) between each component, if should
When particular pose changes, then directionality instruction also correspondingly changes correspondingly.
In addition, the description for being related to " first ", " second " etc. in the present invention is used for description purposes only, and should not be understood as referring to
Show or imply its relative importance or implicitly indicates the quantity of indicated technical characteristic." first ", " are defined as a result,
Two " feature can explicitly or implicitly include at least one of the features.In addition, the technical solution between each embodiment can
It to be combined with each other, but must be based on can be realized by those of ordinary skill in the art, when the combination of technical solution occurs
Conflicting or cannot achieve when, will be understood that the combination of this technical solution is not present, also not the present invention claims protection model
Within enclosing.
The present invention proposes a kind of programmable voltage bias generator.
It is the structural schematic diagram of one embodiment of programmable voltage bias generator of the present invention referring to figs. 1 to 2, Fig. 1；Fig. 2 is
Internal circuit connection schematic diagram in Fig. 1.
In embodiments of the present invention, as described in Figure 1, which includes register group 100, voltage
Biasing circuit, the voltage offset electric circuit include the first power supply 600, second source 700, first resistor array 400, second resistance
Array 500, first switch array 200, second switch array 300, the first resistor array 400 and second resistance array 500
Be connected in series between the first power supply 600 and second source 700, the output end of the register group 100 respectively with first switch
The control terminal connection of array 200, second switch array 300, the switch unit 210 of the first switch array 200 are in parallel respectively
At the both ends of the resistance unit 410 of first resistor array 400, the switch unit 310 of the second switch array 300 is in parallel respectively
Between the both ends of the resistance unit 510 of second resistance array 500, the first resistor array 400 and second resistance array 500
Commonly connected place be generator output.
The programmable voltage bias generator of technical solution of the present invention is used for the total grid grade of cascade stage power amplifier
Gate leve bias voltage generate, register group 100 by several output binary digital signals 110 structure of register cell
At exportable several bit binary number signals control first switch array 200 and second according to the low and high level of digital signal
The open and-shut mode of switch arrays 300, then control first resistor array 400 and second resistance array 500 the first power supply 600 with
Effective partial pressure resistance value of the total resistance value of effective resistance and output end between second source 700, to control the voltage value of output.It is false
If register group 100 includes n register cell 110, then the exportable n bit binary number signal of register group 100, n
Binary digital signal constitutes 2nKind status number signal, the corresponding switch arrays tool for controlling two groups of n switch units 210 and constituting
Have 2nKind open and-shut mode, and then it is electric in the first power supply 600 and second to control the electric resistance array that two groups of n resistance units 410 are constituted
Partial pressure output between source 700 also has 2nKind voltage.To pass through n group register, 2n group switch unit 210 and resistance unit
410, it can be realized 2nKind bias voltage output.For traditional bias voltage generator, if 2 must be realizednKind biased electrical
Pressure output, then need 2nReal register, switch unit 210 and resistance unit 410.Therefore, by above-mentioned bias voltage generator,
It realizes same amount of bias voltage output, reduces the number of register cell 110, switch unit 210 and resistance unit 410
Amount can reduce the area of encapsulation of integrated circuit itself, save the cost when being applied to IC chip.
Specifically, the first resistor array 400, second resistance array 500 are decreased or increased by several in ratio
The series connection of resistance unit 410 is formed, and the number of resistance unit 410 of 410 quantity of resistance unit of first resistor RX1, second resistance RX2
It measures all the same with the quantity of register cell 110.
In the present embodiment, 510 quantity of resistance unit and deposit of first resistor array 400 and second resistance array 500
Quantity and first switch array 200,310 quantity of switch unit of second switch array 300 of device unit 110 are all the same；And the
One electric resistance array 400 is identical as second resistance array 500, is gone here and there by the resistance unit 410 that resistance value equal proportion increases or reduces
Join.In the present embodiment, the equimultiple between adjacent two resistance unit 410 is preferably 2.By such electric resistance array, make
The voltage of bias voltage generator generation is obtained closer to linear change.
Specifically, the minimum resistance end of the first resistor array 400 is connected with the output end of the first power supply 600, institute
The maximum resistance value end for stating first resistor array 400 is connect with the maximum resistance value end of second resistance array 500, second electricity
The minimum resistance end of resistance array 500 is connect with the output end of second source 700.
In the present embodiment, the minimum resistance at the minimum resistance end of first resistor array 400 and second resistance array 500
It is worth end to correspond to, the output end of same register cell 110 is connected to by corresponding two switch unit 210；First resistor battle array
Column 400 and the resistance unit 410 of the similar resistance of second resistance array 500 correspond, and pass through corresponding switch unit
210 are connected to the output end of same register cell 110.Switch unit 210 leads corresponding to similar resistance resistance unit 410
Logical state is on the contrary, therefore, a switch unit 210 being attached thereto can only be connected in the signal that same register cell 110 exports.
I.e. no matter the signal that same register cell 110 exports is high level or low level, in the first power supply 600 and second source
Between 700, the resistance unit 410 of the similar resistance of first resistor array 400 and second resistance array 500 only has access one.
Therefore, the effective resistance value between the first power supply 600 and second source 700 is first resistor array 400 or second resistance array
The sum of the resistance value of 500 resistance unit 510.And the change in resistance that bias voltage output is then second resistance array 500 exists
Obtained by partial pressure between first power supply 600 and second source 700.Therefore, bias voltage is then according to the binary digit of register
Signal intensity and change.
Preferably, between the minimum resistance end of the first resistor array 400 and the output end of the first power supply 600 also
Be provided with first resistor RX1, the second resistance array 500 minimum resistance end and second source 700 output end it
Between be additionally provided with second resistance RX2.
Increase first resistor RX1 between first resistor array 400 and the first power supply 600 and in second resistance array
Increase second resistance RX2 between 500 and second source 700, the resistance of setting first resistor RX1 and second resistance RX2 can be passed through
Value limits the output area of bias voltage.
Preferably, the first switch array 200, second switch array 300 be sequentially connected with by several metal-oxide-semiconductor units and
At, the metal-oxide-semiconductor unit of first switch array 200 is corresponding with the resistance unit 410 of first resistor array 400 and quantity is identical, the
The metal-oxide-semiconductor unit of two switch arrays 300 is corresponding with the resistance unit 510 of second resistance array 500 and quantity is identical；Every MOS
The grid of pipe unit is connected with the output end of corresponding register cell 110 respectively, the source electrode and drain electrode difference of each metal-oxide-semiconductor unit
It is connected with the both ends of corresponding resistance unit 410；The on state and second switch battle array of the metal-oxide-semiconductor unit of first switch array 200
The on state of the corresponding metal-oxide-semiconductor unit of column 300 is opposite.
In the present embodiment, the first switch array 200 is preferably constituted using several PMOS tube units, second switch battle array
Column 300 are preferably constituted using several NMOS tube units.
The PMOS tube unit of first switch array 200 is low level conducting, and the NMOS tube unit of second switch array 300 is
High level conducting.When the binary digital signal that register cell 110 exports is 0, it is connected with the register cell 110
The conducting of PMOS tube unit, NMOS tube disconnect, and the corresponding resistance unit 410 of first resistor array 400 is equivalent to short circuit, second resistance
The corresponding resistance unit 410 of array 500 accesses in the circuit between the first power supply 600 and second source 700.Work as register cell
When the binary digital signal of 110 outputs is 1, the PMOS tube unit being connected with the register cell 110 is disconnected, and NMOS tube is led
Logical, the corresponding resistance unit 410 of second resistance array 500 is equivalent to short circuit, the corresponding resistance unit of first resistor array 400
In circuit between 410 the first power supplys 600 of access and second source 700.Certainly, NMOS can also be used in first switch array 200
Pipe unit is constituted, second switch array 300 is constituted using PMOS tube unit.
Preferably, the NMOS tube unit is deep N-well metal-oxide-semiconductor, and the body end of each deep N-well metal-oxide-semiconductor is connected to second source
The deep N-well end of 700 output end, each deep N-well metal-oxide-semiconductor links together.
Since the conducting resistance of deep N-well NMOS tube is small, then the high value that register cell 110 exports does not have to export very high
Voltage value the NMOS tube can be connected.
Working principle in order to further illustrate the present invention, referring to Fig. 2, using being carried out for triad digital signal
Illustrate, other binary digital signal does not enumerate herein referring to three understandings.
In the present embodiment, register group 100 includes three register cells 110, and first switch array 200 uses three
PMOS tube unit (D11, D12, D13) is constituted, and second switch array 300 uses three NMOS tube unit (D21, D22, D23) structures
At.Set first resistor array 400 and second resistance array 500 three resistance units (R11, R12, R13 and R21, R22,
R23 resistance value) is followed successively by 2 from small to large0x、21x、22The resistance value of x, first resistor RX1 are ax, the resistance value of second resistance RX2
For bx, then the first power supply VddWith second source VssBetween effective resistance value be 20x+21x+22X+ax+bx=(2n-1+a+b)x
=(23-1+a+b)x。
The binary digital signal a total of 2 that three register cells 110 are exported3It is a, i.e. 8 kinds of states, respectively
000,001,010,011,100,101,110,111, when register group 100 is 000 state, then first switch array 200
Three PMOS tube units (D11, D12, D13) are both turned on, three NMOS tube units of second switch array 300 (D21, D22,
D23 it) disconnects, then the resistance unit (R21, R22, R23) of second resistance array 500 accesses in circuit, first resistor array
400 resistance unit (R11, R12, R13) short circuit, at this point, second source VssWith the output V of voltage bias generatoroutBetween
Resistance value it is maximum, be 20x+21x+22X+bx=(2n- 1+b) x=(23- 1+b) x, then obtained by the partial pressure of bias voltage generator
It is maximum:
When register group 100 be 111 state when, then the three of first switch array 200 PMOS tube unit (D11, D12,
D13 it) disconnects, three NMOS tube units (D21, D22, D23) of second switch array 300 are both turned on, then second resistance array
500 resistance unit (R21, R22, R23) short circuit, the resistance unit (R11, R12, R13) of first resistor array 400 access
In circuit, at this point, second source VssWith the output V of voltage bias generatoroutBetween resistance value it is minimum, be bx, then biased electrical
It presses minimum obtained by the partial pressure of generator:
Assuming that a=6, b=8, Vdd=1.8V, Vss=0V, then it can be concluded that Vmax≈ 1.29V, Vmin≈0.69V.Therefore,
The voltage bias generator can export 8 grades of programmable voltages between 0.69V-1.29V, it is only necessary to three register cells 110,6
A switch unit (D11, D12, D13, D21, D22, D23), resistance unit (R11, R12, R13, R21, R22, R23) need can be real
It is existing, compared to 8 grades of voltage programmables that traditional 8 register cells, switch unit, resistance units are just able to achieve, reduce
The quantity of register cell, switch unit and resistance unit therefore, can when the voltage bias generator is applied to integrated chip
Reduce the area of IC chip, save the cost.
The present invention also provides a kind of IC chip, which includes the bias voltage generator, this is partially
The structure, working principle and brought beneficial effect of voltage generator are set, it is no longer superfluous herein referring to above-described embodiment
It states.
The above description is only a preferred embodiment of the present invention, is not intended to limit the scope of the invention, all at this
Under the inventive concept of invention, using equivalent structure transformation made by description of the invention and accompanying drawing content, or directly/use indirectly
It is included in other related technical areas in scope of patent protection of the invention.
Claims (8)
1. a kind of programmable voltage bias generator, which is characterized in that including register group, voltage offset electric circuit, the voltage
Biasing circuit includes the first power supply, second source, first resistor array, second resistance array, first switch array, second switch
Array, the first resistor array and second resistance array are connected in series between the first power supply and second source, the deposit
The output end of device group is connect with the control terminal of first switch array, second switch array respectively, and the first switch array is opened
The both ends that unit is connected in parallel on the resistance unit of first resistor array respectively are closed, the switch unit difference of the second switch array is simultaneously
The both ends of the resistance unit of second resistance array are associated in, it is commonly connected between the first resistor array and second resistance array
Place is the output of generator；
The register group includes n register cell, which exports n bit binary number signal, n bit
Word signal constitutes 2nKind status number signal, the switch arrays that two groups of n switch units of corresponding control are constituted have 2nKind opening and closing shape
State, for controlling partial pressure output tool of the electric resistance array of two groups of n resistance units composition between the first power supply and second source
Have 2nKind voltage.
2. programmable voltage bias generator as described in claim 1, which is characterized in that the first resistor array, second
Electric resistance array to be formed by several connect in the resistance unit that ratio is decreased or increased, and the resistance unit quantity of first resistor,
The resistance unit quantity of second resistance and the quantity of register cell are all the same.
3. programmable voltage bias generator as claimed in claim 2, which is characterized in that the minimum of the first resistor array
Resistance value end is connected with the output end of the first power supply, maximum resistance value end and the second resistance array of the first resistor array
The connection of maximum resistance value end, the minimum resistance end of the second resistance array and the output end of second source connect.
4. programmable voltage bias generator as claimed in claim 3, which is characterized in that the first resistor array most
It is additionally provided with first resistor between small resistance value end and the output end of the first power supply, in the minimum resistance of the second resistance array
Second resistance is additionally provided between value end and the output end of second source.
5. programmable voltage bias generator as claimed in claim 4, which is characterized in that the first switch array, second
Switch arrays are sequentially connected with by several metal-oxide-semiconductor units, metal-oxide-semiconductor unit and the first resistor array of first switch array
Resistance unit is corresponding and quantity is identical, and the metal-oxide-semiconductor unit of second switch array is corresponding with the resistance unit of second resistance array simultaneously
Quantity is identical；The grid of each metal-oxide-semiconductor unit is connected with the output end of corresponding register cell respectively, each metal-oxide-semiconductor unit
Source electrode and drain electrode is connected with the both ends of corresponding resistance unit respectively；The on state of the metal-oxide-semiconductor unit of first switch array and the
The on state that two switch arrays correspond to metal-oxide-semiconductor unit is opposite.
6. programmable voltage bias generator as claimed in claim 5, which is characterized in that the first switch array is by several
PMOS tube unit is constituted, and second switch array is made of several NMOS tube units.
7. programmable voltage bias generator as claimed in claim 6, which is characterized in that the NMOS tube unit is deep N-well
Metal-oxide-semiconductor, the body end of each deep N-well metal-oxide-semiconductor are connected to the output end of second source, and the deep N-well end of each deep N-well metal-oxide-semiconductor is connected to
Together.
8. a kind of IC chip, which is characterized in that inclined including programmable voltage such as of any of claims 1-7
Set generator.
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| CN201711088269.XA CN107888181B (en) | 2017-11-07 | 2017-11-07 | Programmable voltage bias generator and IC chip comprising it |
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|---|---|---|---|
| CN201711088269.XA CN107888181B (en) | 2017-11-07 | 2017-11-07 | Programmable voltage bias generator and IC chip comprising it |
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| CN107888181B true CN107888181B (en) | 2019-03-05 |
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| CN109709862B (en) * | 2019-01-04 | 2021-05-07 | 华大半导体有限公司 | Programmable variable resistor |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104038231A (en) * | 2014-06-30 | 2014-09-10 | 中国电子科技集团公司第四十四研究所 | Nonlinear signal conversion circuit of CMOS image sensor |
| CN104750162A (en) * | 2013-12-31 | 2015-07-01 | 中芯国际集成电路制造(上海)有限公司 | Reference voltage generating circuit and reference voltage calibrating method |
| CN104767909A (en) * | 2015-04-15 | 2015-07-08 | 中国电子科技集团公司第四十四研究所 | Histogram equalization analog-digital conversion circuit of image sensor and method |
-
2017
- 2017-11-07 CN CN201711088269.XA patent/CN107888181B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104750162A (en) * | 2013-12-31 | 2015-07-01 | 中芯国际集成电路制造(上海)有限公司 | Reference voltage generating circuit and reference voltage calibrating method |
| CN104038231A (en) * | 2014-06-30 | 2014-09-10 | 中国电子科技集团公司第四十四研究所 | Nonlinear signal conversion circuit of CMOS image sensor |
| CN104767909A (en) * | 2015-04-15 | 2015-07-08 | 中国电子科技集团公司第四十四研究所 | Histogram equalization analog-digital conversion circuit of image sensor and method |
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