CN107871746A - 用于制造具有存储器单元的集成电路的方法 - Google Patents
用于制造具有存储器单元的集成电路的方法 Download PDFInfo
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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Abstract
本发明涉及用于制造具有存储器单元的集成电路的方法,其提供数种制造集成电路的方法。一种示范方法包括:图案化源极线光阻掩模以覆于衬底的源极线区上,同时暴露出漏极线区。该源极线区在第一及第二存储器单元之间,以及该漏极线区在该第二及第三存储器单元之间。源极线形成于该源极线区中。在形成覆于漏极线区上的漏极线电介质时,同时形成覆于该源极线上的源极线电介质。图案化漏极线光阻掩模以覆在活性区段中的该源极线上,同时暴露出在搭接区段中的该源极线,以及同时暴露出该漏极线区。移除在该漏极线区上面的该漏极线电介质,同时减少该源极线电介质在该搭接区段中的厚度。
Description
技术领域
本发明大体有关于制造具有存储器单元的集成电路的方法,且更特别的是,有关于制造具有存储器单元的集成电路的低成本方法。
背景技术
嵌入式超级闪存单元是使用于某些集成电路,在此可擦除及重新编程该等嵌入式超级闪存单元。超级闪存单元至少有三代,其中每一代比前一代小。第三代存储器单元包括有一堆迭,其中控制栅极覆于控制栅极电介质上,控制栅极电介质覆于浮动栅极上,而此浮动栅极覆于浮动栅极电介质上。整个堆迭覆于衬底上。
制造此类集成电路包括许多制程,例如光刻、蚀刻及沉积。光刻涉及沉积光阻层,接着是图案化该光阻层。通过透过具有透明区段及不透明区段的掩模而暴露于光线或其他电磁辐射,可图案化该光阻层。光线造成光阻的化学变化,由此可选择性移除暴露部分或者是非暴露部分。光刻技术很贵,因此包括较多光刻制程的集成电路制造技术会比有较少光刻制程者昂贵。
因此,最好提供有比传统制造方法还少的光刻制程的集成电路制造方法。此外,最好提供制造具有嵌入式超级闪存单元的集成电路的方法,同时相比于传统制造方法,可减少光刻制程数目。此外,由以下结合附图和本发明背景的详细说明及随附权利要求书可明白本发明具体实施例的其他合意特征及特性。
发明内容
提供数种制造集成电路的方法。一种示范方法包括:图案化源极线光阻掩模以覆于衬底的源极线区上,同时暴露出漏极线区。该源极线区在第一及第二存储器单元之间,以及该漏极线区在该第二及第三存储器单元之间。源极线形成于该源极线区中。在形成覆于漏极线区上的漏极线电介质时,同时形成覆于该源极线上的源极线电介质。图案化漏极线光阻掩模以覆在活性区段(active section)中的该源极线上,同时暴露出在搭接区段(strap section)中的该源极线,以及同时暴露出该漏极线区。移除在该漏极线区上面的该漏极线电介质,同时减少该源极线电介质在该搭接区段中的厚度。
在另一具体实施例中,提供一种制造集成电路的方法。该方法包括:图案化源极线光阻掩模以覆于漏极线区上和覆在该集成电路的搭接区段内的源极线区上,同时暴露在该集成电路的活性区段内的该源极线区。该源极线区在第一存储器单元与第二存储器单元之间,以及该漏极线区在该第二存储器单元与第三存储器单元之间。源极线形成于该活性区段的该源极线区中。漏极线电介质与源极线电介质同时形成,在此该源极线电介质覆在该活性区段及该搭接区段两者中的该源极线区上以及该漏极线电介质覆在该活性及该搭接区段两者中的该漏极线区上。形成覆于该源极线区及该漏极线区上的层间电介质,以及在该搭接区段中形成穿过该层间电介质至该源极线区的通孔。移除在该通孔内覆于该源极线区上的该源极线电介质,以及在该搭接区段中形成与该源极线区电性通讯的接触。
在又一具体实施例中,提供一种制造集成电路的方法。该方法包括:图案化源极线光阻掩模以上覆于漏极线区上,同时暴露出在该集成电路的活性区段内的源极线区,在此该源极线光阻掩模覆在搭接区段中的该源极线区上。该源极线区界定于在第一及第二存储器单元之间的衬底内,以及该漏极线区界定于在第二及第三存储器单元之间的该衬底内。源极线形成于在该集成电路的该活性区段内的该源极线区中。漏极线电介质与源极线电介质同时形成,在此该源极线电介质覆于该源极线区上以及该漏极线电介质覆于该漏极线区上。图案化一漏极线光阻掩模以覆在该活性区段中的该源极线上,同时暴露出在该搭接区段中的该源极线区,以及在此该漏极线光阻掩模暴露出在该集成电路的该活性及该搭接区段两者中的该漏极线区。移除在该漏极线区上面的该漏极线电介质,同时减少该源极线电介质在该搭接区段中的厚度。形成覆于该源极线区及该漏极线区上的层间电介质,以及在该搭接区段中形成与该源极线区电性通讯的接触。
附图说明
以下将结合附图来描述本发明的具体实施例,共同类似的元件用相同的附图标记表示。
图1至图7示集成电路及其制造的具体实施例,在此图1、图3、图5至图7的横截面图图示集成电路的搭接区段以及图2和图4为透视剖面图;以及
图8至图14图示集成电路及其制造的替代具体实施例,在此图8及图10至图14的横截面图图示集成电路的搭接区段以及图9为透视剖面图。
具体实施方式
以下实施方式本质上只是示范说明而非旨在限制各个具体实施例及其应用和用途。此外,不希望受限于在【先前技术】或【实施方式】中提到的任何理论。本揭示内容的具体实施例大体针对用于制造集成电路的方法。描述于本文的各种任务及制程步骤可加入有未详述于本文的额外步骤或机能的更广泛程序或制程。特别是,制造集成电路的各种步骤为众所周知,因此为了简明起见,本文只简述许多现有的步骤或整个省略而不提供现有的制程细节。
提供一种制造具有闪存单元的集成电路的方法,在此该等闪存单元可为第三代超级闪存单元。该集成电路用比传统制造方法有更少光刻制程的方式制造,在此描述于本文的制程差异考虑到去除至少一光刻步骤的可靠制造方法,如下述。请参考图示于图1的示范具体实施例,集成电路10包括含有半导体材料的衬底12。如本文所使用的,用语“半导体衬底”用来涵盖半导体工业现有用来制作电子装置的半导体材料。半导体材料包括单晶硅材料,例如常用于半导体工业的相对纯粹或轻浓度杂质掺杂的单晶硅材料,以及多晶硅材料和与其他元素混合的硅,例如锗、碳及其类似者。此外,“半导体材料”涵盖其他材料,相对纯粹或杂质掺杂的锗、砷化镓、氧化锌、玻璃及其类似者。如本文所指称的,基于材料的总重量,包括提及的元素/化合物的材料包括至少10重量%的提及元素/化合物,除非另有说明。在许多具体实施例中,衬底12主要包括单晶半导体材料。衬底12可为块硅晶圆(如图示)或可为在绝缘层上的一层薄硅(常被称为绝缘体上覆硅或SOI,未图示),接着用载体晶圆支承它。
多个浅沟槽隔离结构14可位于衬底12内,其中该等浅沟槽隔离结构14为电绝缘体。如本文所使用的,“电绝缘材料”或“电绝缘体”为电阻率约有1x104欧姆米或更多的材料,“导电材料”为电阻率约有1x10-4欧姆米或更少的材料,以及“半导电材料”为电阻率高于约1x10-4欧姆米至小于约1x104欧姆米的材料。在一示范具体实施例中,浅沟槽隔离结构14包括二氧化硅,但是在替代具体实施例中可为其他电绝缘材料。
多个存储器单元覆于衬底12及浅沟槽隔离结构14上,彼等包括第一存储器单元16、第二存储器单元18及第三存储器单元20。如本文所使用的,用语“覆于…上”意指“在…上方”使得中介层可在浅沟槽隔离结构14及存储器单元16、18、20之间,或意指“在…上面”,使得浅沟槽隔离结构14实体接触存储器单元16、18、20。此外,用语“直接覆于…上”意指穿过上组件的垂直线也穿过下组件,使得上组件的至少一部分直接在下组件的至少一部分上方。应了解,集成电路10可移动,由此改变相对“向上”及“向下”位置,因此“垂直”线是意指大约与衬底12表面垂直的直线。存储器单元16、18、20各自包括为电绝缘体的浮动栅极电介质24,其中浮动栅极电介质24覆于衬底12上且横向毗邻浅沟槽隔离侧表面22。在一示范具体实施例中,浮动栅极电介质24为二氧化硅,但是替代具体实施例可使用其他材料。同样地,各个存储器单元16、18、20的浮动栅极电介质24位在浅沟槽隔离结构14的两对边上。各个存储器单元16、18、20也包括直接覆于浮动栅极电介质24上的浮动栅极26,在此如同浮动栅极电介质24,浮动栅极26位在浅沟槽隔离结构14的两对边上。因此,浮动栅极26毗邻浅沟槽隔离侧表面22。浮动栅极26为导电材料,以及在一示范具体实施例中,可包括掺杂导电率决定性杂质(conductivity determining impurities)的多晶硅。
控制栅极电介质28直接且居中地覆于浮动栅极26和各个存储器单元16、18、20的浅沟槽隔离结构14上,在此控制栅极电介质28为电绝缘体。在一示范具体实施例中,控制栅极电介质28包括二氧化硅/氮化硅/二氧化硅三层(未个别图示),但是其他具体实施例也有可能。控制栅极30直接且居中地覆于控制栅极电介质28上,在此控制栅极30为电导体,例如具有导电率决定性杂质的多晶硅。硬掩模32直接覆于控制栅极30上,在此硬掩模32为电绝缘体,且在一示范具体实施例中,包括二氧化硅树脂。间隔体34可覆于浮动栅极26上且横向毗邻(i)控制栅极电介质28、(ii)控制栅极30及(iii)硬掩模32的两对边,在此间隔体34为电绝缘体。在一示范具体实施例中,间隔体34包括有不同电介质材料的多层,并且在任一存储器单元16、18、20的两对边上的间隔体34的层数及确切组合物可能并不完全相同。衬底12的源极线区36界定于第一及第二存储器单元16、18之间,以及衬底12的漏极线区38界定于第二及第三存储器单元18、20之间。即刻参考图2,源极线46形成于源极线区36的至少一部分内,以及漏极线(未图示于图1或图2)形成于漏极线区38的至少一部分内。
参考图2的示范具体实施例,在此图2为集成电路10的剖面透视图。多个存储器单元16、18、20的上半部各自直接覆在集成电路10的搭接区段40中的浅沟槽隔离结构14上,但是多个存储器单元16、18、20不直接覆在集成电路10的活性区段42中的浅沟槽隔离结构14(直接在活性区段42中的存储器单元16、18、20下方的衬底12并未图示)上。直接覆于浅沟槽隔离结构14上的多个存储器单元16、18、20的上半部包括控制栅极电介质28、控制栅极30及硬掩模32。搭接区段40用来电气连接至在不同存储器单元16、18、20之间形成于衬底12中的组件,如下所述,而活性区段42用来储存用于记忆目的的电荷。搭接区段40可与活性区段42不同,因为搭接区段40包括在多个存储器单元16、18、20的上半部下方的浅沟槽隔离结构14,而活性区段42不包括在多个存储器单元16、18、20下方的浅沟槽隔离结构14。
形成及图案化源极线光阻掩模44以暴露源极线区36同时覆盖漏极线区38。可用旋涂法(spin coating)沉积源极线光阻掩模44(及描述于下文的其他光阻层),以及通过透过具有透明区段及不透明区段的掩模暴露于光线或其他电磁辐射来图案化。光线造成光阻的化学变化,由此可选择性移除暴露部分或者是非暴露部分,如上述。所欲位置可用有机溶剂移除,而源极线光阻掩模44仍然覆于集成电路10的其他区域上。源极线光阻掩模44(及描述于下文的其他光阻层)可视需要包括上及/或下抗反射涂层及/或硬掩模(未图示)。
通过植入导电率决定性杂质于衬底12的暴露部分中,在源极线区36中形成源极线46于衬底12内。在一示范具体实施例中,该等导电率决定性杂质(亦即,“掺杂物”)可作为离子植入。离子植入涉及离子化所欲导电率决定性杂质以及在电场的影响下推送掺杂物离子进入衬底12。源极线光阻掩模44保护漏极线区38,因此漏极线区38在此时被保护免于植入导电率决定性离子。在图2的具体实施例中,源极线46形成于集成电路10的活性区段42中以及搭接区段40中。源极线光阻掩模44在源极线46形成之后形成,例如用含氧电浆或适当的溶剂。
在一示范具体实施例中,以及如图3所示,形成覆在第一及第二存储器单元16、18之间的源极线46上的源极线电介质48。漏极线电介质50与源极线电介质48同时形成,在此形成覆于漏极线区38上的漏极线电介质50。源极线电介质48和漏极线电介质50为电绝缘体,在有些具体实施例中,可用热氧化形成。在一些具体实施例中,源极线电介质48和漏极线电介质50包括二氧化硅,而源极线电介质48可比漏极线电介质50厚些。例如,在图示具体实施例中,源极线46有高于漏极线区38的导电率决定性杂质(亦即,掺杂物)浓度,而在有较高导电率决定性杂质浓度时,热氧化物的成长更快。源极线46有高于漏极线区38的导电率决定性杂质浓度,导致源极线电介质48比漏极线电介质50更厚。在一示范具体实施例中,源极线电介质48厚约400至约450埃(angstroms),以及漏极线电介质50厚约150至约300埃。
请参考图4的示范具体实施例,以及继续参考图3,形成及图案化覆于衬底12上的漏极线光阻掩模52。漏极线光阻掩模52被图案化成覆在活性区段42中的源极线46上并予以覆盖,同时暴露出漏极线区38中的漏极线电介质50,因此暴露出搭接及活性区段40、42两者中的漏极线电介质50。也图案化漏极线光阻掩模52以暴露出在搭接区段40中的源极线电介质48。移除覆在活性及搭接区段42、40中的漏极线区38上的漏极线电介质50,同时减少源极线电介质48在搭接区段40中的厚度。漏极线电介质50可用使用稀释氢氟酸的湿蚀刻移除,但是在替代具体实施例可使用反应离子蚀刻或其他蚀刻技术。进行漏极线电介质50的移除制程以移除漏极线电介质50,因此在漏极线电介质50都移除完毕时可终止移除制程,例如该移除制程在漏极线电介质50实质完全移除(如通过现有技术来决定)时立即停止。如此,较厚的源极线电介质48(相比于漏极线电介质50)在漏极线电介质50都移除完毕时可能没有被完全移除。在一示范具体实施例中,在漏极线电介质50被移除时,源极线电介质48减少到约150至约250埃的厚度,但是其他厚度也有可能。在有些具体实施例中,可完全移除源极线电介质48。
可能不需要使用专用于隔离及选择性暴露源极线电介质48的光刻技术,因为后续制程可移除搭接区段40中的源极线电介质48以促进电气连接,这在下文有更完整的描述。关于光刻技术是“专用的”是指除指定目的之外,特定光刻技术不使用于另一个目的,例如选择性暴露在搭接区段40中的源极线电介质48。排除隔离及选择性暴露源极线电介质48的独立专用光刻技术可降低制造成本,因为独立专用光刻制程的成本已经排除。
后续制程可进一步减薄及/或移除搭接区段40中的源极线电介质48。例如,如上述用于光阻材料的漏极线光阻掩模52在使用后移除。在一示范具体实施例中,漏极线光阻掩模52用溶剂清洗移除,以及添加热氨及水至溶剂清洗以进一步减薄源极线电介质48。添加热氨及水至溶剂清洗可进一步减薄源极线电介质48,例如到约50至约200埃的厚度,但是在有些具体实施例中,热氨及水可完全移除源极线电介质48在搭接区段40中的暴露部分。各种附加清洗技术及/或蚀刻技术可进一步减少或消除源极线电介质48,在此这些附加技术在集成电路10的制程中可使用于其他目的。
参考图5的示范具体实施例。形成覆于多个存储器单元16、18、20及在其间的衬底12上的层间电介质54,在此层间电介质54为电绝缘体。层间电介质54可包括可用使用硅烷及氧的化学气相沉积形成的二氧化硅,但是替代具体实施例可使用其他电绝缘材料。在图5的具体实施例中,源极线电介质48的薄层仍然覆于源极线46上,但是在替代具体实施例中,在形成层间电介质54之前,可完全移除在搭接区段40中的源极线46上面的源极线电介质48,如上述。
请参考图6,以及继续参考图5,形成穿过层间电介质54至源极线电介质48的通孔56。用硅化物预洁制程(silicide pre-cleaning process)或其他制程,可移除通孔56内的源极线电介质48。因此,移除在搭接区段40内的源极线电介质48的至少一部分,因为通孔56可能不暴露搭接区段40内的全部源极线电介质48。在源极线电介质48先前已被移除的具体实施例中,可通过光刻隔离通孔56的位置,然后蚀刻穿过层间电介质54至源极线电介质48或至源极线46的表面,从而形成通孔56。利用四氟化硅(silicon tetrafluoride)的反应离子蚀刻可用来蚀刻穿过层间电介质54以形成通孔56,但是替代具体实施例可使用许多其他蚀刻剂或蚀刻技术。该硅化物预洁制程可包括:用有机溶液漂洗,接着是稀释氢氟酸溶液,然后用去离子水漂洗及干燥。其他清洁具体实施例也有可能,例如将集成电路10浸入稀释氢氟酸,然后干燥。然后,集成电路10可视需要用溅射氩离子进一步清洁。硅化物预洁制程中的氢氟酸,或硅化物预洁制程的其他方面,可移除在通孔56内覆于源极线46上的源极线电介质48的任何其余部分。
在源极线电介质48移除后,在源极线46的暴露表面上形成硅化物58。在硅化物58形成后,形成通孔56中的接触60,如图7所示,以及继续参考图6。形成与搭接区段40中的源极线46电性通讯的接触60。可通过沉积一层金属(未个别图示),接着是退火制程,从而形成该硅化物。用溅镀或化学气相沉积可沉积该金属,例如镍、钛、钴或其他金属,而该金属在退火期间与可用硅反应以形成硅化物。不过,该金属不与电介质或其他材料反应。因此,移除覆在通孔56内的源极线46上的源极线电介质48是很重要的,因为如果源极线电介质48分离源极线46与沉积金属层,则硅化物58不会形成而且会危及接触60与源极线46之间的电气连接。一旦硅化物58形成,可移除来自该金属层(未图示)的覆盖层(overburden),例如有针对镍的硝酸、乙酸及硫酸混合物的湿蚀刻。可使用针对镍或用来形成硅化物58的其他金属的其他蚀刻剂。
接触60可包括可依序沉积的粘着层、阻障层及柱塞(未个别图示)。在一示范具体实施例中,由钛组成的粘着层是通过低压化学气相沉积五氯化钛而形成,由氮化钛组成的阻障层是通过化学气相沉积四溴化钛及氨而形成,以及由钨组成的柱塞是通过化学气相沉积六氟化钨及氢而形成。其他类型的接触也有可能,例如铜或其他导电材料。
即使没有使用专用于此移除的光刻技术,在硅化物58形成前,用于移除覆在搭接区段40内的源极线区36上的源极线电介质48的替代具体实施例也有可能。以下描述一个替代具体实施例,在此相同组件的附图标记以字首“1”差异化以区别上述具体实施例与以下所述的具体实施例。例如,图1至图7的衬底用附图标记12表示,以及图8至图14的衬底用附图标记112表示。上述具体实施例可与下述具体实施例结合,或者可使用任一具体实施例而不使用另一个,或以各种方式组合该等具体实施例的不同部分,但是在任何情形下不需要专用于移除在搭接区段40中的源极线区36上面的源极线电介质48的光刻技术。
请参考图8,描述于本文的第二具体实施例在制程与上述第一具体实施例的同一点处开始。请参考图9的示范具体实施例,形成及图案化源极线光阻掩模144以暴露在活性区段142内的源极线区136中的衬底112,同时覆盖在搭接及活性区段140、142两者中的漏极线区138内的衬底112。不过,源极线光阻掩模144被图案化成覆盖在搭接区段140中的源极线区136。如此,导电率决定性离子被植入于衬底112中以在集成电路110的活性区段142内形成源极线146于源极线区136内,但是植入近零的导电率决定性杂质于在集成电路110的搭接区段140内的源极线区136中的衬底112内。如此,在搭接区段140内,衬底112在源极线区136中与在漏极线区138中大约有浓度相同的导电率决定性杂质,但是在活性区段142中,衬底112在源极线146(它在源极线区136中)内有高于在漏极线区138内的导电率决定性杂质浓度。
源极线电介质148及漏极线电介质150在源极线光阻掩模144移除后形成,如图10的示范具体实施例所示以及继续参考图9。可通过热氧化衬底112而同时形成源极线电介质148与漏极线电介质150,如上述。在此具体实施例中,源极线电介质148的厚度与漏极线电介质150在搭接区段140中的厚度大约相同,例如在漏极线电介质150的厚度的约百分之10内。源极线区136中的衬底112与在集成电路110的搭接区段140内的漏极线区138中的衬底112大约有相同的导电率决定性杂质浓度,因此热氧化物在这两个位置以大约相同的速率成长。在一示范具体实施例中,在搭接区段140内的源极线电介质148在形成后有约150至约250埃的厚度,但是其他厚度也有可能。在图9及图10的具体实施例中,源极线电介质148在活性区段142中有大于在搭接区段140中的厚度。
请参考图11以及继续参考图9及图10,形成及图案化漏极线光阻掩模152以暴露出在漏极线区138中的衬底112。可图案化漏极线光阻掩模152以覆盖在搭接区段140中的源极线电介质148,如图11所示,因此源极线电介质148留在原位直到之后的制程。不过,在数个替代具体实施例中,可图案化漏极线光阻掩模152以暴露出在搭接区段140中的源极线电介质148,如先前在图4所示。在衬底112于形成源极、漏极线电介质148、150之前不植入导电率决定性杂质于搭接区段140中的具体实施例中,源极线电介质148比较薄,这与在源极线电介质148形成之前形成源极线46(图示于图2)的具体实施例相反。因此,在此情形下,在移除搭接区段140中的漏极线电介质150时,可能没有必要减少源极线电介质148的厚度。不过,上述技术可视需要用来在移除漏极线电介质150的同时移除或减少源极线电介质148的厚度。再者,如上述,不需要专用于移除源极线电介质148的光刻制程。
请参考图12,形成层间电介质154,如上述。然后,可形成通孔156,在一示范具体实施例中,如图13所示,以及导电率决定性杂质可植入于在第一及第二存储器单元116、118之间的衬底112中。导电率决定性杂质的增加浓度扩大源极线146,使得源极线146存在于搭接区段140中。搭接区段140中的源极线146有高于在植入导电率决定性杂质前的衬底112的导电率决定性杂质浓度,因此在搭接区段140中的源极线146有高于在植入导电率决定性杂质前的衬底112的导电率。如上述,可移除源极线电介质148存在于通孔156内的任何部分。
然后,可形成硅化物158及接触160,如图14所示以及另外参考图9,在此在搭接区段140内的接触160是与在搭接区段140内的源极线146电性通讯。描述于本文的具体实施例可具有变化例,包括用以减少及/或排除在搭接区段140内覆于衬底112的源极线电介质148上的清洗或蚀刻技术。
尽管以上实施方式已陈述至少两个示范具体实施例,然而应了解,仍然有许多变化例。也应了解,该等示范具体实施例只是范例而非旨在以任何方式限制本申请案的范畴、适用性或组态。反而,上述实施方式是要让所属领域技术人员有个方便的发展蓝图用来具体实作一或更多具体实施例,应了解,描述于一示范具体实施例的元件的功能及配置可做出各种改变而不脱离如随附权利要求书所述的范畴。
Claims (20)
1.一种制造集成电路的方法,包含下列步骤:
图案化源极线光阻掩模以覆于衬底的源极线区上,同时暴露该衬底的漏极线区,其中,该源极线区界定在第一存储器单元与第二存储器单元之间,以及其中,该漏极线区界定在该第二存储器单元与第三存储器单元之间;
形成源极线于该源极线区中;
同时形成源极线电介质与漏极线电介质,其中,该源极线电介质覆于该源极线上以及该漏极线电介质覆于该漏极线区上;
图案化漏极线光阻掩模以覆在该集成电路的活性区段中的该源极线上,其中,该漏极线光阻掩模暴露出在该集成电路的搭接区段中的该源极线,以及其中,该漏极线光阻掩模暴露出该漏极线区;以及
移除覆于该漏极线区上的该漏极线电介质,其中,在移除覆于该漏极线区的该漏极线电介质上时,减少该源极线电介质在该搭接区段中的厚度。
2.如权利要求1所述的方法,其中,图案化该源极线光阻掩模包含:图案化该源极线光阻掩模,其中,该第一存储器单元、该第二存储器单元及该第三存储器单元各自包含覆于该衬底上的浮动栅极,覆于该浮动栅极上的控制栅极电介质,以及覆于该控制栅极电介质上的控制栅极。
3.如权利要求2所述的方法,其中,图案化该源极线光阻掩模包含:图案化该源极线光阻掩模,其中,该第一存储器单元、该第二存储器单元及该第三存储器单元中的每一者直接覆于浅沟槽隔离结构上。
4.如权利要求3所述的方法,其中,图案化该源极线光阻掩模包含:图案化该源极线光阻掩模,其中,该第一存储器单元、该第二存储器单元及该第三存储器单元包含覆于该衬底上且直接在该浮动栅极下方的浮动栅极电介质,以及其中,该浮动栅极电介质毗邻该浅沟槽隔离结构。
5.如权利要求1所述的方法,更包含:
在减少该源极线电介质在该搭接区段中的厚度之后,移除覆于该搭接区段上的该源极线电介质的至少一部分。
6.如权利要求1所述的方法,其中:
形成覆于该源极线上的该源极线电介质同时形成覆于该漏极线区上的该漏极线电介质包含:形成该源极线电介质,在此该源极线电介质的该厚度大于该漏极线电介质的厚度。
7.如权利要求1所述的方法,更包含:
形成覆于该源极线及该漏极线区上的层间电介质;以及
形成与在该搭接区段中的该源极线电性通讯的接触,其中,在没有专用于移除覆在该搭接区段中的该源极线上的该源极线电介质的光刻步骤下,形成该接触。
8.如权利要求7所述的方法,更包含:
形成穿过该层间电介质的通孔,其中,该通孔直接覆在该搭接区段中的该源极线上。
9.如权利要求8所述的方法,更包含:
移除覆在该通孔内的该源极线上的该源极线电介质。
10.如权利要求8所述的方法,更包含:
在形成该接触之前,形成覆于该源极线上的硅化物于该通孔内。
11.一种制造集成电路的方法,包含:
图案化源极线光阻掩模以覆于漏极线区上,同时暴露在该集成电路的活性区段内的源极线区,其中,该源极线光阻掩模覆在该集成电路的搭接区段中的该源极线区上,其中,该源极线区在第一存储器单元与第二存储器单元之间的衬底内,以及其中,该漏极线区在该第二存储器单元与第三存储器单元之间的该衬底内;
形成源极线于该活性区段的该源极线区中;以及
同时形成源极线电介质与漏极线电介质,其中,该源极线电介质覆在该活性区段及该搭接区段两者中的该源极线区上,以及该漏极线电介质覆在该活性区段及该搭接区段两者中的该漏极线区上;
形成覆于该源极线区及该漏极线区上的层间电介质;
形成穿过该层间电介质至在该搭接区段中的该源极线区的通孔;
移除覆在该通孔内的该源极线区上的该源极线电介质;以及
形成与在该搭接区段中的该源极线区电性通讯的接触。
12.如权利要求11所述的方法,更包含:
通过在形成该接触之前植入导电率决定性杂质于通过该通孔暴露的该源极线区中,形成该源极线于该搭接区段中。
13.如权利要求11所述的方法,其中:
形成覆于该源极线上的该源极线电介质包含:形成该源极线电介质,其中,该源极线电介质的厚度在该漏极线电介质的厚度的约百分之10内。
14.如权利要求11所述的方法,其中,图案化该源极线光阻掩模包含:
图案化该源极线光阻掩模,其中,该第一存储器单元、该第二存储器单元及该第三存储器单元各自包含覆于该衬底上的浮动栅极,覆于该浮动栅极上的控制栅极电介质,以及覆于该控制栅极电介质上的控制栅极。
15.如权利要求14所述的方法,其中,图案化该源极线光阻掩模包含:图案化该源极线光阻掩模,其中,该第一存储器单元、该第二存储器单元及该第三存储器单元各自直接覆于浅沟槽隔离结构上。
16.如权利要求15所述的方法,其中,图案化该源极线光阻掩模包含:图案化该源极线光阻掩模,其中,该第一存储器单元、该第二存储器单元及该第三存储器单元各自包含覆于该衬底上且直接在该浮动栅极下方的浮动栅极电介质,以及其中,该浮动栅极电介质毗邻该浅沟槽隔离结构。
17.如权利要求15所述的方法,其中,形成与该搭接区段的该源极线区电性通讯的该接触包含:在没有专用于移除覆在该搭接区段内的该源极线区上的该源极线电介质的光刻步骤下,形成该接触。
18.一种制造集成电路的方法,包含:
图案化源极线光阻掩模以覆于漏极线区上,同时暴露出在该集成电路的活性区段内的源极线区,其中,该源极线光阻掩模覆在该集成电路的搭接区段中的该源极线区上,其中,该源极线区界定于在第一存储器单元与第二存储器单元之间的衬底内,其中,该漏极线区界定于在该第二存储器单元与第三存储器单元之间的该衬底内;
形成源极线于在该集成电路的该活性区段内的该源极线区中;
同时形成源极线电介质与漏极线电介质,其中,该源极线电介质覆于该源极线区上以及该漏极线电介质覆于该漏极线区上;
图案化漏极线光阻掩模以覆在该活性区段中的该源极线上,其中,该漏极线光阻掩模暴露出在该集成电路的该搭接区段中的该源极线区,以及其中,该漏极线光阻掩模暴露出在该集成电路的该活性区段及该搭接区段两者中的该漏极线区;
移除覆于该漏极线区上的该漏极线电介质,其中,在移除覆于该漏极线区上的该漏极线电介质时,减少该源极线电介质在该集成电路的该搭接区段的厚度;
形成覆于该源极线区及该漏极线区上的层间电介质;以及
形成与在该搭接区段中的该源极线区电性通讯的接触。
19.如权利要求18所述的方法,其中,图案化该源极线光阻掩模包含:图案化该源极线光阻掩模,其中,该第一存储器单元、该第二存储器单元及该第三存储器单元各自包含覆于该衬底上的浮动栅极,覆于该浮动栅极上的控制栅极电介质,以及覆于该控制栅极电介质上的控制栅极。
20.如权利要求19所述的方法,其中,图案化该源极线光阻掩模包含:图案化该源极线光阻掩模,其中,该第一存储器单元、该第二存储器单元及该第三存储器单元各自直接覆于浅沟槽隔离结构上。
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US15/278,112 US9929165B1 (en) | 2016-09-28 | 2016-09-28 | Method for producing integrated circuit memory cells with less dedicated lithographic steps |
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US20180090505A1 (en) | 2018-03-29 |
TWI635597B (zh) | 2018-09-11 |
CN107871746B (zh) | 2019-08-30 |
US9929165B1 (en) | 2018-03-27 |
TW201814889A (zh) | 2018-04-16 |
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