CN107871670B - 半导体器件及其制造方法 - Google Patents
半导体器件及其制造方法 Download PDFInfo
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- CN107871670B CN107871670B CN201710533705.3A CN201710533705A CN107871670B CN 107871670 B CN107871670 B CN 107871670B CN 201710533705 A CN201710533705 A CN 201710533705A CN 107871670 B CN107871670 B CN 107871670B
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- layer
- interlayer dielectric
- etch
- dielectric layer
- forming
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 28
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- 239000010410 layer Substances 0.000 claims abstract description 320
- 239000002184 metal Substances 0.000 claims abstract description 126
- 229910052751 metal Inorganic materials 0.000 claims abstract description 126
- 239000011229 interlayer Substances 0.000 claims abstract description 89
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 229910052710 silicon Inorganic materials 0.000 claims description 26
- 229910052785 arsenic Inorganic materials 0.000 claims description 25
- 229910052796 boron Inorganic materials 0.000 claims description 25
- 238000005530 etching Methods 0.000 claims description 25
- 229910052698 phosphorus Inorganic materials 0.000 claims description 25
- 229910052732 germanium Inorganic materials 0.000 claims description 24
- 229910052799 carbon Inorganic materials 0.000 claims description 22
- 229910052757 nitrogen Inorganic materials 0.000 claims description 16
- 238000005468 ion implantation Methods 0.000 claims description 6
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 6
- 239000000463 material Substances 0.000 description 10
- 239000007769 metal material Substances 0.000 description 6
- 238000009832 plasma treatment Methods 0.000 description 5
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 5
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- 125000004429 atom Chemical group 0.000 description 4
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- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
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- 238000005240 physical vapour deposition Methods 0.000 description 2
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- ITWBWJFEJCHKSN-UHFFFAOYSA-N 1,4,7-triazonane Chemical compound C1CNCCNCCN1 ITWBWJFEJCHKSN-UHFFFAOYSA-N 0.000 description 1
- 229910017107 AlOx Inorganic materials 0.000 description 1
- 229910017049 AsF5 Inorganic materials 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 229910004014 SiF4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910004166 TaN Inorganic materials 0.000 description 1
- DUMHRFXBHXIRTD-UHFFFAOYSA-N Tantalum carbide Chemical compound [Ta+]#[C-] DUMHRFXBHXIRTD-UHFFFAOYSA-N 0.000 description 1
- 229910010038 TiAl Inorganic materials 0.000 description 1
- 229910010037 TiAlN Inorganic materials 0.000 description 1
- 229910008482 TiSiN Inorganic materials 0.000 description 1
- 229910008599 TiW Inorganic materials 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- RBFQJDQYXXHULB-UHFFFAOYSA-N arsane Chemical compound [AsH3] RBFQJDQYXXHULB-UHFFFAOYSA-N 0.000 description 1
- 229910000070 arsenic hydride Inorganic materials 0.000 description 1
- YBGKQGSCGDNZIB-UHFFFAOYSA-N arsenic pentafluoride Chemical compound F[As](F)(F)(F)F YBGKQGSCGDNZIB-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 229940104869 fluorosilicate Drugs 0.000 description 1
- 229910052986 germanium hydride Inorganic materials 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- QRXWMOHMRWLFEY-UHFFFAOYSA-N isoniazide Chemical compound NNC(=O)C1=CC=NC=C1 QRXWMOHMRWLFEY-UHFFFAOYSA-N 0.000 description 1
- 229910052748 manganese Inorganic materials 0.000 description 1
- 125000004433 nitrogen atom Chemical group N* 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 239000003361 porogen Substances 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- ABTOQLMXBSRXSM-UHFFFAOYSA-N silicon tetrafluoride Chemical compound F[Si](F)(F)F ABTOQLMXBSRXSM-UHFFFAOYSA-N 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 229910003468 tantalcarbide Inorganic materials 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
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Abstract
在用于制造半导体器件的方法中,在衬底上方形成第一层间介电层。在第一层间介电层中形成第一凹槽。在第一凹槽中形成第一金属布线。第一抗蚀刻层形成在第一层间介电层的位于第一金属布线之间的表面中,而不形成在第一金属布线的上表面上。在第一抗蚀刻层上和第一金属布线的上表面上形成第一绝缘层。本发明实施例涉及半导体集成电路,更特别地涉及具有多金属布线层的半导体器件及其制造工艺。
Description
技术领域
本发明实施例涉及半导体集成电路,更特别地涉及具有多金属布线层的半导体器件及其制造工艺。
背景技术
随着半导体产业引入具有更高性能和更大功能的新一代集成电路(IC),形成IC的元件的密度增加,并且还采用了具有多金属布线层和多个介电(绝缘)层的金属布线结构。随着元件的密度增加以及元件的尺寸减小,一个金属层和下一个金属层之间的对准误差(重叠误差)将导致更多的问题。
发明内容
根据本发明的一个实施例,提供了一种用于制造半导体器件的方法,包括:在衬底上方形成第一层间介电层;在所述第一层间介电层中形成第一凹槽;在所述第一凹槽中形成第一金属布线;在所述第一层间介电层的位于所述第一金属布线之间的表面中形成第一抗蚀刻层,而不在所述第一金属布线的上表面上形成所述第一抗蚀刻层;以及在所述第一抗蚀刻层上和所述第一金属布线的所述上表面上形成第一绝缘层。
根据本发明的另一实施例,还提供了一种用于制造半导体器件的方法,包括:在衬底上方形成第一层间介电层;在所述第一层间介电层中形成第一凹槽;在所述第一凹槽中形成第一金属布线;在所述第一层间介电层的位于所述第一金属布线之间的表面中形成第一抗蚀刻层,而不在所述第一金属布线的上表面上形成所述第一抗蚀刻层;在所述第一抗蚀刻层上和所述第一金属布线的所述上表面上形成第一绝缘层;在所述第一绝缘层上形成第二层间介电层;在所述第二层间介质层中形成第二凹槽,从而暴露所述第一金属布线的所述上表面;以及在所述第二凹槽中形成第二金属布线。
根据本发明的又一实施例,还提供了一种半导体器件,包括:第一金属布线,形成在设置在衬底上方的第一层间介电层中;抗蚀刻层,形成在所述第一层间介电层的位于所述第一金属布线之间的表面中,而不形成在所述第一金属布线的上表面上;第一绝缘层,设置在所述抗蚀刻层上和所述第一金属布线的所述上表面上;第二层间介电层,设置在所述第一绝缘层上;以及第二金属布线,形成在所述第二层间介电层中,并分别连接至所述第一金属布线,其中,所述第二金属布线的底部与所述抗蚀刻层接触。
附图说明
当结合附图进行阅读时,从以下详细描述可最佳地理解本发明的各个方面。应该注意,根据工业中的标准实践,各个部件未按比例绘制。实际上,为了清楚的讨论,各种部件的尺寸可以被任意增大或减小。
图1至图10示出根据本发明的一个实施例的用于制造具有多金属布线结构的半导体器件的示例性顺序工艺。
图11示出半导体器件的对比例的截面图。
图12至图14示出根据本发明的另一实施例的用于制造具有多金属布线结构的半导体器件的示例性顺序工艺。
具体实施方式
应当理解,以下公开内容提供了许多用于实现本发明的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然,这些仅仅是实例,而不旨在限制本发明。例如,元件的尺寸不限于所公开的范围或值,但可能依赖于工艺条件和/或器件所需的性能。此外,在以下描述中,在第二部件上方或者上形成第一部件可以包括第一部件和第二部件以直接接触的方式形成的实施例,并且也可以包括在第一部件和第二部件之间可以形成额外的部件,从而使得第一部件和第二部件可以不直接接触的实施例。为了简化和清楚,可以以不同的尺寸任意地绘制各个部件。
而且,为了便于描述,在此可以使用诸如“在…下方”、“在…下面”、“下部”、“在…之上”、“上部”等空间相对术语以描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。除了图中所示的方位外,空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上),并且在此使用的空间相对描述符可以同样地作出相应的解释。另外,术语“由...制成”可以意为“包括”或者“由...组成”。
图1至图10是根据本发明的一个实施例示出的用于制造具有多金属布线结构的半导体器件的示例性顺序工艺的截面图。图1至图10示出用于制造形成在衬底之上的两个金属布线层(布线层级)的示例性顺序工艺。应当注意,金属布线层可以指横向延伸的金属布线、具有具有连接至上层或下层的通孔结构的金属布线和通孔结构一个或多个。尽管存在构成位于衬底和金属布线层之间的半导体器件(之后称为“下面的结构”)的诸如晶体管或其他元件(例如,接触件等)的核心结构,但为了简洁在图1至图10中省略了这些元件的详细图示。
如图1所示,在设置在衬底1上方的下面的结构5上方形成第一层间介电(ILD)层10。层间介电层还可称为金属间介电(IMD)层。在一些实施例中,第一ILD层10的厚度在从约100nm至约2000nm的范围内。例如,第一ILD层10由一个或多个低-k介电材料层制成。低-k介电材料具有小于约3.5的k-值(介电常数)并且可具有小于约2.5的k-值。在其他实施例中,第一ILD层10由氧化硅、氟硅酸盐玻璃(FSG)、硼磷硅酸盐玻璃(BPSG)或磷硅酸盐玻璃(PSG)制成。
用于第一ILD层10的低k材料包括Si、O、C和/或H的元素,诸如SiCOH和SiOC。诸如聚合物的有机材料可用于第一ILD层10。例如,第一ILD层10由含碳材料、有机-硅酸盐玻璃、含致孔剂的材料和/或它们的组合的一层或多层制成。在一些实施例中,第一ILD层10中还可包括氮。第一ILD层10可以是多孔层。在一个实施例中,第一ILD层10的密度小于约3g/cm3,在其他实施例中,第一ILD层10的密度小于约2.5g/cm3。例如,可通过使用等离子体增强化学汽相沉积(PECVD)、低压CVD(LPCVD)、原子层CVD(ALCVD)和/或旋涂技术形成第一ILD层10。在PECVD的情况下,在约25℃至约400℃的范围内的衬底温度处以及在小于100托的压力下沉积膜。
在一些实施例中,第一ILD层可以包括层间绝缘膜和布线间绝缘膜,从而使得金属布线主要形成在金属间绝缘膜中。层间绝缘膜可包括SiOC膜,并且布线间绝缘膜可包括TEOS(正硅酸乙酯)膜。
如图2所示,通过使用包括光刻和蚀刻工艺的图案化操作在第一ILD层10中形成第一凹槽15。在一些实施例中,可以在第一凹槽的底部处形成将连接至下面的结构的一个或多个元件的一个或多个贯通孔(接触孔)(未示出)。
在一些实施例中,可使用蚀刻停止层12,从而使得可限定凹槽15的底部。在这种情况下,第一ILD层10可以包括第一下ILD层10A和第一上ILD层10B,蚀刻停止层(ESL)12插在第一下ILD层10A和第一上ILD层10B之间。用于第一下ILD层10A和第一上ILD层10B的材料可相同或不同。如果未使用蚀刻停止层,则可通过控制凹槽蚀刻的蚀刻时间或蚀刻速率控制凹槽的深度。在本发明中,用于给定蚀刻工艺的蚀刻停止层不完全使蚀刻工艺停止在蚀刻停止层的表面处,而是可以被轻微蚀刻。然而,蚀刻停止层大致停止蚀刻工艺,从而使得例如在蚀刻停止层中不形成贯通孔。
如图3所示,在第一凹槽中形成金属材料以形成第一金属布线20。形成第一金属布线的操作包括镶嵌工艺。在镶嵌工艺中,在第一凹槽15中且在第一ILD层10的上表面上形成一层或多层金属材料,并且实施诸如化学机械抛光法和/或回蚀法的平坦化操作,以去除金属材料的形成在第一ILD层10的上表面上的部分。
通过CVD、物理汽相沉积(PVD)和/或电镀形成一层或多层金属材料。
用于第一金属布线20的金属材料是Al、Cu、Co、Mn、W、Ti、Ta、TiN、TaN、TiW、WN、TiAl、TiAlN、TaC、TaCN和TiSiN的一层或多层。例如,第一金属布线20可以包括由例如TiN和/或TaN制成的阻挡层以及由例如Cu或基于Cu的材料制成的主体层。
在形成第一金属布线20之后,改性第一ILD层10的上表面以形成抗蚀刻层30。可以通过将Si、C、N、B、P、As和Ge原子中的一个或多个引入到第一ILD层10的表面区域内来形成抗蚀刻层30。
在一个实施例中,利用离子注入法25将这种原子引入第一ILD层10的表面区域内。在一些实施例中,离子注入的加速能量在约1keV至约10keV的范围内,并且剂量的量在约1×105cm-2至约1×1020cm-2的范围内,以提供抗蚀刻层30中的掺杂剂浓度在从约1×105cm-3至约1×1020cm-3的范围内。
抗蚀刻层30的密度高于第一ILD层10的密度。在一个实施例中,抗蚀刻层30的密度等于或大于约2.5g/cm3,在其他实施例中,该密度大于约3.0g/cm3。在特定实施例中,抗蚀刻层30的密度等于或大于约3.5g/cm3。
在其他实施例中,实施等离子体处理以将原子引入第一ILD层10的上表面内。例如,氨(NH3)和/或氮(N2)可以用作用于引入氮原子的等离子体处理的源气体。等离子体处理可以包括在约100℃至约400℃的温度处以及在小于100托的压力下的直接等离子体或远程等离子体。在其他实施例中,使用BF3、B2H6、PH3、AsH3、AsF5、SiF4、CO、CO2或GeH4中的一种或多种作为用于引入相应原子的等离子体处理的源气体。
通过等离子体处理,将第一ILD层10的上表面的约5nm至30nm的深度的部分改性为抗蚀刻层30。在一些实施例中,抗蚀刻层的厚度在从约10nm至约20nm的范围内。如图4所示,抗蚀刻层30形成在第一ILD层10的位于第一金属布线20之间的上表面处,而不是在第一金属布线20上方。
应当注意,可以基于形成在抗蚀刻层30上方的作为蚀刻停止层的第一绝缘层40的材料来选择要引入到第一ILD层10的表面区域中的元素,从而使得在抗蚀刻层30和第一绝缘层40之间的蚀刻速率(或电阻率)的差异足够大。
如图5所示,在形成抗蚀刻层30之后,在第一金属布线20和抗蚀刻层30上方形成第一绝缘层40。第一绝缘层40用作第一蚀刻停止层。
第一绝缘层40包括基于Si的绝缘材料(包括具有O、N、C、B和或H的Si)或Al基的绝缘材料(包括具有O、N、C、B和/或H的Al)的一层或多层。第一绝缘层的实例包括SiN、SiCN、SiC、SiCON、AlOx、AlNx和AlNxOy。在一些实施例中,第一绝缘层的介电常数在约4至约10的范围内。
在一些实施例中,第一绝缘层40的厚度在约1nm至约50nm的范围内,并且在其他的实施例中,该厚度在约5nm至约30nm的范围内。在一个实施例中,第一绝缘层40的密度小于约3g/cm3,在其他实施例中,第一绝缘层10的密度小于约2.5g/cm3。
可以通过使用例如PECVD、LPCVD、ALCVD和/或旋涂技术来形成第一绝缘层40。在PECVD的情况下,在约25℃至约400℃的范围内的衬底温度处以及在小于100托的压力下沉积第一绝缘层40。
如图6所示,在形成第一绝缘层40之后,在第一绝缘层40上方形成第二ILD层50。可以通过与第一ILD层10类似的材料和方法形成第二ILD层50。在一些实施例中,第二ILD层50的厚度在从约100nm至约2000nm的范围内。
然后,如图7所示,通过使用包括光刻和蚀刻工艺的图案化操作,在第二ILD层50中形成一个或多个第二凹槽55。如图7所示,在蚀刻工艺中,在第一绝缘层(蚀刻停止层)40处大致停止蚀刻。
随后,如图8A所示,进一步蚀刻第一绝缘层(蚀刻停止层)40以暴露第一金属布线20的表面。在图8A中,第二凹槽55与第一金属布线20大致对准。因此,在第一金属布线的上表面上设置凹槽的整个底部。
相比之下,在图8B中,在第二凹槽和第一金属布线20之间存在重叠误差或对准误差。因此,第二凹槽的底部的部分不设置在第一金属布线的上表面上,即,在第二凹槽的底部中暴露抗蚀刻层30的部分。然而,由于抗蚀刻层30形成在第一金属布线的侧部处,因此在蚀刻第一绝缘层40期间,蚀刻大致停止在抗蚀刻层30处。
如果没有形成抗蚀刻层30,则部分地蚀刻第一ILD层10以形成齿状凹坑62,如图11所示,这可能导致诸如低的器件可靠性或短路的各种问题。
如上所述,用于第一绝缘层40的第一绝缘层40的蚀刻中的蚀刻速率充分高于用于抗蚀刻层30的蚀刻速率。在一些实施例中,用于第一绝缘层40的第一绝缘层40的蚀刻中的蚀刻速率是抗蚀刻层30的蚀刻速率的约4倍至约20倍。
当第一绝缘层40由SiN制成时,要注入到第一ILD层的表面内的元素是Si、C、B、P、As和Ge中的一种或多种。当第一绝缘层40由SiC制成时,要注入到第一ILD层的表面内的元素是Si、N、B、P、As和Ge中的一种或多种。当第一绝缘层40由SiCN、SiON或SiOCN制成时,要注入到第一ILD层的表面内的元素是Si、B、P、As和Ge中的一种或多种。
如图9所示,在暴露第一金属布线20的上表面之后,通过使用与第一金属布线20的形成类似的材料和方法在第二凹槽55中形成第二金属布线60。
类似于关于图4所解释的操作,如图10所示,在第二ILD层50的位于第二金属布线60之间的上部区域中形成第二抗蚀刻层70。如图10所示,第二布线60的上部和底部分别与抗蚀刻层70和30接触。此外,第二金属布线60的底部不与抗蚀刻层30下面的第一ILD层10接触。当然,如果在第二凹槽55和第一金属布线20之间没有重叠误差,如图8所示,第二布线60的底部不与抗蚀刻层30接触。
通过重复图5至图9所解释的操作,可以获得多金属层结构。
图12至图14示出根据本发明的另一实施例的用于制造具有多金属布线结构的半导体器件的示例性顺序工艺。应当理解,可以在图12至图14所示的工艺之前、期间和之后提供额外的操作,并且在该方法的额外的实施例中,可以替代或消除下文中描述的一些操作。可互换操作/工艺的顺序。此外,与上述实施例相同或相似的操作、工艺、配置或材料可以应用于本实施例,并且可以省略其详细说明。
类似于图1,在设置在衬底上方的下面的结构上方形成第一层间介电(ILD)层10。然后,如图12所示,在第一ILD层10的上表面上方形成抗蚀刻层30'。
通过与抗蚀刻层30类似的材料和方法形成抗蚀刻层30'。在一些实施例中,抗蚀刻层30'的厚度在约0.5nm至约30nm的范围内,并且在其他的实施例中,该厚度在约10nm至约20nm的范围内。
如图13所示,通过使用包括光刻和蚀刻工艺的图案化操作,在第一ILD层10和抗蚀刻层30'中形成第一凹槽15'。
类似于图3,如图14所示,在第一凹槽中形成金属材料以形成金属布线20。类似于图3,形成金属布线的操作包括镶嵌工艺。通过该操作,可以获得类似于图4的结构。
在获得图12所示的结构之后,实施与图5至图9(或5-10)相同或相似的操作,以获得具有多金属布线结构的半导体器件。
本文描述的各个实施例或实例提供优于现有技术的一些优势。例如,在本发明中,由于在第一金属布线的侧部处形成抗蚀刻层,因此在第一绝缘层的蚀刻期间,蚀刻大致停止在抗蚀刻层处,这可以防止部分蚀刻第一ILD层。因此,可以改进半导体器件的可靠性。
应当理解,在此不必讨论所有优势,没有特定的优势是所有实施例或实例都必需的,并且其他实施例或实例可提供不同的优势。
根据本发明的一个方面,在用于制造半导体器件的方法中,在衬底上方形成第一层间介电层。在第一层间介电层中形成第一凹槽。在第一凹槽中形成第一金属布线。第一抗蚀刻层形成在第一层间介电层的位于第一金属布线之间的表面中,而不形成在第一金属布线的上表面上。在第一抗蚀刻层上和第一金属布线的上表面上形成第一绝缘层。
根据本发明的另一方面,在制造半导体器件的方法中,在衬底上方形成第一层间介电层。在第一层间介电层中形成第一凹槽。在第一凹槽中形成第一金属布线。第一抗蚀刻层形成在第一层间介电层的位于第一金属布线之间的表面中,而不形成在第一金属布线的上表面上。在第一抗蚀刻层上和第一金属布线的上表面上形成第一绝缘层。在第一绝缘层上形成第二层间介电层。在第二层间介电层中形成第二凹槽,从而使得暴露第一金属布线的上表面。在第二凹槽中形成第二金属布线。
根据本发明的另一方面,一种半导体器件包括:第一金属布线,形成在设置在衬底上方的第一层间介电层中;以及抗蚀刻层,形成在第一层间介电层的位于第一金属布线之间的表面中,而不形成在第一金属布线的上表面上。第一绝缘层设置在第一抗蚀刻层上且在第一金属布线的上表面上,以及第二层间介电层设置在第一绝缘层上。第二金属布线形成在第二层间介电层中,并分别连接至第一金属布线。第二金属布线的底部与抗蚀刻层接触。
根据本发明的一个实施例,提供了一种用于制造半导体器件的方法,包括:在衬底上方形成第一层间介电层;在所述第一层间介电层中形成第一凹槽;在所述第一凹槽中形成第一金属布线;在所述第一层间介电层的位于所述第一金属布线之间的表面中形成第一抗蚀刻层,而不在所述第一金属布线的上表面上形成所述第一抗蚀刻层;以及在所述第一抗蚀刻层上和所述第一金属布线的所述上表面上形成第一绝缘层。
在上述方法中,所述抗蚀刻层的厚度在从10nm至20nm的范围内。
在上述方法中,形成所述第一抗蚀刻层包括将所述第一层间介电层的所述表面改性为具有比所述第一层间介电层更高的密度。
在上述方法中,所述第一抗蚀刻层的密度等于或大于2.5g/cm3。
在上述方法中,形成所述第一抗蚀刻层包括通过离子注入法将Si、C、N、B、P、As和Ge中的一种或多种引入至所述第一层间介电层内。
在上述方法中,形成所述第一抗蚀刻层包括通过使用等离子体辐射将Si、C、N、B、P、As和Ge中的一种或多种引入至所述第一层间介电层内。
在上述方法中,其中:所述第一绝缘层由SiN制成,以及将Si、C、B、P、As和Ge中的一种或多种注入到所述第一层间介电层内。
在上述方法中,其中:所述第一绝缘层由SiC制成,以及将Si、N、B、P、As和Ge中的一种或多种注入到所述第一层间介电层内。
在上述方法中,其中:所述第一绝缘层由SiCN、SiON或SiOCN制成,以及将Si、B、P、As和Ge中的一种或多种注入到所述第一层间介电层内。
在上述方法中,将Si、C、B、P、As或Ge中的一种或多种注入到所述第一层间介电层内。
根据本发明的另一实施例,还提供了一种用于制造半导体器件的方法,包括:在衬底上方形成第一层间介电层;在所述第一层间介电层中形成第一凹槽;在所述第一凹槽中形成第一金属布线;在所述第一层间介电层的位于所述第一金属布线之间的表面中形成第一抗蚀刻层,而不在所述第一金属布线的上表面上形成所述第一抗蚀刻层;在所述第一抗蚀刻层上和所述第一金属布线的所述上表面上形成第一绝缘层;在所述第一绝缘层上形成第二层间介电层;在所述第二层间介质层中形成第二凹槽,从而暴露所述第一金属布线的所述上表面;以及在所述第二凹槽中形成第二金属布线。
在上述方法中:当形成所述第二凹槽时,在所述第二凹槽的底部处暴露所述第一抗蚀刻层的部分,以及所述第二金属布线的底部与所述第一抗蚀刻层接触。
在上述方法中,还包括:在所述第二层间介电层的位于所述第二金属布线之间的表面中形成第二抗蚀刻层,而不在所述第二金属布线的上表面上形成所述第二抗蚀刻层,其中,所述第二金属布线的上部与所述第二抗蚀刻层接触。
在上述方法中,所述第二金属布线的所述底部不接触位于所述第一抗蚀刻层下方的所述第一层间介电层。
在上述方法中,形成所述第一抗蚀刻层包括通过离子注入法将Si、C、N、B、P、As和Ge中的一种或多种引入至所述第一层间介电层内。
在上述方法中,其中:所述第一绝缘层由SiN制成,以及将Si、C、B、P、As和Ge中的一种或多种注入到所述第一层间介电层内。
在上述方法中,其中:所述第一绝缘层由SiC制成,以及将Si、N、B、P、As和Ge中的一种或多种注入到所述第一层间介电层内。
在上述方法中,其中:所述第一绝缘层由SiCN、SiON或SiOCN制成,以及将Si、B、P、As和Ge中的一种或多种注入到所述第一层间介电层内。
在上述方法中,其中:在形成所述第二凹槽中,蚀刻所述第二层间介电层,并且所述第二层间介电层的所述蚀刻停止在所述第一绝缘层处,然后,蚀刻所述第一绝缘层以暴露所述第一金属布线的所述上表面。
根据本发明的又一实施例,还提供了一种半导体器件,包括:第一金属布线,形成在设置在衬底上方的第一层间介电层中;抗蚀刻层,形成在所述第一层间介电层的位于所述第一金属布线之间的表面中,而不形成在所述第一金属布线的上表面上;第一绝缘层,设置在所述抗蚀刻层上和所述第一金属布线的所述上表面上;第二层间介电层,设置在所述第一绝缘层上;以及第二金属布线,形成在所述第二层间介电层中,并分别连接至所述第一金属布线,其中,所述第二金属布线的底部与所述抗蚀刻层接触。
上面概述了若干实施例的特征,使得本领域技术人员可以更好地理解本发明的各方面。本领域技术人员应该理解,他们可以容易地使用本发明作为基础来设计或修改用于实施与在此所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到,这种等同构造并不背离本发明的精神和范围,并且在不背离本发明的精神和范围的情况下,在此他们可以做出多种变化、替换以及改变。
Claims (16)
1.一种用于制造半导体器件的方法,包括:
在衬底上方形成第一层间介电层;
在所述第一层间介电层中形成第一凹槽;
在所述第一凹槽中形成第一金属布线;
在所述第一层间介电层的位于所述第一金属布线之间的表面中形成第一抗蚀刻层,而不在所述第一金属布线的上表面上形成所述第一抗蚀刻层;以及
在所述第一抗蚀刻层上和所述第一金属布线的所述上表面上形成第一绝缘层;
其中,形成所述第一抗蚀刻层包括通过离子注入法将Si、C、N、B、P、As和Ge中的一种或多种引入至所述第一层间介电层内,或通过使用等离子体辐射将Si、C、B、P、As和Ge中的一种或多种引入至所述第一层间介电层内,
在所述第一绝缘层的蚀刻中,所述第一绝缘层的蚀刻速率是第一抗蚀刻层的蚀刻速率的4倍至20倍。
2.根据权利要求1所述的方法,其中,所述第一抗蚀刻层的厚度在从10nm至20nm的范围内。
3.根据权利要求1所述的方法,其中,形成所述第一抗蚀刻层包括将所述第一层间介电层的所述表面改性为具有比所述第一层间介电层更高的密度。
4.根据权利要求3所述的方法,其中,所述第一抗蚀刻层的密度等于或大于2.5g/cm3。
5.根据权利要求1所述的方法,其中:
所述第一绝缘层由SiN制成,以及
将Si、C、B、P、As和Ge中的一种或多种注入到所述第一层间介电层内。
6.根据权利要求1所述的方法,其中:
所述第一绝缘层由SiC制成,以及
将Si、N、B、P、As和Ge中的一种或多种注入到所述第一层间介电层内。
7.根据权利要求1所述的方法,其中:
所述第一绝缘层由SiCN、SiON或SiOCN制成,以及
将Si、B、P、As和Ge中的一种或多种注入到所述第一层间介电层内。
8.一种用于制造半导体器件的方法,包括:
在衬底上方形成第一层间介电层;
在所述第一层间介电层中形成第一凹槽;
在所述第一凹槽中形成第一金属布线;
在所述第一层间介电层的位于所述第一金属布线之间的表面中形成第一抗蚀刻层,而不在所述第一金属布线的上表面上形成所述第一抗蚀刻层;
在所述第一抗蚀刻层上和所述第一金属布线的所述上表面上形成第一绝缘层;
在所述第一绝缘层上形成第二层间介电层;
在所述第二层间介电层中形成第二凹槽,从而暴露所述第一金属布线的所述上表面;以及
在所述第二凹槽中形成第二金属布线;
其中,形成所述第一抗蚀刻层包括通过离子注入法将Si、C、N、B、P、As和Ge中的一种或多种引入至所述第一层间介电层内,或通过使用等离子体辐射将Si、C、N、B、P、As和Ge中的一种或多种引入至所述第一层间介电层内,
在蚀刻形成所述第二凹槽的过程中,所述第一绝缘层的蚀刻速率是第一抗蚀刻层的蚀刻速率的4倍至20倍。
9.根据权利要求8所述的方法,其中:
当形成所述第二凹槽时,在所述第二凹槽的底部处暴露所述第一抗蚀刻层的部分,以及
所述第二金属布线的底部与所述第一抗蚀刻层接触。
10.根据权利要求9所述的方法,还包括:
在所述第二层间介电层的位于所述第二金属布线之间的表面中形成第二抗蚀刻层,而不在所述第二金属布线的上表面上形成所述第二抗蚀刻层,
其中,所述第二金属布线的上部与所述第二抗蚀刻层接触。
11.根据权利要求10所述的方法,其中,所述第二金属布线的所述底部不接触位于所述第一抗蚀刻层下方的所述第一层间介电层。
12.根据权利要求8所述的方法,其中:
所述第一绝缘层由SiN制成,以及
将Si、C、B、P、As和Ge中的一种或多种注入到所述第一层间介电层内。
13.根据权利要求8所述的方法,其中:
所述第一绝缘层由SiC制成,以及
将Si、N、B、P、As和Ge中的一种或多种注入到所述第一层间介电层内。
14.根据权利要求8所述的方法,其中:
所述第一绝缘层由SiCN、SiON或SiOCN制成,以及
将Si、B、P、As和Ge中的一种或多种注入到所述第一层间介电层内。
15.根据权利要求8所述的方法,其中:
在形成所述第二凹槽中,蚀刻所述第二层间介电层,并且所述第二层间介电层的所述蚀刻停止在所述第一绝缘层处,
然后,蚀刻所述第一绝缘层以暴露所述第一金属布线的所述上表面。
16.一种半导体器件,包括:
第一金属布线,形成在设置在衬底上方的第一层间介电层中;
抗蚀刻层,形成在所述第一层间介电层的位于所述第一金属布线之间的表面中,而不形成在所述第一金属布线的上表面上;
第一绝缘层,设置在所述抗蚀刻层上和所述第一金属布线的所述上表面上;
第二层间介电层,设置在所述第一绝缘层上;以及
第二金属布线,形成在所述第二层间介电层中,并分别连接至所述第一金属布线,
其中,所述第二金属布线的底部与所述抗蚀刻层接触,所述抗蚀刻层包括Si、C、B、P、As和Ge中的一种或多种,其浓度高于所述第一层间介电层,
所述第一绝缘层的蚀刻速率是所述抗蚀刻层的蚀刻速率的4倍至20倍。
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US9905456B1 (en) | 2016-09-26 | 2018-02-27 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and manufacturing method thereof |
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US11195724B1 (en) | 2020-07-01 | 2021-12-07 | Nanya Technology Corporation | Method of manufacturing semiconductor structure |
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US9905456B1 (en) | 2018-02-27 |
TWI637475B (zh) | 2018-10-01 |
DE102017117962A1 (de) | 2018-03-29 |
KR20180034221A (ko) | 2018-04-04 |
US10157782B2 (en) | 2018-12-18 |
US20180166332A1 (en) | 2018-06-14 |
TW201814860A (zh) | 2018-04-16 |
US10651079B2 (en) | 2020-05-12 |
US20200243378A1 (en) | 2020-07-30 |
KR102036827B1 (ko) | 2019-10-25 |
US11232978B2 (en) | 2022-01-25 |
CN107871670A (zh) | 2018-04-03 |
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